diff --git a/.forgejo/workflows/test.yml b/.forgejo/workflows/test.yml index 001168f..b7b1924 100644 --- a/.forgejo/workflows/test.yml +++ b/.forgejo/workflows/test.yml @@ -16,6 +16,9 @@ jobs: - uses: https://git.libre-chip.org/mirrors/rust-cache@v2 with: save-if: ${{ github.ref == 'refs/heads/master' }} + - run: rustup override set 1.93.0 + - run: rustup component add rust-src + - run: make -C rocq-demo - run: cargo test - run: cargo build --tests --features=unstable-doc - run: cargo test --doc --features=unstable-doc diff --git a/Cargo.lock b/Cargo.lock index be5f3bc..9177305 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -319,10 +319,12 @@ dependencies = [ "jobslot", "num-bigint", "num-traits", + "once_cell", "ordered-float", "petgraph", "serde", "serde_json", + "sha2", "tempfile", "trybuild", "vec_map", @@ -521,9 +523,9 @@ dependencies = [ [[package]] name = "once_cell" -version = "1.19.0" +version = "1.21.3" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "3fdb12b2476b595f9358c5161aa467c2438859caa136dec86c26fdd2efe17b92" +checksum = "42f5e15c9953c5e4ccceeb2e7382a716482c34515315f7b03532b8b4e8393d2d" [[package]] name = "ordered-float" diff --git a/Cargo.toml b/Cargo.toml index 2380ea7..504d90f 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -11,7 +11,7 @@ edition = "2024" repository = "https://git.libre-chip.org/libre-chip/fayalite" keywords = ["hdl", "hardware", "semiconductors", "firrtl", "fpga"] categories = ["simulation", "development-tools", "compilers"] -rust-version = "1.89.0" +rust-version = "1.93.0" [workspace.dependencies] fayalite-proc-macros = { version = "=0.3.0", path = "crates/fayalite-proc-macros" } @@ -30,6 +30,7 @@ indexmap = { version = "2.5.0", features = ["serde"] } jobslot = "0.2.23" num-bigint = "0.4.6" num-traits = "0.2.16" +once_cell = "1.21.3" ordered-float = { version = "5.1.0", features = ["serde"] } petgraph = "0.8.1" prettyplease = "0.2.20" diff --git a/crates/fayalite-proc-macros-impl/src/fold.rs b/crates/fayalite-proc-macros-impl/src/fold.rs index 22e7b82..50423b5 100644 --- a/crates/fayalite-proc-macros-impl/src/fold.rs +++ b/crates/fayalite-proc-macros-impl/src/fold.rs @@ -257,5 +257,6 @@ no_op_fold!(syn::Token![let]); no_op_fold!(syn::Token![mut]); no_op_fold!(syn::Token![static]); no_op_fold!(syn::Token![struct]); +no_op_fold!(syn::Token![type]); no_op_fold!(syn::Token![where]); no_op_fold!(usize); diff --git a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs index 97fa3ff..f7ad68d 100644 --- a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs +++ b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs @@ -3,8 +3,9 @@ use crate::{ Errors, HdlAttr, PairsIterExt, hdl_type_common::{ - ItemOptions, MakeHdlTypeExpr, MaybeParsed, ParsedField, ParsedFieldsNamed, ParsedGenerics, - SplitForImpl, TypesParser, WrappedInConst, common_derives, get_target, + CustomDebugOptions, CustomDebugTrait, ItemOptions, MakeHdlTypeExpr, MaybeParsed, + ParsedField, ParsedFieldsNamed, ParsedGenerics, SplitForImpl, TypesParser, WrappedInConst, + common_derives, create_struct_debug_impl, get_target, }, kw, }; @@ -30,6 +31,7 @@ pub(crate) struct ParsedBundle { pub(crate) fields: MaybeParsed, pub(crate) field_flips: Vec>>, pub(crate) mask_type_ident: Ident, + pub(crate) mask_type_name: String, pub(crate) mask_type_match_variant_ident: Ident, pub(crate) mask_type_sim_value_ident: Ident, pub(crate) match_variant_ident: Ident, @@ -88,6 +90,8 @@ impl ParsedBundle { no_runtime_generics: _, cmp_eq: _, ref get, + custom_debug: _, + custom_sim_display: _, } = options.body; if let Some((get, ..)) = get { errors.error(get, "#[hdl(get(...))] is not allowed on structs"); @@ -131,6 +135,7 @@ impl ParsedBundle { fields, field_flips, mask_type_ident: format_ident!("__{}__MaskType", ident), + mask_type_name: format!("MaskType<{}>", ident), mask_type_match_variant_ident: format_ident!("__{}__MaskType__MatchVariant", ident), mask_type_sim_value_ident: format_ident!("__{}__MaskType__SimValue", ident), match_variant_ident: format_ident!("__{}__MatchVariant", ident), @@ -448,6 +453,7 @@ impl ToTokens for ParsedBundle { fields, field_flips, mask_type_ident, + mask_type_name, mask_type_match_variant_ident, mask_type_sim_value_ident, match_variant_ident, @@ -464,11 +470,20 @@ impl ToTokens for ParsedBundle { no_runtime_generics, cmp_eq, get: _, + custom_debug: _, + custom_sim_display, } = &options.body; + let CustomDebugOptions { + type_: custom_debug_type, + sim: custom_debug_sim, + mask_type: custom_debug_mask_type, + mask_sim: custom_debug_mask_sim, + } = options.body.custom_debug(); let target = get_target(target, ident); + let struct_name = ident.to_string(); let mut item_attrs = attrs.clone(); - item_attrs.push(common_derives(span)); - ItemStruct { + item_attrs.push(common_derives(span, false)); + let type_struct = ItemStruct { attrs: item_attrs, vis: vis.clone(), struct_token: *struct_token, @@ -476,8 +491,8 @@ impl ToTokens for ParsedBundle { generics: generics.into(), fields: Fields::Named(fields.clone().into()), semi_token: None, - } - .to_tokens(tokens); + }; + type_struct.to_tokens(tokens); let (impl_generics, type_generics, where_clause) = generics.split_for_impl(); if let (MaybeParsed::Parsed(generics), MaybeParsed::Parsed(fields), None) = (generics, fields, no_runtime_generics) @@ -503,6 +518,9 @@ impl ToTokens for ParsedBundle { } let mut wrapped_in_const = WrappedInConst::new(tokens, span); let tokens = wrapped_in_const.inner(); + if custom_debug_type.is_none() { + create_struct_debug_impl(&type_struct, &struct_name, None).to_tokens(tokens); + } let builder = Builder { vis: vis.clone(), struct_token: *struct_token, @@ -530,9 +548,9 @@ impl ToTokens for ParsedBundle { mask_type_builder.to_tokens(tokens); let unfilled_mask_type_builder_ty = mask_type_builder.builder_struct_ty(|_| BuilderFieldState::Unfilled); - ItemStruct { + let mask_type_struct = ItemStruct { attrs: vec![ - common_derives(span), + common_derives(span, false), parse_quote_spanned! {span=> #[allow(non_camel_case_types, dead_code)] }, @@ -543,17 +561,20 @@ impl ToTokens for ParsedBundle { generics: generics.into(), fields: Fields::Named(mask_type_fields.clone()), semi_token: None, + }; + mask_type_struct.to_tokens(tokens); + if custom_debug_mask_type.is_none() { + create_struct_debug_impl(&mask_type_struct, mask_type_name, None).to_tokens(tokens); } - .to_tokens(tokens); let mut mask_type_match_variant_fields = mask_type_fields.clone(); for Field { ty, .. } in &mut mask_type_match_variant_fields.named { *ty = parse_quote_spanned! {span=> ::fayalite::expr::Expr<#ty> }; } - ItemStruct { + let mask_type_match_variant_struct = ItemStruct { attrs: vec![ - common_derives(span), + common_derives(span, false), parse_quote_spanned! {span=> #[allow(non_camel_case_types, dead_code)] }, @@ -564,17 +585,19 @@ impl ToTokens for ParsedBundle { generics: generics.into(), fields: Fields::Named(mask_type_match_variant_fields), semi_token: None, - } - .to_tokens(tokens); + }; + mask_type_match_variant_struct.to_tokens(tokens); + create_struct_debug_impl(&mask_type_match_variant_struct, mask_type_name, None) + .to_tokens(tokens); let mut match_variant_fields = FieldsNamed::from(fields.clone()); for Field { ty, .. } in &mut match_variant_fields.named { *ty = parse_quote_spanned! {span=> ::fayalite::expr::Expr<#ty> }; } - ItemStruct { + let match_variant_struct = ItemStruct { attrs: vec![ - common_derives(span), + common_derives(span, false), parse_quote_spanned! {span=> #[allow(non_camel_case_types, dead_code)] }, @@ -585,19 +608,19 @@ impl ToTokens for ParsedBundle { generics: generics.into(), fields: Fields::Named(match_variant_fields), semi_token: None, - } - .to_tokens(tokens); + }; + match_variant_struct.to_tokens(tokens); + create_struct_debug_impl(&match_variant_struct, &struct_name, None).to_tokens(tokens); let mut mask_type_sim_value_fields = mask_type_fields; for Field { ty, .. } in &mut mask_type_sim_value_fields.named { *ty = parse_quote_spanned! {span=> ::fayalite::sim::value::SimValue<#ty> }; } - ItemStruct { + let mask_type_sim_value_struct = ItemStruct { attrs: vec![ parse_quote_spanned! {span=> #[::fayalite::__std::prelude::v1::derive( - ::fayalite::__std::fmt::Debug, ::fayalite::__std::clone::Clone, )] }, @@ -611,19 +634,34 @@ impl ToTokens for ParsedBundle { generics: generics.into(), fields: Fields::Named(mask_type_sim_value_fields), semi_token: None, + }; + mask_type_sim_value_struct.to_tokens(tokens); + if custom_debug_mask_sim.is_none() { + create_struct_debug_impl( + &mask_type_struct, + mask_type_name, + Some(CustomDebugTrait { + trait_path: &parse_quote_spanned! {span=> + ::fayalite::ty::SimValueDebug + }, + fn_name: &format_ident!("sim_value_debug", span = span), + this_arg: &parse_quote_spanned! {span=> + value: &::SimValue + }, + }), + ) + .to_tokens(tokens); } - .to_tokens(tokens); let mut sim_value_fields = FieldsNamed::from(fields.clone()); for Field { ty, .. } in &mut sim_value_fields.named { *ty = parse_quote_spanned! {span=> ::fayalite::sim::value::SimValue<#ty> }; } - ItemStruct { + let sim_value_struct = ItemStruct { attrs: vec![ parse_quote_spanned! {span=> #[::fayalite::__std::prelude::v1::derive( - ::fayalite::__std::fmt::Debug, ::fayalite::__std::clone::Clone, )] }, @@ -637,8 +675,36 @@ impl ToTokens for ParsedBundle { generics: generics.into(), fields: Fields::Named(sim_value_fields), semi_token: None, + }; + sim_value_struct.to_tokens(tokens); + if custom_debug_sim.is_none() { + create_struct_debug_impl( + &type_struct, + &struct_name, + Some(CustomDebugTrait { + trait_path: &parse_quote_spanned! {span=> + ::fayalite::ty::SimValueDebug + }, + fn_name: &format_ident!("sim_value_debug", span = span), + this_arg: &parse_quote_spanned! {span=> + value: &::SimValue + }, + }), + ) + .to_tokens(tokens); + } + if custom_sim_display.is_some() { + quote_spanned! {span=> + #[automatically_derived] + impl #impl_generics ::fayalite::__std::fmt::Display for #sim_value_ident #type_generics + #where_clause + { + fn fmt(&self, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result { + <#target #type_generics as ::fayalite::ty::SimValueDisplay>::sim_value_display(self, f) + } + } + }.to_tokens(tokens); } - .to_tokens(tokens); let this_token = Ident::new("__this", span); let fields_token = Ident::new("__fields", span); let self_token = Token![self](span); @@ -820,6 +886,14 @@ impl ToTokens for ParsedBundle { } } #[automatically_derived] + impl #impl_generics ::fayalite::__std::fmt::Debug for #mask_type_sim_value_ident #type_generics + #where_clause + { + fn fmt(&self, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result { + <#mask_type_ident #type_generics as ::fayalite::ty::SimValueDebug>::sim_value_debug(self, f) + } + } + #[automatically_derived] impl #impl_generics ::fayalite::expr::ValueType for #mask_type_sim_value_ident #type_generics #where_clause { @@ -980,6 +1054,14 @@ impl ToTokens for ParsedBundle { } } #[automatically_derived] + impl #impl_generics ::fayalite::__std::fmt::Debug for #sim_value_ident #type_generics + #where_clause + { + fn fmt(&self, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result { + <#target #type_generics as ::fayalite::ty::SimValueDebug>::sim_value_debug(self, f) + } + } + #[automatically_derived] impl #impl_generics ::fayalite::expr::ValueType for #sim_value_ident #type_generics #where_clause { @@ -1141,7 +1223,7 @@ impl ToTokens for ParsedBundle { valueless_eq_body = quote_spanned! {span=> let __lhs = ::fayalite::expr::ValueType::ty(&__lhs); let __rhs = ::fayalite::expr::ValueType::ty(&__rhs); - #(#fields_valueless_eq)|* + #(#fields_valueless_eq)&* }; valueless_ne_body = quote_spanned! {span=> let __lhs = ::fayalite::expr::ValueType::ty(&__lhs); diff --git a/crates/fayalite-proc-macros-impl/src/hdl_enum.rs b/crates/fayalite-proc-macros-impl/src/hdl_enum.rs index 90838f0..e9f013b 100644 --- a/crates/fayalite-proc-macros-impl/src/hdl_enum.rs +++ b/crates/fayalite-proc-macros-impl/src/hdl_enum.rs @@ -3,8 +3,9 @@ use crate::{ Errors, HdlAttr, PairsIterExt, hdl_type_common::{ - ItemOptions, MakeHdlTypeExpr, MaybeParsed, ParsedGenerics, ParsedType, SplitForImpl, - TypesParser, WrappedInConst, common_derives, get_target, + CustomDebugOptions, ItemOptions, MakeHdlTypeExpr, MaybeParsed, ParsedGenerics, ParsedType, + SplitForImpl, TypesParser, WrappedInConst, common_derives, create_struct_debug_impl, + get_target, }, kw, }; @@ -158,15 +159,32 @@ impl ParsedEnum { custom_bounds, no_static: _, no_runtime_generics: _, - cmp_eq, + cmp_eq: _, ref get, + custom_debug: _, + custom_sim_display: _, } = options.body; - if let Some((cmp_eq,)) = cmp_eq { - errors.error(cmp_eq, "#[hdl(cmp_eq)] is not yet implemented for enums"); - } if let Some((get, ..)) = get { errors.error(get, "#[hdl(get(...))] is not allowed on enums"); } + let CustomDebugOptions { + type_: _, + sim: _, + mask_type, + mask_sim, + } = options.body.custom_debug(); + if let Some((mask_type,)) = mask_type { + errors.error( + mask_type, + "#[hdl(custom_debug(mask_type)] is not allowed on enums", + ); + } + if let Some((mask_sim,)) = mask_sim { + errors.error( + mask_sim, + "#[hdl(custom_debug(mask_sim)] is not allowed on enums", + ); + } attrs.retain(|attr| { if attr.path().is_ident("repr") { errors.error(attr, "#[repr] is not supported on #[hdl] enums"); @@ -228,12 +246,21 @@ impl ToTokens for ParsedEnum { custom_bounds: _, no_static, no_runtime_generics, - cmp_eq: _, // TODO: implement cmp_eq for enums + cmp_eq, get: _, + custom_debug: _, + custom_sim_display, } = &options.body; + let CustomDebugOptions { + type_: custom_debug_type, + sim: custom_debug_sim, + mask_type: _, + mask_sim: _, + } = options.body.custom_debug(); let target = get_target(target, ident); + let enum_name = ident.to_string(); let mut struct_attrs = attrs.clone(); - struct_attrs.push(common_derives(span)); + struct_attrs.push(common_derives(span, false)); struct_attrs.push(parse_quote_spanned! {span=> #[allow(non_snake_case)] }); @@ -273,7 +300,7 @@ impl ToTokens for ParsedEnum { } }, )); - ItemStruct { + let type_struct = ItemStruct { attrs: struct_attrs, vis: vis.clone(), struct_token: Token![struct](enum_token.span), @@ -288,8 +315,8 @@ impl ToTokens for ParsedEnum { }) }, semi_token: None, - } - .to_tokens(tokens); + }; + type_struct.to_tokens(tokens); let (impl_generics, type_generics, where_clause) = generics.split_for_impl(); if let (MaybeParsed::Parsed(generics), None) = (generics, no_runtime_generics) { generics.make_runtime_generics(tokens, vis, ident, &target, |context| { @@ -373,6 +400,9 @@ impl ToTokens for ParsedEnum { } .to_tokens(tokens); } + if custom_debug_type.is_none() { + create_struct_debug_impl(&type_struct, &enum_name, None).to_tokens(tokens); + } let mut enum_attrs = attrs.clone(); enum_attrs.push(parse_quote_spanned! {span=> #[allow(dead_code, non_camel_case_types)] @@ -453,7 +483,6 @@ impl ToTokens for ParsedEnum { let mut enum_attrs = attrs.clone(); enum_attrs.push(parse_quote_spanned! {span=> #[::fayalite::__std::prelude::v1::derive( - ::fayalite::__std::fmt::Debug, ::fayalite::__std::clone::Clone, )] }); @@ -838,6 +867,240 @@ impl ToTokens for ParsedEnum { }, )), ); + if custom_debug_sim.is_none() { + let debug_match_arms = Vec::from_iter( + variants + .iter() + .map( + |ParsedVariant { + attrs: _, + options: _, + ident, + field, + }| { + let variant_name = ident.to_string(); + if let Some(_) = field { + quote_spanned! {span=> + #sim_value_ident::#ident(field, _) => { + f.debug_tuple(#variant_name).field(field).finish() + } + } + } else { + quote_spanned! {span=> + #sim_value_ident::#ident(_) => { + f.write_str(#variant_name) + } + } + } + }, + ) + .chain(sim_value_unknown_variant_name.as_ref().map( + |sim_value_unknown_variant_name| { + let sim_value_unknown_variant_name_str = + sim_value_unknown_variant_name.to_string(); + quote_spanned! {span=> + #sim_value_ident::#sim_value_unknown_variant_name(_) => { + f.write_str(#sim_value_unknown_variant_name_str) + } + } + }, + )), + ); + quote_spanned! {span=> + #[automatically_derived] + impl #impl_generics ::fayalite::ty::SimValueDebug for #target #type_generics + #where_clause + { + fn sim_value_debug( + value: &::SimValue, + f: &mut ::fayalite::__std::fmt::Formatter<'_>, + ) -> ::fayalite::__std::fmt::Result { + match value { + #(#debug_match_arms)* + } + } + } + } + .to_tokens(tokens); + } + if custom_sim_display.is_some() { + quote_spanned! {span=> + #[automatically_derived] + impl #impl_generics ::fayalite::__std::fmt::Display for #sim_value_ident #type_generics + #where_clause + { + fn fmt(&self, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result { + <#target #type_generics as ::fayalite::ty::SimValueDisplay>::sim_value_display(self, f) + } + } + }.to_tokens(tokens); + } + if let Some((cmp_eq,)) = cmp_eq { + let mut cmp_eq_where_clause = + Generics::from(generics) + .where_clause + .unwrap_or_else(|| syn::WhereClause { + where_token: Token![where](span), + predicates: Punctuated::new(), + }); + let mut variants_value_eq = vec![]; + let mut variants_expr_eq = vec![]; + let mut fields_valueless_eq = vec![]; + for ( + variant_index, + ParsedVariant { + attrs: _, + options: variant_options, + ident: variant_ident, + field, + }, + ) in variants.iter().enumerate() + { + let VariantOptions {} = variant_options.body; + if let Some(ParsedVariantField { + paren_token: _, + attrs: _, + options: field_options, + ty: field_ty, + comma_token: _, + }) = field + { + let FieldOptions {} = field_options.body; + cmp_eq_where_clause + .predicates + .push(parse_quote_spanned! {cmp_eq.span=> + #field_ty: ::fayalite::expr::HdlPartialEqImpl<#field_ty> + }); + variants_value_eq.push(quote_spanned! {span=> + (#sim_value_ident::#variant_ident(__lhs_field, _), #sim_value_ident::#variant_ident(__rhs_field, _)) => { + ::fayalite::expr::HdlPartialEqImpl::cmp_value_eq( + __lhs.#variant_ident, + ::fayalite::__std::borrow::Cow::Borrowed(__lhs_field), + __rhs.#variant_ident, + ::fayalite::__std::borrow::Cow::Borrowed(__rhs_field), + ) + } + }); + variants_expr_eq.push(quote_spanned! {span=> + { + let (#match_variant_ident::#variant_ident(__lhs), __scope) = + ::fayalite::ty::MatchVariantAndInactiveScope::match_activate_scope( + ::fayalite::__std::iter::Iterator::next(&mut __lhs_match_variant_iter) + .expect("known to have enough variants"), + ) + else { + ::fayalite::__std::unreachable!(); + }; + let (#match_variant_ident::#variant_ident(__rhs), __scope) = + ::fayalite::ty::MatchVariantAndInactiveScope::match_activate_scope( + ::fayalite::__std::iter::Iterator::nth( + &mut ::fayalite::module::match_(__rhs), + #variant_index, + ) + .expect("known to have variant"), + ) + else { + ::fayalite::__std::unreachable!(); + }; + ::fayalite::module::connect(__retval, ::fayalite::expr::HdlPartialEqImpl::cmp_expr_eq(__lhs, __rhs)); + } + }); + fields_valueless_eq.push(quote_spanned! {span=> + ::fayalite::expr::HdlPartialEqImpl::cmp_valueless_eq( + ::fayalite::expr::Valueless::new(__lhs.#variant_ident), + ::fayalite::expr::Valueless::new(__rhs.#variant_ident), + ) + }); + } else { + variants_value_eq.push(quote_spanned! {span=> + (#sim_value_ident::#variant_ident(_), #sim_value_ident::#variant_ident(_)) => true, + }); + variants_expr_eq.push(quote_spanned! {span=> + { + let (#match_variant_ident::#variant_ident, __scope) = + ::fayalite::ty::MatchVariantAndInactiveScope::match_activate_scope( + ::fayalite::__std::iter::Iterator::next(&mut __lhs_match_variant_iter) + .expect("known to have enough variants"), + ) + else { + ::fayalite::__std::unreachable!(); + }; + let (#match_variant_ident::#variant_ident, __scope) = + ::fayalite::ty::MatchVariantAndInactiveScope::match_activate_scope( + ::fayalite::__std::iter::Iterator::nth( + &mut ::fayalite::module::match_(__rhs), + #variant_index, + ) + .expect("known to have variant"), + ) + else { + ::fayalite::__std::unreachable!(); + }; + ::fayalite::module::connect(__retval, true); + } + }); + } + } + if let Some(sim_value_unknown_variant_name) = &sim_value_unknown_variant_name { + variants_value_eq.push(quote_spanned! {span=> + (#sim_value_ident::#sim_value_unknown_variant_name(__lhs_unknown), #sim_value_ident::#sim_value_unknown_variant_name(__rhs_unknown)) => { + __lhs_unknown == __rhs_unknown + } + }); + } + let valueless_eq_body = if fields_valueless_eq.is_empty() { + quote_spanned! {span=> + ::fayalite::expr::Valueless::new(::fayalite::int::Bool) + } + } else { + quote_spanned! {span=> + let __lhs = ::fayalite::expr::ValueType::ty(&__lhs); + let __rhs = ::fayalite::expr::ValueType::ty(&__rhs); + #(#fields_valueless_eq)&* + } + }; + let cmp_expr_eq_wire_name = format!("{ident}_cmp_eq"); + quote_spanned! {span=> + #[automatically_derived] + impl #impl_generics ::fayalite::expr::HdlPartialEqImpl for #target #type_generics + #cmp_eq_where_clause + { + #[track_caller] + fn cmp_value_eq( + __lhs: Self, + __lhs_value: ::fayalite::__std::borrow::Cow<'_, ::SimValue>, + __rhs: Self, + __rhs_value: ::fayalite::__std::borrow::Cow<'_, ::SimValue>, + ) -> ::fayalite::__std::primitive::bool { + match (&*__lhs_value, &*__rhs_value) { + #(#variants_value_eq)* + _ => false, + } + } + + #[track_caller] + fn cmp_expr_eq( + __lhs: ::fayalite::expr::Expr, + __rhs: ::fayalite::expr::Expr, + ) -> ::fayalite::expr::Expr<::fayalite::int::Bool> { + let __retval = ::fayalite::module::wire(::fayalite::module::ImplicitName(#cmp_expr_eq_wire_name), ::fayalite::int::Bool); + ::fayalite::module::connect(__retval, false); + let mut __lhs_match_variant_iter = ::fayalite::module::match_(__lhs); + #(#variants_expr_eq)* + __retval + } + + #[track_caller] + fn cmp_valueless_eq( + __lhs: ::fayalite::expr::Valueless, + __rhs: ::fayalite::expr::Valueless, + ) -> ::fayalite::expr::Valueless<::fayalite::int::Bool> { + #valueless_eq_body + } + } + } + .to_tokens(tokens); + } let variants_len = variants.len(); quote_spanned! {span=> #[automatically_derived] @@ -888,6 +1151,7 @@ impl ToTokens for ParsedEnum { #(#sim_value_from_opaque_match_arms)* } } + #[allow(irrefutable_let_patterns)] fn sim_value_clone_from_opaque( &self, value: &mut ::SimValue, @@ -933,6 +1197,14 @@ impl ToTokens for ParsedEnum { } } #[automatically_derived] + impl #impl_generics ::fayalite::__std::fmt::Debug for #sim_value_ident #type_generics + #where_clause + { + fn fmt(&self, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result { + <#target #type_generics as ::fayalite::ty::SimValueDebug>::sim_value_debug(self, f) + } + } + #[automatically_derived] impl #impl_generics ::fayalite::sim::value::ToSimValueWithType<#target #type_generics> for #sim_value_ident #type_generics #where_clause diff --git a/crates/fayalite-proc-macros-impl/src/hdl_type_alias.rs b/crates/fayalite-proc-macros-impl/src/hdl_type_alias.rs index 0fa2222..556c15b 100644 --- a/crates/fayalite-proc-macros-impl/src/hdl_type_alias.rs +++ b/crates/fayalite-proc-macros-impl/src/hdl_type_alias.rs @@ -215,6 +215,8 @@ impl ParsedTypeAlias { no_runtime_generics, cmp_eq, get: _, + ref custom_debug, + custom_sim_display, } = options.body; if let Some((no_static,)) = no_static { errors.error(no_static, "no_static is not valid on type aliases"); @@ -234,6 +236,15 @@ impl ParsedTypeAlias { if let Some((cmp_eq,)) = cmp_eq { errors.error(cmp_eq, "cmp_eq is not valid on type aliases"); } + if let Some((custom_debug, _, _)) = custom_debug { + errors.error(custom_debug, "custom_debug is not valid on type aliases"); + } + if let Some((custom_sim_display,)) = custom_sim_display { + errors.error( + custom_sim_display, + "custom_sim_display is not valid on type aliases", + ); + } if let Some((custom_bounds,)) = custom_bounds { errors.error( custom_bounds, @@ -287,6 +298,8 @@ impl ParsedTypeAlias { no_runtime_generics: _, cmp_eq, ref mut get, + ref custom_debug, + custom_sim_display, } = options.body; if let Some(get) = get.take() { return Self::parse_phantom_const_accessor( @@ -311,6 +324,15 @@ impl ParsedTypeAlias { if let Some((cmp_eq,)) = cmp_eq { errors.error(cmp_eq, "cmp_eq is not valid on type aliases"); } + if let Some((custom_debug, _, _)) = custom_debug { + errors.error(custom_debug, "custom_debug is not valid on type aliases"); + } + if let Some((custom_sim_display,)) = custom_sim_display { + errors.error( + custom_sim_display, + "custom_sim_display is not valid on type aliases", + ); + } let generics = if custom_bounds.is_some() { MaybeParsed::Unrecognized(generics) } else if let Some(generics) = errors.ok(ParsedGenerics::parse(&mut generics)) { @@ -356,6 +378,8 @@ impl ToTokens for ParsedTypeAlias { no_runtime_generics, cmp_eq: _, get: _, + custom_debug: _, + custom_sim_display: _, } = &options.body; let target = get_target(target, ident); let mut type_attrs = attrs.clone(); @@ -402,6 +426,8 @@ impl ToTokens for ParsedTypeAlias { no_runtime_generics: _, cmp_eq: _, get: _, + custom_debug: _, + custom_sim_display: _, } = &options.body; let span = ident.span(); let mut type_attrs = attrs.clone(); @@ -427,7 +453,7 @@ impl ToTokens for ParsedTypeAlias { format_ident!("__{}__GenericsAccumulation", ident); ItemStruct { attrs: vec![ - common_derives(span), + common_derives(span, true), parse_quote_spanned! {span=> #[allow(non_camel_case_types)] }, diff --git a/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs b/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs index 3a0e5e9..18cffc6 100644 --- a/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs +++ b/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs @@ -7,10 +7,10 @@ use std::{collections::HashMap, fmt, mem}; use syn::{ AngleBracketedGenericArguments, Attribute, Block, ConstParam, Expr, ExprBlock, ExprGroup, ExprIndex, ExprParen, ExprPath, ExprTuple, Field, FieldMutability, Fields, FieldsNamed, - FieldsUnnamed, GenericArgument, GenericParam, Generics, Ident, ImplGenerics, Index, ItemStruct, - Path, PathArguments, PathSegment, PredicateType, QSelf, Stmt, Token, TraitBound, Turbofish, - Type, TypeGenerics, TypeGroup, TypeParam, TypeParamBound, TypeParen, TypePath, TypeTuple, - Visibility, WhereClause, WherePredicate, + FieldsUnnamed, FnArg, GenericArgument, GenericParam, Generics, Ident, ImplGenerics, Index, + ItemStruct, Path, PathArguments, PathSegment, PredicateType, QSelf, Stmt, Token, TraitBound, + Turbofish, Type, TypeGenerics, TypeGroup, TypeParam, TypeParamBound, TypeParen, TypePath, + TypeTuple, Visibility, WhereClause, WherePredicate, parse::{Parse, ParseStream}, parse_quote, parse_quote_spanned, punctuated::{Pair, Punctuated}, @@ -18,6 +18,17 @@ use syn::{ token::{Brace, Bracket, Paren}, }; +crate::options! { + #[options = CustomDebugOptions] + #[no_ident_fragment] + pub(crate) enum CustomDebugOption { + Type(type_), + Sim(sim), + MaskType(mask_type), + MaskSim(mask_sim), + } +} + crate::options! { #[options = ItemOptions] pub(crate) enum ItemOption { @@ -28,6 +39,8 @@ crate::options! { NoRuntimeGenerics(no_runtime_generics), CmpEq(cmp_eq), Get(get, Expr), + CustomDebug(custom_debug, CustomDebugOptions), + CustomSimDisplay(custom_sim_display), } } @@ -41,8 +54,36 @@ impl ItemOptions { { self.no_static = Some((kw::no_static(custom_bounds.span),)); } + if let Some((kw, _, custom_debug)) = &mut self.custom_debug { + if let CustomDebugOptions { + type_: None, + sim: None, + mask_type: None, + mask_sim: None, + } = custom_debug + { + *custom_debug = CustomDebugOptions { + type_: Some((kw::type_(kw.span),)), + sim: Some((kw::sim(kw.span),)), + mask_type: None, + mask_sim: None, + }; + } + } Ok(()) } + pub(crate) fn custom_debug(&self) -> &CustomDebugOptions { + self.custom_debug.as_ref().map(|v| &v.2).unwrap_or( + const { + &CustomDebugOptions { + type_: None, + sim: None, + mask_type: None, + mask_sim: None, + } + }, + ) + } } pub(crate) struct WrappedInConst<'a> { @@ -84,10 +125,17 @@ pub(crate) fn get_target(target: &Option<(kw::target, Paren, Path)>, item_ident: } } -pub(crate) fn common_derives(span: Span) -> Attribute { +pub(crate) fn common_derives(span: Span, include_debug: bool) -> Attribute { + let debug = include_debug + .then(|| { + quote_spanned! {span=> + ::fayalite::__std::fmt::Debug + } + }) + .into_iter(); parse_quote_spanned! {span=> #[::fayalite::__std::prelude::v1::derive( - ::fayalite::__std::fmt::Debug, + #(#debug,)* ::fayalite::__std::cmp::Eq, ::fayalite::__std::cmp::PartialEq, ::fayalite::__std::hash::Hash, @@ -2975,7 +3023,7 @@ impl ParsedGenerics { let span = ident.span(); ItemStruct { attrs: vec![ - common_derives(span), + common_derives(span, true), parse_quote_spanned! {span=> #[allow(non_camel_case_types)] }, @@ -4733,3 +4781,109 @@ impl ParsedVisibility { .map(|ord| if ord.is_lt() { self } else { other }) } } + +pub(crate) struct CustomDebugTrait<'a> { + pub(crate) trait_path: &'a Path, + pub(crate) fn_name: &'a Ident, + pub(crate) this_arg: &'a FnArg, +} + +#[must_use] +pub(crate) fn create_struct_debug_impl( + item_struct: &ItemStruct, + debug_struct_name: &str, + custom_debug_trait: Option>, +) -> TokenStream { + let ident = &item_struct.ident; + let span = ident.span(); + let (impl_generics, type_generics, where_clause) = item_struct.generics.split_for_impl(); + let trait_path; + let fn_name; + let this_arg; + let CustomDebugTrait { + trait_path, + fn_name, + this_arg, + } = match custom_debug_trait { + Some(v) => v, + None => { + trait_path = parse_quote_spanned! {span=> + ::fayalite::__std::fmt::Debug + }; + fn_name = parse_quote_spanned! {span=> + fmt + }; + this_arg = parse_quote_spanned! {span=> + &self + }; + CustomDebugTrait { + trait_path: &trait_path, + fn_name: &fn_name, + this_arg: &this_arg, + } + } + }; + let this_arg_name = match this_arg { + FnArg::Receiver(this_arg) => this_arg.self_token.to_token_stream(), + FnArg::Typed(this_arg) => match &*this_arg.pat { + syn::Pat::Ident(pat_ident) => pat_ident.ident.to_token_stream(), + _ => unreachable!(), + }, + }; + match &item_struct.fields { + Fields::Named(fields) => { + let field_idents = fields + .named + .iter() + .map(|v| v.ident.as_ref().expect("known to have field name")); + let field_names = field_idents.clone().map(|v| v.to_string()); + quote_spanned! {span=> + #[automatically_derived] + impl #impl_generics #trait_path for #ident #type_generics + #where_clause + { + fn #fn_name(#this_arg, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result { + let _ = #this_arg_name; + f.debug_struct(#debug_struct_name) + #(.field(#field_names, &#this_arg_name.#field_idents))* + .finish() + } + } + } + } + Fields::Unnamed(fields) => { + let field_members = fields + .unnamed + .iter() + .enumerate() + .map(|(index, _)| syn::Index { + index: index as _, + span, + }); + quote_spanned! {span=> + #[automatically_derived] + impl #impl_generics #trait_path for #ident #type_generics + #where_clause + { + fn #fn_name(#this_arg, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result { + let _ = #this_arg_name; + f.debug_tuple(#debug_struct_name) + #(.field(&#this_arg_name.#field_members))* + .finish() + } + } + } + } + Fields::Unit => quote_spanned! {ident.span()=> + #[automatically_derived] + impl #impl_generics #trait_path for #ident #type_generics + #where_clause + { + fn #fn_name(#this_arg, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result { + let _ = #this_arg_name; + f.write_str(#debug_struct_name) + } + } + }, + } +} diff --git a/crates/fayalite-proc-macros-impl/src/lib.rs b/crates/fayalite-proc-macros-impl/src/lib.rs index 152053c..905cb05 100644 --- a/crates/fayalite-proc-macros-impl/src/lib.rs +++ b/crates/fayalite-proc-macros-impl/src/lib.rs @@ -42,6 +42,7 @@ pub(crate) trait CustomToken: mod kw { pub(crate) use syn::token::Extern as extern_; + pub(crate) use syn::token::Type as type_; macro_rules! custom_keyword { ($kw:ident) => { @@ -75,6 +76,8 @@ mod kw { custom_keyword!(cmp_eq); custom_keyword!(connect_inexact); custom_keyword!(custom_bounds); + custom_keyword!(custom_debug); + custom_keyword!(custom_sim_display); custom_keyword!(flip); custom_keyword!(get); custom_keyword!(hdl); @@ -83,6 +86,8 @@ mod kw { custom_keyword!(input); custom_keyword!(instance); custom_keyword!(m); + custom_keyword!(mask_sim); + custom_keyword!(mask_type); custom_keyword!(memory); custom_keyword!(memory_array); custom_keyword!(memory_with_init); diff --git a/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs b/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs index ca06c0b..605f662 100644 --- a/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs +++ b/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs @@ -1096,11 +1096,9 @@ impl Visitor<'_> { let (#(#bindings,)*) = { type __MatchTy = ::SimValue; let __match_value = #expr; - let __match_value = { - use ::fayalite::sim::value::match_sim_value::*; - // use method syntax to deduce the correct trait to call - ::fayalite::sim::value::match_sim_value::MatchSimValueHelper::new(__match_value).__fayalite_match_sim_value() - }; + // use method syntax to deduce what type to convert to + let __match_value = ::fayalite::sim::value::match_sim_value::MatchSimValueHelper::new(__match_value) + .__fayalite_match_sim_value(); #let_token #pat #eq_token __match_value #semi_token (#(#bindings_idents,)*) }; @@ -1172,11 +1170,9 @@ impl Visitor<'_> { { type __MatchTy = ::SimValue; let __match_value = #expr; - let __match_value = { - use ::fayalite::sim::value::match_sim_value::*; - // use method syntax to deduce the correct trait to call - ::fayalite::sim::value::match_sim_value::MatchSimValueHelper::new(__match_value).__fayalite_match_sim_value() - }; + // use method syntax to deduce what type to convert to + let __match_value = ::fayalite::sim::value::match_sim_value::MatchSimValueHelper::new(__match_value) + .__fayalite_match_sim_value(); #match_token __match_value { #(#arms)* } diff --git a/crates/fayalite/Cargo.toml b/crates/fayalite/Cargo.toml index fdf1c87..1743add 100644 --- a/crates/fayalite/Cargo.toml +++ b/crates/fayalite/Cargo.toml @@ -26,10 +26,12 @@ hashbrown.workspace = true jobslot.workspace = true num-bigint.workspace = true num-traits.workspace = true +once_cell.workspace = true ordered-float.workspace = true petgraph.workspace = true serde_json.workspace = true serde.workspace = true +sha2.workspace = true tempfile.workspace = true vec_map.workspace = true which.workspace = true diff --git a/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/destructuring.rs b/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/destructuring.rs index 8d70d21..065e5de 100644 --- a/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/destructuring.rs +++ b/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/destructuring.rs @@ -95,7 +95,23 @@ //! } //! //! #[hdl] -//! fn destructure_to_sim_value<'a, T: Type>(v: impl ToSimValue>) { +//! fn destructure_inner(v: as Type>::SimValue) { +//! #[hdl(sim)] +//! let MyStruct:: { +//! a, +//! mut b, +//! c, +//! } = v; +//! +//! // that gives these types: +//! let _: SimValue> = a; +//! let _: SimValue = b; +//! let _: SimValue = c; +//! *b = false; // can modify b since mut was used +//! } +//! +//! #[hdl] +//! fn destructure_inner_ref<'a, T: Type>(v: &'a as Type>::SimValue) { //! #[hdl(sim)] //! let MyStruct:: { //! a, @@ -104,8 +120,25 @@ //! } = v; //! //! // that gives these types: -//! let _: SimValue> = a; -//! let _: SimValue = b; -//! let _: SimValue = c; +//! let _: &'a SimValue> = a; +//! let _: &'a SimValue = b; +//! let _: &'a SimValue = c; +//! } +//! +//! #[hdl] +//! fn destructure_inner_mut<'a, T: Type>(v: &'a mut as Type>::SimValue) { +//! #[hdl(sim)] +//! let MyStruct:: { +//! a, +//! b, +//! c, +//! } = v; +//! +//! **b = true; // you can modify v by modifying b which borrows from it +//! +//! // that gives these types: +//! let _: &'a mut SimValue> = a; +//! let _: &'a mut SimValue = b; +//! let _: &'a mut SimValue = c; //! } //! ``` diff --git a/crates/fayalite/src/_docs/modules/module_bodies/hdl_match_statements.rs b/crates/fayalite/src/_docs/modules/module_bodies/hdl_match_statements.rs index accd3d7..9e2d41d 100644 --- a/crates/fayalite/src/_docs/modules/module_bodies/hdl_match_statements.rs +++ b/crates/fayalite/src/_docs/modules/module_bodies/hdl_match_statements.rs @@ -72,15 +72,47 @@ //! } //! //! #[hdl] -//! fn match_to_sim_value<'a, T: Type>(v: impl ToSimValue>) { +//! fn match_inner_move(v: as Type>::SimValue) -> String { //! #[hdl(sim)] //! match v { -//! MyEnum::::A => println!("got A"), -//! MyEnum::::B(b) => { +//! MyEnum::::A => String::from("got A"), +//! MyEnum::::B(mut b) => { //! let _: SimValue = b; // b has this type -//! println!("got B({b})"); +//! let text = format!("got B({b})"); +//! *b = true; // can modify b since mut was used +//! text //! } -//! _ => println!("something else"), +//! _ => String::from("something else"), +//! } +//! } +//! +//! #[hdl] +//! fn match_inner_ref<'a, T: Type>(v: &'a as Type>::SimValue) -> u32 { +//! #[hdl(sim)] +//! match v { +//! MyEnum::::A => 1, +//! MyEnum::::B(b) => { +//! let _: &'a SimValue = b; // b has this type +//! println!("got B({b})"); +//! 5 +//! } +//! _ => 42, +//! } +//! } +//! +//! #[hdl] +//! fn match_inner_mut<'a, T: Type>(v: &'a mut as Type>::SimValue) -> Option<&'a mut SimValue> { +//! #[hdl(sim)] +//! match v { +//! MyEnum::::A => None, +//! MyEnum::::B(b) => { +//! println!("got B({b})"); +//! **b = true; // you can modify v by modifying b which borrows from it +//! let _: &'a mut SimValue = b; // b has this type +//! None +//! } +//! MyEnum::::C(v) => Some(v), // you can return matched values +//! _ => None, // HDL enums can have invalid discriminants, so we need this extra match arm //! } //! } //! ``` diff --git a/crates/fayalite/src/array.rs b/crates/fayalite/src/array.rs index 4e2b223..fa754fd 100644 --- a/crates/fayalite/src/array.rs +++ b/crates/fayalite/src/array.rs @@ -13,13 +13,13 @@ use crate::{ source_location::SourceLocation, ty::{ CanonicalType, MatchVariantWithoutScope, OpaqueSimValueSlice, OpaqueSimValueWriter, - OpaqueSimValueWritten, StaticType, Type, TypeProperties, TypeWithDeref, + OpaqueSimValueWritten, SimValueDebug, StaticType, Type, TypeProperties, TypeWithDeref, serde_impls::SerdeCanonicalType, }, util::ConstUsize, }; use serde::{Deserialize, Deserializer, Serialize, Serializer, de::Error}; -use std::{borrow::Cow, iter::FusedIterator, ops::Index}; +use std::{borrow::Cow, fmt, iter::FusedIterator, ops::Index}; #[derive(Copy, Clone, PartialEq, Eq, Hash)] pub struct ArrayType { @@ -28,8 +28,8 @@ pub struct ArrayType { type_properties: TypeProperties, } -impl std::fmt::Debug for ArrayType { - fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { +impl fmt::Debug for ArrayType { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { write!(f, "Array<{:?}, {}>", self.element, self.len()) } } @@ -109,14 +109,42 @@ impl Default for ArrayType { } } +struct MakeType(Interned); + +impl From> for Interned { + fn from(value: MakeType) -> Self { + value.0 + } +} + +impl Default for MakeType { + fn default() -> Self { + Self(T::TYPE.intern_sized()) + } +} + +struct MakeMaskType(Interned); + +impl From> for Interned { + fn from(value: MakeMaskType) -> Self { + value.0 + } +} + +impl Default for MakeMaskType { + fn default() -> Self { + Self(T::MASK_TYPE.intern_sized()) + } +} + impl StaticType for ArrayType { const TYPE: Self = Self { - element: LazyInterned::new_lazy(&|| T::TYPE.intern_sized()), + element: LazyInterned::new_const::>(), len: Len::SIZE, type_properties: Self::TYPE_PROPERTIES, }; const MASK_TYPE: Self::MaskType = ArrayType:: { - element: LazyInterned::new_lazy(&|| T::MASK_TYPE.intern_sized()), + element: LazyInterned::new_const::>(), len: Len::SIZE, type_properties: Self::MASK_TYPE_PROPERTIES, }; @@ -154,6 +182,15 @@ impl, Len: Size, State: Visitor + ?Sized> Visit } } +impl SimValueDebug for ArrayType { + fn sim_value_debug( + value: &::SimValue, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + fmt::Debug::fmt(value, f) + } +} + impl Type for ArrayType { type BaseType = Array; type MaskType = ArrayType; diff --git a/crates/fayalite/src/bundle.rs b/crates/fayalite/src/bundle.rs index 1471f3a..5fad35c 100644 --- a/crates/fayalite/src/bundle.rs +++ b/crates/fayalite/src/bundle.rs @@ -14,8 +14,8 @@ use crate::{ source_location::SourceLocation, ty::{ CanonicalType, MatchVariantWithoutScope, OpaqueSimValue, OpaqueSimValueSize, - OpaqueSimValueSlice, OpaqueSimValueWriter, OpaqueSimValueWritten, StaticType, Type, - TypeProperties, TypeWithDeref, impl_match_variant_as_self, + OpaqueSimValueSlice, OpaqueSimValueWriter, OpaqueSimValueWritten, SimValueDebug, + StaticType, Type, TypeProperties, TypeWithDeref, impl_match_variant_as_self, }, util::HashMap, }; @@ -271,6 +271,15 @@ impl Type for Bundle { } } +impl SimValueDebug for Bundle { + fn sim_value_debug( + value: &::SimValue, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + fmt::Debug::fmt(value, f) + } +} + pub trait BundleType: Type { type Builder: Default; fn fields(&self) -> Interned<[BundleField]>; @@ -471,6 +480,14 @@ macro_rules! impl_tuples { #[var($var)] })*] } + impl<$($T: Type,)*> SimValueDebug for ($($T,)*) { + fn sim_value_debug( + value: &::SimValue, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + fmt::Debug::fmt(value, f) + } + } impl<$($T: Type,)*> Type for ($($T,)*) { type BaseType = Bundle; type MaskType = ($($T::MaskType,)*); @@ -773,6 +790,15 @@ impl_tuples! { ] } +impl SimValueDebug for PhantomData { + fn sim_value_debug( + value: &::SimValue, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + fmt::Debug::fmt(value, f) + } +} + impl Type for PhantomData { type BaseType = Bundle; type MaskType = (); diff --git a/crates/fayalite/src/clock.rs b/crates/fayalite/src/clock.rs index 168142b..0e6d145 100644 --- a/crates/fayalite/src/clock.rs +++ b/crates/fayalite/src/clock.rs @@ -1,5 +1,6 @@ // SPDX-License-Identifier: LGPL-3.0-or-later // See Notices.txt for copyright information + use crate::{ expr::{Expr, ValueType}, hdl, @@ -9,10 +10,12 @@ use crate::{ source_location::SourceLocation, ty::{ CanonicalType, OpaqueSimValueSize, OpaqueSimValueSlice, OpaqueSimValueWriter, - OpaqueSimValueWritten, StaticType, Type, TypeProperties, impl_match_variant_as_self, + OpaqueSimValueWritten, SimValueDebug, StaticType, Type, TypeProperties, + impl_match_variant_as_self, }, }; use bitvec::{bits, order::Lsb0}; +use std::fmt; #[derive(Copy, Clone, Eq, PartialEq, Hash, Debug, Default)] pub struct Clock; @@ -69,6 +72,15 @@ impl Type for Clock { } } +impl SimValueDebug for Clock { + fn sim_value_debug( + value: &::SimValue, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + fmt::Debug::fmt(value, f) + } +} + impl Clock { pub fn type_properties(self) -> TypeProperties { Self::TYPE_PROPERTIES diff --git a/crates/fayalite/src/enum_.rs b/crates/fayalite/src/enum_.rs index a04f67a..f6af578 100644 --- a/crates/fayalite/src/enum_.rs +++ b/crates/fayalite/src/enum_.rs @@ -2,7 +2,7 @@ // See Notices.txt for copyright information use crate::{ - expr::{Expr, HdlPartialEq, HdlPartialEqImpl, ToExpr, ValueType, ops::VariantAccess}, + expr::{Expr, ToExpr, ValueType, ops::VariantAccess}, hdl, int::{Bool, UIntValue}, intern::{Intern, Interned}, @@ -10,18 +10,18 @@ use crate::{ EnumMatchVariantAndInactiveScopeImpl, EnumMatchVariantsIterImpl, Scope, connect, enum_match_variants_helper, incomplete_wire, wire, }, - sim::value::SimValue, + sim::value::{SimValue, ToSimValue, ToSimValueWithType}, source_location::SourceLocation, ty::{ CanonicalType, MatchVariantAndInactiveScope, OpaqueSimValue, OpaqueSimValueSize, - OpaqueSimValueSlice, OpaqueSimValueWriter, OpaqueSimValueWritten, StaticType, Type, - TypeProperties, + OpaqueSimValueSlice, OpaqueSimValueWriter, OpaqueSimValueWritten, SimValueDebug, + StaticType, Type, TypeProperties, }, util::HashMap, }; use bitvec::{order::Lsb0, slice::BitSlice, view::BitView}; use serde::{Deserialize, Serialize}; -use std::{borrow::Cow, convert::Infallible, fmt, iter::FusedIterator, sync::Arc}; +use std::{convert::Infallible, fmt, iter::FusedIterator, sync::Arc}; #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Serialize, Deserialize)] pub struct EnumVariant { @@ -410,6 +410,15 @@ impl Type for Enum { } } +impl SimValueDebug for Enum { + fn sim_value_debug( + value: &::SimValue, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + fmt::Debug::fmt(value, f) + } +} + #[derive(Clone, PartialEq, Eq, Hash, Debug, Default)] pub struct EnumPaddingSimValue { bits: Option, @@ -723,95 +732,12 @@ pub fn enum_type_to_sim_builder(v: T) -> T::SimBuilder { v.into() } -#[hdl] +#[hdl(cmp_eq)] pub enum HdlOption { HdlNone, HdlSome(T), } -impl, Rhs: Type> HdlPartialEqImpl> - for HdlOption -{ - fn cmp_value_eq( - lhs: Self, - lhs_value: Cow<'_, Self::SimValue>, - rhs: HdlOption, - rhs_value: Cow<'_, as Type>::SimValue>, - ) -> bool { - type SimValueMatch = ::SimValue; - match (&*lhs_value, &*rhs_value) { - (SimValueMatch::::HdlNone(_), SimValueMatch::>::HdlNone(_)) => { - true - } - (SimValueMatch::::HdlSome(..), SimValueMatch::>::HdlNone(_)) - | (SimValueMatch::::HdlNone(_), SimValueMatch::>::HdlSome(..)) => { - false - } - ( - SimValueMatch::::HdlSome(l, _), - SimValueMatch::>::HdlSome(r, _), - ) => HdlPartialEqImpl::cmp_value_eq( - lhs.HdlSome, - Cow::Borrowed(&**l), - rhs.HdlSome, - Cow::Borrowed(&**r), - ), - } - } - - #[hdl] - fn cmp_expr_eq(lhs: Expr, rhs: Expr>) -> Expr { - #[hdl] - let cmp_eq = wire(); - #[hdl] - match lhs { - HdlSome(lhs) => - { - #[hdl] - match rhs { - HdlSome(rhs) => connect(cmp_eq, lhs.cmp_eq(rhs)), - HdlNone => connect(cmp_eq, false), - } - } - HdlNone => - { - #[hdl] - match rhs { - HdlSome(_) => connect(cmp_eq, false), - HdlNone => connect(cmp_eq, true), - } - } - } - cmp_eq - } - - #[hdl] - fn cmp_expr_ne(lhs: Expr, rhs: Expr>) -> Expr { - #[hdl] - let cmp_ne = wire(); - #[hdl] - match lhs { - HdlSome(lhs) => - { - #[hdl] - match rhs { - HdlSome(rhs) => connect(cmp_ne, lhs.cmp_ne(rhs)), - HdlNone => connect(cmp_ne, true), - } - } - HdlNone => - { - #[hdl] - match rhs { - HdlSome(_) => connect(cmp_ne, true), - HdlNone => connect(cmp_ne, false), - } - } - } - cmp_ne - } -} - #[allow(non_snake_case)] pub fn HdlNone() -> Expr> { HdlOption[T::TYPE].HdlNone() @@ -823,6 +749,123 @@ pub fn HdlSome(value: impl ToExpr) -> Expr> { HdlOption[value.ty()].HdlSome(value) } +impl From>> for Option> { + #[hdl] + fn from(value: SimValue>) -> Self { + #[hdl(sim)] + match value { + HdlSome(v) => Some(v), + HdlNone => None, + } + } +} + +impl<'a, T: Type> From<&'a SimValue>> for Option<&'a SimValue> { + #[hdl] + fn from(value: &'a SimValue>) -> Self { + #[hdl(sim)] + match value { + HdlSome(v) => Some(v), + HdlNone => None, + } + } +} + +impl<'a, T: Type> From<&'a mut SimValue>> for Option<&'a mut SimValue> { + #[hdl] + fn from(value: &'a mut SimValue>) -> Self { + #[hdl(sim)] + match value { + HdlSome(v) => Some(v), + HdlNone => None, + } + } +} + +impl>> ValueType for Option { + type Type = HdlOption; + type ValueCategory = T::ValueCategory; + + fn ty(&self) -> Self::Type { + StaticType::TYPE + } +} + +impl> ToSimValueWithType> for Option { + #[hdl] + fn to_sim_value_with_type(&self, ty: HdlOption) -> SimValue> { + match self { + Some(v) => + { + #[hdl(sim)] + ty.HdlSome(v) + } + None => + { + #[hdl(sim)] + ty.HdlNone() + } + } + } + #[hdl] + fn into_sim_value_with_type(self, ty: HdlOption) -> SimValue> { + match self { + Some(v) => + { + #[hdl(sim)] + ty.HdlSome(v) + } + None => + { + #[hdl(sim)] + ty.HdlNone() + } + } + } +} + +impl>> ToSimValue for Option { + #[hdl] + fn to_sim_value(&self) -> SimValue { + match self { + Some(v) => + { + #[hdl(sim)] + HdlSome(v) + } + None => + { + #[hdl(sim)] + HdlNone() + } + } + } + #[hdl] + fn into_sim_value(self) -> SimValue { + match self { + Some(v) => + { + #[hdl(sim)] + HdlSome(v) + } + None => + { + #[hdl(sim)] + HdlNone() + } + } + } +} + +impl>> ToExpr for Option { + fn to_expr(&self) -> Expr { + match self { + Some(v) => HdlSome(v), + None => HdlNone(), + } + } +} + impl HdlOption { #[track_caller] pub fn try_map( diff --git a/crates/fayalite/src/expr.rs b/crates/fayalite/src/expr.rs index 00a0cee..e235cd7 100644 --- a/crates/fayalite/src/expr.rs +++ b/crates/fayalite/src/expr.rs @@ -17,7 +17,7 @@ use crate::{ reg::Reg, reset::{AsyncReset, Reset, ResetType, ResetTypeDispatch, SyncReset}, sim::value::{SimValue, ToSimValue, ToSimValueWithType}, - ty::{CanonicalType, OpaqueSimValue, StaticType, Type, TypeWithDeref}, + ty::{CanonicalType, OpaqueSimValue, StaticType, TraceAsString, Type, TypeWithDeref}, util::{ConstBool, ConstUsize}, wire::Wire, }; @@ -218,6 +218,8 @@ expr_enum! { SliceSInt(ops::SliceSInt), CastToBits(ops::CastToBits), CastBitsTo(ops::CastBitsTo), + ToTraceAsString(ops::ToTraceAsString), + TraceAsStringAsInner(ops::TraceAsStringAsInner), ModuleIO(ModuleIO), Instance(Instance), Wire(Wire), @@ -389,6 +391,35 @@ impl Expr { __flow: this.__flow, } } + #[track_caller] + pub fn as_trace_as_string(this: Self, ty: TraceAsString) -> Expr> { + assert_eq!(this.ty(), ty.inner_ty()); + ops::ToTraceAsString::new(Expr::canonical(this), ty).to_expr() + } +} + +impl Expr { + pub fn unwrap_transparent_types(mut this: Self) -> Expr { + loop { + match this.ty() { + CanonicalType::UInt(_) + | CanonicalType::SInt(_) + | CanonicalType::Bool(_) + | CanonicalType::Array(_) + | CanonicalType::Enum(_) + | CanonicalType::Bundle(_) + | CanonicalType::AsyncReset(_) + | CanonicalType::SyncReset(_) + | CanonicalType::Reset(_) + | CanonicalType::Clock(_) + | CanonicalType::PhantomConst(_) + | CanonicalType::DynSimOnly(_) => return this, + CanonicalType::TraceAsString(_) => { + this = *Expr::::from_canonical(this); + } + } + } + } } impl ToLiteralBits for Expr { @@ -1692,3 +1723,188 @@ impl<'a, T: Type> ToSimValueInner<'a> for &'a SimValue { Cow::Borrowed(&**this) } } + +pub trait ToTraceAsString: ValueType { + type Output: ValueType, ValueCategory = Self::ValueCategory>; + fn to_trace_as_string_with_ty(&self, ty: TraceAsString) -> Self::Output; + fn into_trace_as_string_with_ty(self, ty: TraceAsString) -> Self::Output + where + Self: Sized; + fn to_trace_as_string(&self) -> Self::Output; + fn into_trace_as_string(self) -> Self::Output + where + Self: Sized; +} + +impl< + T: ?Sized + + ValueType + + ToTraceAsStringImpl<::Type, ::ValueCategory>, +> ToTraceAsString for T +{ + type Output = T::ImplOutput; + fn to_trace_as_string_with_ty(&self, ty: TraceAsString) -> Self::Output { + Self::to_trace_as_string_with_ty_impl(self, ty) + } + fn into_trace_as_string_with_ty(self, ty: TraceAsString) -> Self::Output + where + Self: Sized, + { + Self::into_trace_as_string_with_ty_impl(self, ty) + } + fn to_trace_as_string(&self) -> Self::Output { + Self::to_trace_as_string_impl(self) + } + fn into_trace_as_string(self) -> Self::Output + where + Self: Sized, + { + Self::into_trace_as_string_impl(self) + } +} + +pub trait ToTraceAsStringImpl { + type ImplOutput: ValueType, ValueCategory = C>; + fn to_trace_as_string_impl(this: &Self) -> Self::ImplOutput; + fn into_trace_as_string_impl(this: Self) -> Self::ImplOutput + where + Self: Sized; + fn to_trace_as_string_with_ty_impl(this: &Self, ty: TraceAsString) -> Self::ImplOutput; + fn into_trace_as_string_with_ty_impl(this: Self, ty: TraceAsString) -> Self::ImplOutput + where + Self: Sized; +} + +impl + ToTraceAsStringImpl for T +{ + type ImplOutput = crate::ty::TraceAsStringSimValue; + + fn to_trace_as_string_impl(this: &Self) -> Self::ImplOutput { + crate::ty::TraceAsStringSimValue::new(this) + } + + fn into_trace_as_string_impl(this: Self) -> Self::ImplOutput + where + Self: Sized, + { + crate::ty::TraceAsStringSimValue::new(this) + } + + fn to_trace_as_string_with_ty_impl( + this: &Self, + ty: TraceAsString, + ) -> Self::ImplOutput { + crate::ty::TraceAsStringSimValue::new_with_ty(this, ty) + } + + fn into_trace_as_string_with_ty_impl(this: Self, ty: TraceAsString) -> Self::ImplOutput + where + Self: Sized, + { + crate::ty::TraceAsStringSimValue::new_with_ty(this, ty) + } +} + +impl + ToTraceAsStringImpl for T +{ + type ImplOutput = SimValue>; + + fn to_trace_as_string_impl(this: &Self) -> Self::ImplOutput { + crate::ty::TraceAsStringSimValue::new(this).into_sim_value() + } + + fn into_trace_as_string_impl(this: Self) -> Self::ImplOutput + where + Self: Sized, + { + crate::ty::TraceAsStringSimValue::new(this).into_sim_value() + } + + fn to_trace_as_string_with_ty_impl( + this: &Self, + ty: TraceAsString, + ) -> Self::ImplOutput { + crate::ty::TraceAsStringSimValue::new_with_ty(this, ty).into_sim_value() + } + + fn into_trace_as_string_with_ty_impl(this: Self, ty: TraceAsString) -> Self::ImplOutput + where + Self: Sized, + { + crate::ty::TraceAsStringSimValue::new_with_ty(this, ty).into_sim_value() + } +} + +impl ToTraceAsStringImpl for T { + type ImplOutput = Expr>; + + fn to_trace_as_string_impl(this: &Self) -> Self::ImplOutput { + let this = this.to_expr(); + ops::ToTraceAsString::new(Expr::canonical(this), TraceAsString::new(this.ty())).to_expr() + } + + fn into_trace_as_string_impl(this: Self) -> Self::ImplOutput + where + Self: Sized, + { + let this = this.to_expr(); + ops::ToTraceAsString::new(Expr::canonical(this), TraceAsString::new(this.ty())).to_expr() + } + + fn to_trace_as_string_with_ty_impl( + this: &Self, + ty: TraceAsString, + ) -> Self::ImplOutput { + let this = this.to_expr(); + ops::ToTraceAsString::new( + Expr::canonical(this), + ty.with_new_inner_ty(this.ty().intern_sized()), + ) + .to_expr() + } + + fn into_trace_as_string_with_ty_impl(this: Self, ty: TraceAsString) -> Self::ImplOutput + where + Self: Sized, + { + let this = this.to_expr(); + ops::ToTraceAsString::new( + Expr::canonical(this), + ty.with_new_inner_ty(this.ty().intern_sized()), + ) + .to_expr() + } +} + +impl ToTraceAsStringImpl + for T +{ + type ImplOutput = Valueless>; + + fn to_trace_as_string_impl(this: &Self) -> Self::ImplOutput { + Valueless::new(TraceAsString::new(this.ty())) + } + + fn into_trace_as_string_impl(this: Self) -> Self::ImplOutput + where + Self: Sized, + { + Valueless::new(TraceAsString::new(this.ty())) + } + + fn to_trace_as_string_with_ty_impl( + this: &Self, + ty: TraceAsString, + ) -> Self::ImplOutput { + Valueless::new(ty.with_new_inner_ty(this.ty().intern_sized())) + } + + fn into_trace_as_string_with_ty_impl(this: Self, ty: TraceAsString) -> Self::ImplOutput + where + Self: Sized, + { + Valueless::new(ty.with_new_inner_ty(this.ty().intern_sized())) + } +} diff --git a/crates/fayalite/src/expr/ops.rs b/crates/fayalite/src/expr/ops.rs index b8ef4f7..b2e20ad 100644 --- a/crates/fayalite/src/expr/ops.rs +++ b/crates/fayalite/src/expr/ops.rs @@ -12,7 +12,8 @@ use crate::{ ToExpr, ToLiteralBits, ToSimValueInner, ToValueless, ValueType, Valueless, target::{ GetTarget, Target, TargetPathArrayElement, TargetPathBundleField, - TargetPathDynArrayElement, TargetPathElement, + TargetPathDynArrayElement, TargetPathElement, TargetPathToTraceAsString, + TargetPathTraceAsStringInner, }, value_category::ValueCategoryExpr, }, @@ -27,7 +28,7 @@ use crate::{ ToSyncReset, }, sim::value::{SimValue, ToSimValue}, - ty::{CanonicalType, StaticType, Type}, + ty::{CanonicalType, StaticType, TraceAsString, Type}, util::ConstUsize, }; use bitvec::{order::Lsb0, slice::BitSlice, vec::BitVec, view::BitView}; @@ -44,6 +45,9 @@ use std::{ }, }; +#[cfg(test)] +mod test_ops_impls; + macro_rules! make_impls { ( $([$($args:tt)*])? @@ -579,10 +583,9 @@ macro_rules! make_impls { (#[kind(i64)] $($rest:tt)*) => {make_impls! { #[type([][] (i64))] $($rest)* }}; (#[kind(i128)] $($rest:tt)*) => {make_impls! { #[type([][] (i128))] $($rest)* }}; } -pub(crate) use make_impls; #[cfg(test)] -mod test_ops_impls; +pub(crate) use make_impls; macro_rules! impl_simple_binary_op_trait { ( @@ -4692,3 +4695,189 @@ impl, A> FromIterator for Expr { This::expr_from_iter(iter) } } + +#[derive(Copy, Clone, PartialEq, Eq, Hash)] +pub struct ToTraceAsString { + inner: Expr, + ty: TraceAsString, + literal_bits: Result, NotALiteralExpr>, + target: Option>, +} + +impl fmt::Debug for ToTraceAsString { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let Self { + inner, + ty: _, + literal_bits: _, + target: _, + } = self; + f.debug_struct("ToTraceAsString") + .field("inner", inner) + .finish_non_exhaustive() + } +} + +impl ToTraceAsString { + pub fn new(inner: Expr, ty: TraceAsString) -> Self { + assert_eq!(inner.ty(), ty.inner_ty().canonical()); + let literal_bits = inner.to_literal_bits(); + let target = inner.target().map(|base| { + Intern::intern_sized( + base.join(TargetPathElement::intern_sized( + TargetPathToTraceAsString { + ty: ty.canonical_trace_as_string(), + } + .into(), + )) + .canonicalized(), + ) + }); + Self { + inner, + ty, + literal_bits, + target, + } + } + pub fn inner(self) -> Expr { + self.inner + } +} + +impl GetTarget for ToTraceAsString { + fn target(&self) -> Option> { + self.target + } +} + +impl ToLiteralBits for ToTraceAsString { + fn to_literal_bits(&self) -> Result, NotALiteralExpr> { + self.literal_bits + } +} + +impl ValueType for ToTraceAsString { + type Type = TraceAsString; + type ValueCategory = ValueCategoryExpr; + + fn ty(&self) -> Self::Type { + self.ty + } +} + +impl ToExpr for ToTraceAsString { + fn to_expr(&self) -> Expr { + Expr { + __enum: ExprEnum::ToTraceAsString(ToTraceAsString { + inner: self.inner, + ty: self.ty.canonical_trace_as_string(), + literal_bits: self.literal_bits, + target: self.target, + }) + .intern(), + __ty: self.ty, + __flow: Expr::flow(self.inner), + } + } +} + +#[derive(Copy, Clone, PartialEq, Eq, Hash)] +pub struct TraceAsStringAsInner { + arg: Expr>, + ty: T, + literal_bits: Result, NotALiteralExpr>, + target: Option>, +} + +impl fmt::Debug for TraceAsStringAsInner { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let Self { + arg, + ty: _, + literal_bits: _, + target: _, + } = self; + f.debug_struct("TraceAsStringAsInner") + .field("arg", arg) + .finish_non_exhaustive() + } +} + +impl TraceAsStringAsInner { + pub fn from_arg_and_ty(arg: Expr>, ty: T) -> Self { + assert_eq!(arg.ty().inner_ty(), ty.canonical()); + let literal_bits = arg.to_literal_bits(); + let target = arg.target().map(|base| { + Intern::intern_sized( + base.join(TargetPathElement::intern_sized( + TargetPathTraceAsStringInner {}.into(), + )) + .canonicalized(), + ) + }); + Self { + arg, + ty, + literal_bits, + target, + } + } + pub fn new(arg: Expr>) -> Self { + Self::from_arg_and_ty( + Expr { + __enum: arg.__enum, + __ty: arg.__ty.canonical_trace_as_string(), + __flow: arg.__flow, + }, + arg.ty().inner_ty(), + ) + } + pub fn arg(self) -> Expr> { + self.arg + } + pub fn arg_typed(self) -> Expr> { + Expr { + __enum: self.arg.__enum, + __ty: TraceAsString::from_canonical_trace_as_string(self.arg.__ty), + __flow: self.arg.__flow, + } + } +} + +impl GetTarget for TraceAsStringAsInner { + fn target(&self) -> Option> { + self.target + } +} + +impl ToLiteralBits for TraceAsStringAsInner { + fn to_literal_bits(&self) -> Result, NotALiteralExpr> { + self.literal_bits + } +} + +impl ValueType for TraceAsStringAsInner { + type Type = T; + type ValueCategory = ValueCategoryExpr; + + fn ty(&self) -> Self::Type { + self.ty + } +} + +impl ToExpr for TraceAsStringAsInner { + fn to_expr(&self) -> Expr { + Expr { + __enum: ExprEnum::TraceAsStringAsInner(TraceAsStringAsInner { + arg: self.arg, + ty: self.ty.canonical(), + literal_bits: self.literal_bits, + target: self.target, + }) + .intern(), + __ty: self.ty, + __flow: Expr::flow(self.arg), + } + } +} diff --git a/crates/fayalite/src/expr/target.rs b/crates/fayalite/src/expr/target.rs index 95d8e0f..9016111 100644 --- a/crates/fayalite/src/expr/target.rs +++ b/crates/fayalite/src/expr/target.rs @@ -10,7 +10,7 @@ use crate::{ reg::Reg, reset::{AsyncReset, Reset, ResetType, ResetTypeDispatch, SyncReset}, source_location::SourceLocation, - ty::{CanonicalType, Type}, + ty::{CanonicalType, TraceAsString, Type}, wire::Wire, }; use std::fmt; @@ -46,11 +46,33 @@ impl fmt::Display for TargetPathDynArrayElement { } } +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub struct TargetPathTraceAsStringInner {} + +impl fmt::Display for TargetPathTraceAsStringInner { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + write!(f, ".") + } +} + +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub struct TargetPathToTraceAsString { + pub ty: TraceAsString, +} + +impl fmt::Display for TargetPathToTraceAsString { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + write!(f, ".to_trace_as_string(...)") + } +} + #[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] pub enum TargetPathElement { BundleField(TargetPathBundleField), ArrayElement(TargetPathArrayElement), DynArrayElement(TargetPathDynArrayElement), + TraceAsStringInner(TargetPathTraceAsStringInner), + ToTraceAsString(TargetPathToTraceAsString), } impl From for TargetPathElement { @@ -71,12 +93,26 @@ impl From for TargetPathElement { } } +impl From for TargetPathElement { + fn from(value: TargetPathTraceAsStringInner) -> Self { + Self::TraceAsStringInner(value) + } +} + +impl From for TargetPathElement { + fn from(value: TargetPathToTraceAsString) -> Self { + Self::ToTraceAsString(value) + } +} + impl fmt::Display for TargetPathElement { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { match self { Self::BundleField(v) => v.fmt(f), Self::ArrayElement(v) => v.fmt(f), Self::DynArrayElement(v) => v.fmt(f), + Self::TraceAsStringInner(v) => v.fmt(f), + Self::ToTraceAsString(v) => v.fmt(f), } } } @@ -100,6 +136,15 @@ impl TargetPathElement { let parent_ty = Array::::from_canonical(parent.canonical_ty()); parent_ty.element() } + Self::TraceAsStringInner(_) => { + let parent_ty = + TraceAsString::::from_canonical(parent.canonical_ty()); + parent_ty.inner_ty() + } + &Self::ToTraceAsString(TargetPathToTraceAsString { ty }) => { + assert_eq!(parent.canonical_ty(), ty.inner_ty()); + ty.canonical() + } } } pub fn flow(&self, parent: Interned) -> Flow { @@ -111,13 +156,18 @@ impl TargetPathElement { .expect("field name is known to be a valid field of parent type"); parent.flow().flip_if(field.flipped) } - Self::ArrayElement(_) => parent.flow(), - Self::DynArrayElement(_) => parent.flow(), + Self::ArrayElement(_) + | Self::DynArrayElement(_) + | Self::TraceAsStringInner(_) + | Self::ToTraceAsString(_) => parent.flow(), } } pub fn is_static(&self) -> bool { match self { - Self::BundleField(_) | Self::ArrayElement(_) => true, + Self::BundleField(_) + | Self::ArrayElement(_) + | Self::TraceAsStringInner(_) + | Self::ToTraceAsString(_) => true, Self::DynArrayElement(_) => false, } } @@ -314,6 +364,7 @@ pub struct TargetChild { path_element: Interned, canonical_ty: CanonicalType, flow: Flow, + canonicalized_if_different: Option>, } impl fmt::Debug for TargetChild { @@ -323,6 +374,7 @@ impl fmt::Debug for TargetChild { path_element, canonical_ty: _, flow: _, + canonicalized_if_different: _, } = self; parent.fmt(f)?; fmt::Display::fmt(path_element, f) @@ -336,6 +388,7 @@ impl fmt::Display for TargetChild { path_element, canonical_ty: _, flow: _, + canonicalized_if_different: _, } = self; parent.fmt(f)?; path_element.fmt(f) @@ -343,14 +396,69 @@ impl fmt::Display for TargetChild { } impl TargetChild { - pub fn new(parent: Interned, path_element: Interned) -> Self { + fn new_helper( + parent: Interned, + path_element: Interned, + canonicalized_if_different: Option>, + ) -> Self { Self { parent, path_element, canonical_ty: path_element.canonical_ty(parent), flow: path_element.flow(parent), + canonicalized_if_different, } } + fn make_canonicalized_if_different( + parent: Interned, + path_element: Interned, + ) -> Option> { + use TargetPathElement::*; + match *path_element { + BundleField(_) => {} + ArrayElement(_) => {} + DynArrayElement(_) => {} + TraceAsStringInner(_) => { + if let Some(child) = parent.canonicalized().child() { + match *child.path_element() { + BundleField(_) + | ArrayElement(_) + | DynArrayElement(_) + | TraceAsStringInner(_) => {} + ToTraceAsString(_) => return Some(child.parent()), + } + } + } + ToTraceAsString(TargetPathToTraceAsString { ty }) => { + if let Some(child) = parent.canonicalized().child() { + match *child.path_element() { + BundleField(_) | ArrayElement(_) | DynArrayElement(_) + | ToTraceAsString(_) => {} + TraceAsStringInner(_) => { + if ty.canonical() == child.parent().canonical_ty() { + return Some(child.parent()); + } + } + } + } + } + } + Some( + Target::Child(Self::new_helper( + parent.canonicalized_if_different()?, + path_element, + None, + )) + .intern_sized(), + ) + } + pub fn new(parent: Interned, path_element: Interned) -> Self { + Self::new_helper( + parent, + path_element, + Self::make_canonicalized_if_different(parent, path_element), + ) + } pub fn parent(self) -> Interned { self.parent } @@ -363,6 +471,19 @@ impl TargetChild { pub fn flow(self) -> Flow { self.flow } + pub fn is_canonicalized(self) -> bool { + self.canonicalized_if_different.is_none() + } + pub fn canonicalized_if_different(self) -> Option> { + self.canonicalized_if_different + } + #[must_use] + pub fn canonicalized(self) -> Target { + match self.canonicalized_if_different { + Some(v) => *v, + None => Target::Child(self), + } + } pub fn bundle_field(self) -> Option { if let TargetPathElement::BundleField(TargetPathBundleField { name }) = *self.path_element { let parent_ty = Bundle::from_canonical(self.parent.canonical_ty()); @@ -443,6 +564,82 @@ impl Target { Target::Child(v) => v.canonical_ty(), } } + pub fn is_canonicalized(self) -> bool { + match self { + Self::Base(_) => true, + Self::Child(child) => child.is_canonicalized(), + } + } + pub fn canonicalized_if_different(self) -> Option> { + match self { + Self::Base(_) => None, + Self::Child(child) => child.canonicalized_if_different(), + } + } + #[must_use] + pub fn canonicalized(self) -> Target { + match self.canonicalized_if_different() { + Some(v) => *v, + None => self, + } + } + #[must_use] + pub fn canonicalized_interned(this: Interned) -> Interned { + this.canonicalized_if_different().unwrap_or(this) + } + #[must_use] + pub fn unwrap_transparent_types(mut self) -> Target { + loop { + self = self.canonicalized(); + match self.canonical_ty() { + CanonicalType::UInt(_) + | CanonicalType::SInt(_) + | CanonicalType::Bool(_) + | CanonicalType::Array(_) + | CanonicalType::Enum(_) + | CanonicalType::Bundle(_) + | CanonicalType::AsyncReset(_) + | CanonicalType::SyncReset(_) + | CanonicalType::Reset(_) + | CanonicalType::Clock(_) + | CanonicalType::PhantomConst(_) + | CanonicalType::DynSimOnly(_) => return self, + CanonicalType::TraceAsString(_) => { + if let Self::Child(child) = self + && let TargetPathElement::ToTraceAsString(_) = *child.path_element() + { + self = *child.parent(); + } else { + self = self.join(TargetPathElement::intern_sized( + TargetPathTraceAsStringInner {}.into(), + )); + } + } + } + } + } + #[must_use] + pub fn unwrap_transparent_types_interned(this: Interned) -> Interned { + let retval = this.unwrap_transparent_types(); + if retval != *this { + retval.intern_sized() + } else { + this + } + } + #[must_use] + pub fn without_trailing_transparent_path_elements(mut self) -> Target { + use TargetPathElement::*; + loop { + match self { + Self::Base(_) => return self, + Self::Child(child) => match *child.path_element() { + BundleField(_) | ArrayElement(_) | DynArrayElement(_) => return self, + TraceAsStringInner(_) | ToTraceAsString(_) => self = *child.parent(), + }, + } + } + } } impl fmt::Display for Target { diff --git a/crates/fayalite/src/firrtl.rs b/crates/fayalite/src/firrtl.rs index 383bd95..51aa040 100644 --- a/crates/fayalite/src/firrtl.rs +++ b/crates/fayalite/src/firrtl.rs @@ -16,6 +16,7 @@ use crate::{ ops::{self, VariantAccess}, target::{ Target, TargetBase, TargetPathArrayElement, TargetPathBundleField, TargetPathElement, + TargetPathTraceAsStringInner, }, }, formal::FormalKind, @@ -471,7 +472,7 @@ impl TypeState { Ok(self.enum_def(ty)?.1.variants.borrow_mut().get(name)) } fn ty(&self, ty: T) -> Result { - Ok(match ty.canonical() { + Ok(match ty.canonical().unwrap_transparent_types() { CanonicalType::Bundle(ty) => self.bundle_ty(ty)?.to_string(), CanonicalType::Enum(ty) => self.enum_ty(ty)?.to_string(), CanonicalType::Array(ty) => { @@ -490,6 +491,7 @@ impl TypeState { CanonicalType::DynSimOnly(_) => { return Err(FirrtlError::SimOnlyValuesAreNotPermitted); } + CanonicalType::TraceAsString(_) => unreachable!("handled by unwrap_transparent_types"), }) } } @@ -1191,7 +1193,7 @@ impl<'a> Exporter<'a> { definitions: &RcDefinitions, extra_indent: Indent<'_>, ) -> Result { - match ty { + match ty.unwrap_transparent_types() { CanonicalType::Bundle(ty) => { self.expr_cast_bundle_to_bits(value_str, ty, definitions, extra_indent) } @@ -1210,6 +1212,7 @@ impl<'a> Exporter<'a> { | CanonicalType::Reset(_) => Ok(format!("asUInt({value_str})")), CanonicalType::PhantomConst(_) => Ok("UInt<0>(0)".into()), CanonicalType::DynSimOnly(_) => Err(FirrtlError::SimOnlyValuesAreNotPermitted.into()), + CanonicalType::TraceAsString(_) => unreachable!("handled by unwrap_transparent_types"), } } fn expr_cast_bits_to_bundle( @@ -1407,7 +1410,7 @@ impl<'a> Exporter<'a> { definitions: &RcDefinitions, extra_indent: Indent<'_>, ) -> Result { - match ty { + match ty.unwrap_transparent_types() { CanonicalType::Bundle(ty) => { self.expr_cast_bits_to_bundle(value_str, ty, definitions, extra_indent) } @@ -1431,6 +1434,7 @@ impl<'a> Exporter<'a> { return Ok(retval.to_string()); } CanonicalType::DynSimOnly(_) => Err(FirrtlError::SimOnlyValuesAreNotPermitted.into()), + CanonicalType::TraceAsString(_) => unreachable!("handled by unwrap_transparent_types"), } } fn expr_unary( @@ -1798,6 +1802,10 @@ impl<'a> Exporter<'a> { write!(out, "[{index}]").unwrap(); Ok(out) } + ExprEnum::ToTraceAsString(expr) => self.expr(expr.inner(), definitions, const_ty), + ExprEnum::TraceAsStringAsInner(expr) => { + self.expr(Expr::canonical(expr.arg()), definitions, const_ty) + } ExprEnum::ModuleIO(expr) => Ok(self.module.ns.get(expr.name_id()).to_string()), ExprEnum::Instance(expr) => { assert!(!const_ty, "not a constant"); @@ -1957,6 +1965,10 @@ impl<'a> Exporter<'a> { .segments .push(AnnotationTargetRefSegment::Index { index }), TargetPathElement::DynArrayElement(_) => unreachable!(), + TargetPathElement::ToTraceAsString(_) + | TargetPathElement::TraceAsStringInner(_) => { + // ignored + } } Ok(retval) } @@ -3211,6 +3223,8 @@ impl ScalarizeTreeNode { TargetPathElement::DynArrayElement(_) => { unreachable!("annotations are only on static targets"); } + TargetPathElement::ToTraceAsString(_) + | TargetPathElement::TraceAsStringInner(_) => parent, } } } @@ -3337,6 +3351,13 @@ impl ScalarizeTreeBuilder { CanonicalType::DynSimOnly(_) => { return Err(ScalarizedModuleABIError::SimOnlyValuesAreNotPermitted); } + CanonicalType::TraceAsString(_) => self.build( + target + .join(TargetPathElement::intern_sized( + TargetPathTraceAsStringInner {}.into(), + )) + .intern_sized(), + )?, }) } } diff --git a/crates/fayalite/src/int.rs b/crates/fayalite/src/int.rs index 2d1f6d2..15f8ed1 100644 --- a/crates/fayalite/src/int.rs +++ b/crates/fayalite/src/int.rs @@ -10,13 +10,13 @@ use crate::{ value_category::ValueCategoryValue, }, hdl, - intern::{Intern, Interned, Memoize}, + intern::{Intern, Interned, Memoize, OnceInterned}, sim::value::{SimValue, ToSimValueWithType}, source_location::SourceLocation, ty::{ CanonicalType, FillInDefaultedGenerics, OpaqueSimValueSize, OpaqueSimValueSlice, - OpaqueSimValueWriter, OpaqueSimValueWritten, StaticType, Type, TypeProperties, - impl_match_variant_as_self, + OpaqueSimValueWriter, OpaqueSimValueWritten, SimValueDebug, SimValueDisplay, StaticType, + Type, TypeProperties, impl_match_variant_as_self, }, util::{ConstBool, ConstUsize, GenericConstBool, GenericConstUsize, interned_bit, slice_range}, }; @@ -65,14 +65,21 @@ pub type DynSize = ConstUsize; trait KnownSizeBaseSealed {} -impl KnownSizeBaseSealed for [(); N] {} +impl KnownSizeBaseSealed for ConstUsize {} #[expect(private_bounds)] -pub trait KnownSizeBase: KnownSizeBaseSealed {} +pub trait KnownSizeBase: KnownSizeBaseSealed + GetInternedIntCaches {} macro_rules! impl_known_size_base { ($($size:literal),* $(,)?) => { - $(impl KnownSizeBase for [(); $size] {})* + $(impl KnownSizeBase for ConstUsize<$size> {})* + $(impl GetInternedIntCaches for ConstUsize<$size> { + #[inline(always)] + fn get_interned_int_caches() -> &'static InternedIntCaches { + static CACHES: InternedIntCaches> = InternedIntCaches::new(); + &CACHES + } + })* }; } @@ -113,12 +120,34 @@ impl_known_size_base! { 0x200, } +trait GetInternedIntCaches { + fn get_interned_int_caches() -> &'static InternedIntCaches + where + Self: KnownSize; +} + +struct InternedIntCaches { + uint: OnceInterned>, + sint: OnceInterned>, +} + +impl InternedIntCaches { + const fn new() -> Self { + Self { + uint: OnceInterned::new(), + sint: OnceInterned::new(), + } + } +} + +#[expect(private_bounds)] pub trait KnownSize: GenericConstUsize + sealed::SizeTypeSealed + sealed::SizeSealed + Default + FillInDefaultedGenerics + + GetInternedIntCaches { const SIZE: Self; type ArrayMatch: AsRef<[Expr]> @@ -148,7 +177,7 @@ pub trait KnownSize: impl KnownSize for ConstUsize where - [(); N]: KnownSizeBase, + ConstUsize: KnownSizeBase, { const SIZE: Self = Self; type ArrayMatch = [Expr; N]; @@ -221,6 +250,10 @@ pub trait Size: fn from_usize(v: usize) -> Self::SizeType { Self::try_from_usize(v).expect("wrong size") } + #[doc(hidden)] + fn interned_uint(size_type: Self::SizeType) -> Interned>; + #[doc(hidden)] + fn interned_sint(size_type: Self::SizeType) -> Interned>; } impl sealed::SizeTypeSealed for usize {} @@ -229,6 +262,8 @@ impl SizeType for usize { type Size = DynSize; } +const MAX_CACHED_INT_WIDTH: usize = 1 << 10; + impl Size for DynSize { type ArrayMatch = Box<[Expr]>; type ArraySimValue = Box<[SimValue]>; @@ -242,6 +277,36 @@ impl Size for DynSize { fn try_from_usize(v: usize) -> Option { Some(v) } + + #[doc(hidden)] + fn interned_uint(size_type: Self::SizeType) -> Interned> { + static CACHED: [OnceInterned; MAX_CACHED_INT_WIDTH] = + [const { OnceInterned::new() }; _]; + #[cold] + fn intern_cold(width: usize) -> Interned { + Intern::intern_sized(UInt::new(width)) + } + if let Some(cached) = CACHED.get(size_type) { + cached.get_or_init(|| intern_cold(size_type)) + } else { + intern_cold(size_type) + } + } + + #[doc(hidden)] + fn interned_sint(size_type: Self::SizeType) -> Interned> { + static CACHED: [OnceInterned; MAX_CACHED_INT_WIDTH] = + [const { OnceInterned::new() }; _]; + #[cold] + fn intern_cold(width: usize) -> Interned { + Intern::intern_sized(SInt::new(width)) + } + if let Some(cached) = CACHED.get(size_type) { + cached.get_or_init(|| intern_cold(size_type)) + } else { + intern_cold(size_type) + } + } } impl sealed::SizeSealed for ConstUsize {} @@ -267,6 +332,20 @@ impl Size for T { fn try_from_usize(v: usize) -> Option { if v == T::VALUE { Some(T::SIZE) } else { None } } + + #[doc(hidden)] + fn interned_uint(_size_type: Self::SizeType) -> Interned> { + T::get_interned_int_caches() + .uint + .get_or_init(|| UIntType::new_static().intern_sized()) + } + + #[doc(hidden)] + fn interned_sint(_size_type: Self::SizeType) -> Interned> { + T::get_interned_int_caches() + .sint + .get_or_init(|| SIntType::new_static().intern_sized()) + } } #[derive(Clone, PartialEq, Eq, Debug)] @@ -586,7 +665,7 @@ macro_rules! impl_valueless_op_forward { } macro_rules! impl_int { - ($pretty_name:ident, $name:ident, $generic_name:ident, $value:ident, $SIGNED:literal) => { + ($pretty_name:ident, $name:ident, $generic_name:ident, $value:ident, $SIGNED:literal, $interned_int:ident) => { #[derive(Copy, Clone, PartialEq, Eq, Hash)] #[repr(transparent)] pub struct $name { @@ -940,6 +1019,24 @@ macro_rules! impl_int { } } + impl SimValueDebug for $name { + fn sim_value_debug( + value: &::SimValue, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + fmt::Debug::fmt(value, f) + } + } + + impl SimValueDisplay for $name { + fn sim_value_display( + value: &::SimValue, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + fmt::Display::fmt(value, f) + } + } + impl Default for $name { fn default() -> Self { Self::TYPE @@ -1003,7 +1100,7 @@ macro_rules! impl_int { type Output = $name; fn index(&self, width: Width) -> &Self::Output { - Interned::into_inner(Intern::intern_sized($name::new(width))) + Interned::into_inner(Width::Size::$interned_int(width)) } } @@ -1180,12 +1277,29 @@ macro_rules! impl_int { pub fn bitvec_mut(&mut self) -> &mut BitVec { Arc::make_mut(&mut self.bits) } + pub fn arc_bitvec_mut(&mut self) -> &mut Arc { + &mut self.bits + } } }; } -impl_int!(UInt, UIntType, UIntWithoutGenerics, UIntValue, false); -impl_int!(SInt, SIntType, SIntWithoutGenerics, SIntValue, true); +impl_int!( + UInt, + UIntType, + UIntWithoutGenerics, + UIntValue, + false, + interned_uint +); +impl_int!( + SInt, + SIntType, + SIntWithoutGenerics, + SIntValue, + true, + interned_sint +); impl UInt { /// gets the smallest `UInt` that fits `v` losslessly @@ -1806,6 +1920,15 @@ impl Type for Bool { } } +impl SimValueDebug for Bool { + fn sim_value_debug( + value: &::SimValue, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + fmt::Debug::fmt(value, f) + } +} + impl StaticType for Bool { const TYPE: Self = Bool; const MASK_TYPE: Self::MaskType = Bool; diff --git a/crates/fayalite/src/int/uint_in_range.rs b/crates/fayalite/src/int/uint_in_range.rs index acf2fec..edf2e25 100644 --- a/crates/fayalite/src/int/uint_in_range.rs +++ b/crates/fayalite/src/int/uint_in_range.rs @@ -14,7 +14,7 @@ use crate::{ source_location::SourceLocation, ty::{ CanonicalType, OpaqueSimValueSlice, OpaqueSimValueWriter, OpaqueSimValueWritten, - StaticType, Type, TypeProperties, impl_match_variant_as_self, + SimValueDebug, StaticType, Type, TypeProperties, impl_match_variant_as_self, }, }; use bitvec::{order::Lsb0, view::BitView}; @@ -94,6 +94,15 @@ impl Type for UIntInRangeMaskType { } } +impl SimValueDebug for UIntInRangeMaskType { + fn sim_value_debug( + value: &::SimValue, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + fmt::Debug::fmt(value, f) + } +} + impl BundleType for UIntInRangeMaskType { type Builder = NoBuilder; @@ -339,6 +348,15 @@ macro_rules! define_uint_in_range_type { } } + impl SimValueDebug for $UIntInRangeType { + fn sim_value_debug( + value: &::SimValue, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + fmt::Debug::fmt(value, f) + } + } + impl fmt::Debug for $UIntInRangeType { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { let Self { value, range } = self; diff --git a/crates/fayalite/src/intern.rs b/crates/fayalite/src/intern.rs index b68140b..b78aa59 100644 --- a/crates/fayalite/src/intern.rs +++ b/crates/fayalite/src/intern.rs @@ -4,68 +4,191 @@ use crate::{intern::type_map::TypeIdMap, util::DefaultBuildHasher}; use bitvec::{ptr::BitPtr, slice::BitSlice, vec::BitVec}; use hashbrown::HashTable; +use once_cell::race::OnceRef; use serde::{Deserialize, Serialize}; use std::{ any::{Any, TypeId}, borrow::{Borrow, Cow}, + cell::RefCell, cmp::Ordering, ffi::{OsStr, OsString}, fmt, hash::{BuildHasher, Hash, Hasher}, iter::FusedIterator, - marker::PhantomData, ops::Deref, path::{Path, PathBuf}, - sync::{Mutex, RwLock}, + sync::RwLock, }; +mod interner; mod type_map; -pub trait LazyInternedTrait: Send + Sync + Any { - fn get(&self) -> Interned; +/// invariant: T must be zero-sized, `type_id` is unique for every possible T value. +struct LazyInternedLazyInner { + type_id: TypeId, + value: T, } -impl Interned + Send + Sync + Any> - LazyInternedTrait for F -{ - fn get(&self) -> Interned { - self() +impl Hash for LazyInternedLazyInner { + fn hash(&self, state: &mut H) { + let Self { type_id, value: _ } = self; + type_id.hash(state); } } -#[repr(transparent)] -pub struct LazyInternedFn(pub &'static dyn LazyInternedTrait); +impl PartialEq for LazyInternedLazyInner { + fn eq(&self, other: &Self) -> bool { + let Self { type_id, value: _ } = self; + *type_id == other.type_id + } +} -impl Copy for LazyInternedFn {} +impl Eq for LazyInternedLazyInner {} -impl Clone for LazyInternedFn { +impl fmt::Debug for LazyInternedLazyInner { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_struct("LazyInternedLazyInner") + .finish_non_exhaustive() + } +} + +impl LazyInternedLazyInner { + const fn new(value: T) -> Self + where + T: Sized, + { + const { assert!(size_of::() == 0) }; + Self { + type_id: TypeId::of::(), + value, + } + } +} + +pub struct LazyInternedLazy( + &'static LazyInternedLazyInner Interned + Send + Sync>, +); + +impl LazyInternedLazy { + pub const fn new_const>>() -> Self { + Self(&const { LazyInternedLazyInner::new(|| V::default().into()) }) + } + pub const fn new_const_default() -> Self + where + Interned: Default, + { + Self::new_const::>() + } + pub fn interned(self) -> Interned { + struct Map(hashbrown::HashTable<(TypeId, &'static (dyn Any + Send + Sync))>); + impl Map { + const EMPTY: Self = Self(hashbrown::HashTable::new()); + fn get( + &self, + lazy_interned_lazy: LazyInternedLazy, + hash: u64, + ) -> Option<&'static Interned> { + let &(_, v) = self.0.find(hash, |v| v.0 == lazy_interned_lazy.0.type_id)?; + let Some(retval) = v.downcast_ref::>() else { + unreachable!(); + }; + Some(retval) + } + fn get_or_insert( + &mut self, + lazy_interned_lazy: LazyInternedLazy, + hash: u64, + v: &'static Interned, + ) -> &'static Interned { + let entry = self + .0 + .entry( + hash, + |&(k, _)| k == lazy_interned_lazy.0.type_id, + |&(k, _)| type_map::TypeIdBuildHasher.hash_one(k), + ) + .or_insert_with(|| (lazy_interned_lazy.0.type_id, v)); + let &(_, v) = entry.get(); + let Some(retval) = v.downcast_ref::>() else { + unreachable!(); + }; + retval + } + } + static GLOBAL_CACHE: RwLock = RwLock::new(Map::EMPTY); + #[cold] + fn insert_in_thread_local_cache( + cache: &RefCell, + this: LazyInternedLazy, + hash: u64, + ) -> Interned { + let read_lock = GLOBAL_CACHE.read().unwrap(); + let v = read_lock.get(this, hash); + drop(read_lock); + let v = v.unwrap_or_else(|| { + let v = Box::leak(Box::new((this.0.value)())); + GLOBAL_CACHE.write().unwrap().get_or_insert(this, hash, v) + }); + *cache.borrow_mut().get_or_insert(this, hash, v) + } + thread_local! { + static THREAD_LOCAL_CACHE: RefCell = const { RefCell::new(Map::EMPTY) }; + } + let hash = type_map::TypeIdBuildHasher.hash_one(self.0.type_id); + THREAD_LOCAL_CACHE.with(|cache| { + let borrow = cache.borrow(); + if let Some(v) = borrow.get(self, hash) { + *v + } else { + drop(borrow); + insert_in_thread_local_cache(cache, self, hash) + } + }) + } +} + +impl Copy for LazyInternedLazy {} + +impl Clone for LazyInternedLazy { fn clone(&self) -> Self { *self } } -impl Hash for LazyInternedFn { +impl Hash for LazyInternedLazy { fn hash(&self, state: &mut H) { - self.0.get_ptr_eq_with_type_id().hash(state); + self.0.hash(state); } } -impl Eq for LazyInternedFn {} +impl Eq for LazyInternedLazy {} -impl PartialEq for LazyInternedFn { +impl PartialEq for LazyInternedLazy { fn eq(&self, other: &Self) -> bool { - self.0.get_ptr_eq_with_type_id() == other.0.get_ptr_eq_with_type_id() + self.0 == other.0 } } pub enum LazyInterned { Interned(Interned), - Lazy(LazyInternedFn), + Lazy(LazyInternedLazy), } impl LazyInterned { - pub const fn new_lazy(v: &'static dyn LazyInternedTrait) -> Self { - Self::Lazy(LazyInternedFn(v)) + pub const fn new_const>>() -> Self { + Self::Lazy(LazyInternedLazy::new_const::()) + } + pub const fn new_const_default() -> Self + where + Interned: Default, + { + Self::new_const::>() + } + pub fn interned(self) -> Interned { + match self { + Self::Interned(retval) => retval, + Self::Lazy(retval) => retval.interned(), + } } } @@ -77,7 +200,7 @@ impl Clone for LazyInterned { impl Copy for LazyInterned {} -impl Deref for LazyInterned { +impl Deref for LazyInterned { type Target = T; fn deref(&self) -> &Self::Target { @@ -85,9 +208,9 @@ impl Deref for LazyInterned { } } -impl Eq for LazyInterned where Interned: Eq {} +impl Eq for LazyInterned where Interned: Eq {} -impl PartialEq for LazyInterned +impl PartialEq for LazyInterned where Interned: PartialEq, { @@ -96,7 +219,7 @@ where } } -impl Ord for LazyInterned +impl Ord for LazyInterned where Interned: Ord, { @@ -105,7 +228,7 @@ where } } -impl PartialOrd for LazyInterned +impl PartialOrd for LazyInterned where Interned: PartialOrd, { @@ -114,7 +237,7 @@ where } } -impl Hash for LazyInterned +impl Hash for LazyInterned where Interned: Hash, { @@ -123,77 +246,6 @@ where } } -impl LazyInterned { - pub fn interned(self) -> Interned - where - T: Intern, - { - struct MemoizeInterned(PhantomData); - - impl Hash for MemoizeInterned { - fn hash(&self, _state: &mut H) {} - } - - impl PartialEq for MemoizeInterned { - fn eq(&self, _other: &Self) -> bool { - true - } - } - - impl Eq for MemoizeInterned {} - - impl Clone for MemoizeInterned { - fn clone(&self) -> Self { - *self - } - } - - impl Copy for MemoizeInterned {} - - impl MemoizeGeneric for MemoizeInterned { - type InputRef<'a> = LazyInternedFn; - - type InputOwned = LazyInternedFn; - - type InputCow<'a> = LazyInternedFn; - - type Output = Interned; - - fn input_eq(a: Self::InputRef<'_>, b: Self::InputRef<'_>) -> bool { - a == b - } - - fn input_borrow(input: &Self::InputOwned) -> Self::InputRef<'_> { - *input - } - - fn input_cow_into_owned(input: Self::InputCow<'_>) -> Self::InputOwned { - input - } - - fn input_cow_borrow<'a>(input: &'a Self::InputCow<'_>) -> Self::InputRef<'a> { - *input - } - - fn input_cow_from_owned<'a>(input: Self::InputOwned) -> Self::InputCow<'a> { - input - } - - fn input_cow_from_ref(input: Self::InputRef<'_>) -> Self::InputCow<'_> { - input - } - - fn inner(self, input: Self::InputRef<'_>) -> Self::Output { - input.0.get() - } - } - match self { - Self::Interned(retval) => retval, - Self::Lazy(retval) => MemoizeInterned(PhantomData).get(retval), - } - } -} - pub trait InternedCompare { type InternedCompareKey: Ord + Hash; fn interned_compare_key_ref(this: &Self) -> Self::InternedCompareKey; @@ -593,71 +645,6 @@ impl From> for Cow<'_, } } -struct InternerState { - table: HashTable<&'static T>, - hasher: DefaultBuildHasher, -} - -pub struct Interner { - state: Mutex>, -} - -impl Interner { - fn get() -> &'static Interner { - static TYPE_ID_MAP: TypeIdMap = TypeIdMap::new(); - TYPE_ID_MAP.get_or_insert_default() - } -} - -impl Default for Interner { - fn default() -> Self { - Self { - state: Mutex::new(InternerState { - table: HashTable::new(), - hasher: Default::default(), - }), - } - } -} - -impl Interner { - fn intern) -> &'static T>( - &self, - alloc: F, - value: Cow<'_, T>, - ) -> Interned { - let mut state = self.state.lock().unwrap(); - let InternerState { table, hasher } = &mut *state; - let inner = *table - .entry( - hasher.hash_one(&*value), - |k| **k == *value, - |k| hasher.hash_one(&**k), - ) - .or_insert_with(|| alloc(value)) - .get(); - Interned { inner } - } -} - -impl Interner { - fn intern_sized(&self, value: Cow<'_, T>) -> Interned { - self.intern(|value| Box::leak(Box::new(value.into_owned())), value) - } -} - -impl Interner<[T]> { - fn intern_slice(&self, value: Cow<'_, [T]>) -> Interned<[T]> { - self.intern(|value| value.into_owned().leak(), value) - } -} - -impl Interner { - fn intern_bit_slice(&self, value: Cow<'_, BitSlice>) -> Interned { - self.intern(|value| value.into_owned().leak(), value) - } -} - pub struct Interned { inner: &'static T, } @@ -977,7 +964,7 @@ impl Intern for T { where Self: ToOwned, { - Interner::get().intern_sized(this) + interner::Interner::get().intern_sized(this) } } @@ -997,7 +984,7 @@ impl Intern for [T] { where Self: ToOwned, { - Interner::get().intern_slice(this) + interner::Interner::get().intern_slice(this) } } @@ -1017,7 +1004,7 @@ impl Intern for BitSlice { where Self: ToOwned, { - Interner::get().intern_bit_slice(this) + interner::Interner::get().intern_bit_slice(this) } } @@ -1035,10 +1022,17 @@ pub trait MemoizeGeneric: 'static + Send + Sync + Hash + Eq + Copy { fn inner(self, input: Self::InputRef<'_>) -> Self::Output; fn get_cow(self, input: Self::InputCow<'_>) -> Self::Output { static TYPE_ID_MAP: TypeIdMap = TypeIdMap::new(); + thread_local! { + static TYPE_ID_MAP_CACHE: TypeIdMap = const { TypeIdMap::new() }; + } let map: &RwLock<( DefaultBuildHasher, HashTable<(Self, Self::InputOwned, Self::Output)>, - )> = TYPE_ID_MAP.get_or_insert_default(); + )> = TYPE_ID_MAP_CACHE.with(|cache| { + cache.get_or_insert_with(|| { + TYPE_ID_MAP.get_or_insert_with(|| Box::leak(Default::default())) + }) + }); fn hash_eq_key<'a, 'b, T: MemoizeGeneric>( this: &'a T, input: T::InputRef<'b>, @@ -1140,3 +1134,35 @@ pub trait Memoize: 'static + Send + Sync + Hash + Eq + Copy { self.get_cow(Cow::Borrowed(input)) } } + +/// like `once_cell::race::OnceBox` but for `Interned` instead of `Box` +pub struct OnceInterned(OnceRef<'static, T>); + +impl fmt::Debug for OnceInterned { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_tuple("OnceInterned").field(&self.get()).finish() + } +} + +impl Default for OnceInterned { + fn default() -> Self { + Self::new() + } +} + +impl OnceInterned { + pub const fn new() -> Self { + Self(OnceRef::new()) + } + pub fn set(&self, v: Interned) -> Result<(), ()> { + self.0.set(v.inner) + } + pub fn get(&self) -> Option> { + self.0.get().map(|inner| Interned { inner }) + } + pub fn get_or_init Interned>(&self, f: F) -> Interned { + Interned { + inner: self.0.get_or_init(|| f().inner), + } + } +} diff --git a/crates/fayalite/src/intern/interner.rs b/crates/fayalite/src/intern/interner.rs new file mode 100644 index 0000000..4e35636 --- /dev/null +++ b/crates/fayalite/src/intern/interner.rs @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: LGPL-3.0-or-later +// See Notices.txt for copyright information + +use crate::{ + intern::{Interned, type_map::TypeIdMap}, + util::DefaultBuildHasher, +}; +use bitvec::slice::BitSlice; +use hashbrown::HashTable; +use std::{ + borrow::Cow, + hash::{BuildHasher, Hash}, + sync::RwLock, +}; + +struct InternerShard { + table: HashTable<&'static T>, +} + +const LOG2_SHARD_COUNT: u32 = 6; + +fn shard_index_from_hash(hash: u64) -> usize { + // number of bits used for hashbrown's Tag + const HASH_BROWN_TAG_BITS: u32 = 7; + // try to extract bits of the hash that hashbrown isn't using, + // while accounting for some hash functions only returning `usize` bits. + const SHARD_INDEX_START: u32 = usize::BITS + .saturating_sub(HASH_BROWN_TAG_BITS) + .saturating_sub(LOG2_SHARD_COUNT); + let mut shard_index = hash >> SHARD_INDEX_START; + shard_index %= 1 << LOG2_SHARD_COUNT; + shard_index as usize +} + +pub(crate) struct Interner { + shards: [RwLock>; 1 << LOG2_SHARD_COUNT], + hasher: DefaultBuildHasher, +} + +impl Interner { + pub(crate) fn get() -> &'static Interner { + static TYPE_ID_MAP: TypeIdMap = TypeIdMap::new(); + thread_local! { + static TYPE_ID_MAP_CACHE: TypeIdMap = const { TypeIdMap::new() }; + } + TYPE_ID_MAP_CACHE.with(|cache| { + cache.get_or_insert_with(|| { + TYPE_ID_MAP.get_or_insert_with(|| Box::leak(Default::default())) + }) + }) + } +} + +impl Default for Interner { + fn default() -> Self { + Self { + shards: [const { + RwLock::new(InternerShard { + table: HashTable::new(), + }) + }; _], + hasher: Default::default(), + } + } +} + +impl Interner { + fn intern) -> &'static T>( + &self, + alloc: F, + value: Cow<'_, T>, + ) -> Interned { + let hash = self.hasher.hash_one(&*value); + let shard_index = shard_index_from_hash(hash); + let shard = &self.shards[shard_index]; + let shard_read = shard.read().unwrap(); + let Some(&inner) = shard_read.table.find(hash, |k| **k == *value) else { + drop(shard_read); + return self.intern_cold(alloc, value, hash, shard); + }; + Interned { inner } + } + #[cold] + fn intern_cold) -> &'static T>( + &self, + alloc: F, + value: Cow<'_, T>, + hash: u64, + shard: &RwLock>, + ) -> Interned { + let mut shard = shard.write().unwrap(); + let inner = *shard + .table + .entry(hash, |k| **k == *value, |k| self.hasher.hash_one(&**k)) + .or_insert_with(|| alloc(value)) + .get(); + Interned { inner } + } +} + +impl Interner { + pub(crate) fn intern_sized(&self, value: Cow<'_, T>) -> Interned { + self.intern(|value| Box::leak(Box::new(value.into_owned())), value) + } +} + +impl Interner<[T]> { + pub(crate) fn intern_slice(&self, value: Cow<'_, [T]>) -> Interned<[T]> { + self.intern(|value| value.into_owned().leak(), value) + } +} + +impl Interner { + pub(crate) fn intern_bit_slice(&self, value: Cow<'_, BitSlice>) -> Interned { + self.intern(|value| value.into_owned().leak(), value) + } +} diff --git a/crates/fayalite/src/intern/type_map.rs b/crates/fayalite/src/intern/type_map.rs index 945116b..e31a5bf 100644 --- a/crates/fayalite/src/intern/type_map.rs +++ b/crates/fayalite/src/intern/type_map.rs @@ -6,7 +6,7 @@ use std::{ sync::RwLock, }; -struct TypeIdHasher(u64); +pub(crate) struct TypeIdHasher(u64); // assumes TypeId has at least 64 bits that is a good hash impl Hasher for TypeIdHasher { @@ -63,7 +63,7 @@ impl Hasher for TypeIdHasher { } } -struct TypeIdBuildHasher; +pub(crate) struct TypeIdBuildHasher; impl BuildHasher for TypeIdBuildHasher { type Hasher = TypeIdHasher; @@ -87,20 +87,23 @@ impl TypeIdMap { fn insert_slow( &self, type_id: TypeId, - make: fn() -> Box, + make: impl FnOnce() -> &'static (dyn Any + Sync + Send), ) -> &'static (dyn Any + Sync + Send) { - let value = Box::leak(make()); + let value = make(); let mut write_guard = self.0.write().unwrap(); *write_guard.entry(type_id).or_insert(value) } - pub(crate) fn get_or_insert_default(&self) -> &T { + pub(crate) fn get_or_insert_with( + &self, + make: impl FnOnce() -> &'static T, + ) -> &'static T { let type_id = TypeId::of::(); let read_guard = self.0.read().unwrap(); let retval = read_guard.get(&type_id).map(|v| *v); drop(read_guard); let retval = match retval { Some(retval) => retval, - None => self.insert_slow(type_id, move || Box::new(T::default())), + None => self.insert_slow(type_id, move || make()), }; retval.downcast_ref().expect("known to have correct TypeId") } diff --git a/crates/fayalite/src/memory.rs b/crates/fayalite/src/memory.rs index 83e7437..b3af13c 100644 --- a/crates/fayalite/src/memory.rs +++ b/crates/fayalite/src/memory.rs @@ -1093,6 +1093,7 @@ pub fn splat_mask(ty: T, value: Expr) -> Expr> { .to_expr(), )), CanonicalType::PhantomConst(_) => Expr::from_canonical(Expr::canonical(().to_expr())), + CanonicalType::TraceAsString(ty) => Expr::from_canonical(splat_mask(ty.inner_ty(), value)), } } diff --git a/crates/fayalite/src/module.rs b/crates/fayalite/src/module.rs index d959182..816a286 100644 --- a/crates/fayalite/src/module.rs +++ b/crates/fayalite/src/module.rs @@ -1111,7 +1111,10 @@ fn validate_clock_for_past( let mut target = clock_for_past; while let Target::Child(child) = target { match *child.path_element() { - TargetPathElement::BundleField(_) | TargetPathElement::ArrayElement(_) => {} + TargetPathElement::BundleField(_) + | TargetPathElement::ArrayElement(_) + | TargetPathElement::ToTraceAsString(_) + | TargetPathElement::TraceAsStringInner(_) => {} TargetPathElement::DynArrayElement(_) => { panic!( "clock_for_past: clock must be a static target (you can't use `Expr` array indexes):\n{clock_for_past:?}" @@ -1535,6 +1538,7 @@ impl TargetState { } } fn new(target: Interned, declared_in_block: usize) -> Self { + let target = Target::unwrap_transparent_types_interned(target); Self { target, inner: match target.canonical_ty() { @@ -1586,6 +1590,9 @@ impl TargetState { declared_in_block, written_in_blocks: RefCell::default(), }, + CanonicalType::TraceAsString(_) => { + unreachable!("handled by Target::unwrap_transparent_types_interned") + } }, } } @@ -1605,44 +1612,59 @@ impl AssertValidityState { } fn get_target_states<'a>( &'a self, - target: &Target, + target: Target, process_target_state: &dyn Fn(&'a TargetState, bool), ) -> Result<(), ()> { - match target { - Target::Base(target_base) => { - let target_state = self.get_base_state(*target_base)?; - process_target_state(target_state, false); - Ok(()) - } - Target::Child(target_child) => self.get_target_states( - &target_child.parent(), - &|target_state, exact_target_unknown| { - let TargetStateInner::Decomposed { subtargets } = &target_state.inner else { - unreachable!( - "TargetState::new makes TargetState tree match the Target type" - ); - }; - match *target_child.path_element() { - TargetPathElement::BundleField(_) => process_target_state( - subtargets - .get(&target_child.path_element()) - .expect("bundle fields filled in by TargetState::new"), - exact_target_unknown, - ), - TargetPathElement::ArrayElement(_) => process_target_state( - subtargets - .get(&target_child.path_element()) - .expect("array elements filled in by TargetState::new"), - exact_target_unknown, - ), - TargetPathElement::DynArrayElement(_) => { - for target_state in subtargets.values() { - process_target_state(target_state, true); + let mut target = target.unwrap_transparent_types(); + loop { + break match target { + Target::Base(target_base) => { + let target_state = self.get_base_state(target_base)?; + process_target_state(target_state, false); + Ok(()) + } + Target::Child(target_child) => match *target_child.path_element() { + TargetPathElement::BundleField(_) + | TargetPathElement::ArrayElement(_) + | TargetPathElement::DynArrayElement(_) => self.get_target_states( + *target_child.parent(), + &|target_state, exact_target_unknown| { + let TargetStateInner::Decomposed { subtargets } = &target_state.inner + else { + unreachable!( + "TargetState::new makes TargetState tree match the Target type" + ); + }; + match *target_child.path_element() { + TargetPathElement::BundleField(_) => process_target_state( + subtargets + .get(&target_child.path_element()) + .expect("bundle fields filled in by TargetState::new"), + exact_target_unknown, + ), + TargetPathElement::ArrayElement(_) => process_target_state( + subtargets + .get(&target_child.path_element()) + .expect("array elements filled in by TargetState::new"), + exact_target_unknown, + ), + TargetPathElement::DynArrayElement(_) => { + for target_state in subtargets.values() { + process_target_state(target_state, true); + } + } + TargetPathElement::TraceAsStringInner(_) + | TargetPathElement::ToTraceAsString(_) => unreachable!(), } - } + }, + ), + TargetPathElement::TraceAsStringInner(_) + | TargetPathElement::ToTraceAsString(_) => { + target = *target_child.parent(); + continue; } }, - ), + }; } } fn get_base_state(&self, target_base: Interned) -> Result<&TargetState, ()> { @@ -1693,6 +1715,7 @@ impl AssertValidityState { &TargetPathElement::BundleField(_) => { let field = sub_target_state .target + .without_trailing_transparent_path_elements() .child() .expect("known to be a child") .bundle_field() @@ -1716,6 +1739,8 @@ impl AssertValidityState { TargetPathElement::DynArrayElement { .. } => { Self::set_connect_target_written(sub_target_state, is_lhs, block, true); } + TargetPathElement::TraceAsStringInner(_) + | TargetPathElement::ToTraceAsString(_) => unreachable!("never added"), } } } @@ -1733,7 +1758,7 @@ impl AssertValidityState { debug_assert!(!is_lhs, "the ModuleBuilder asserts lhs.target().is_some()"); return; }; - let result = self.get_target_states(&target, &|target_state, exact_target_unknown| { + let result = self.get_target_states(*target, &|target_state, exact_target_unknown| { Self::set_connect_target_written(target_state, is_lhs, block, exact_target_unknown); }); if result.is_err() { diff --git a/crates/fayalite/src/module/transform/deduce_resets.rs b/crates/fayalite/src/module/transform/deduce_resets.rs index 61167fd..4595e84 100644 --- a/crates/fayalite/src/module/transform/deduce_resets.rs +++ b/crates/fayalite/src/module/transform/deduce_resets.rs @@ -10,7 +10,8 @@ use crate::{ ops::{self, ArrayLiteral}, target::{ Target, TargetBase, TargetChild, TargetPathArrayElement, TargetPathBundleField, - TargetPathDynArrayElement, TargetPathElement, + TargetPathDynArrayElement, TargetPathElement, TargetPathToTraceAsString, + TargetPathTraceAsStringInner, }, }, formal::FormalKind, @@ -26,6 +27,7 @@ use crate::{ prelude::*, reset::{ResetType, ResetTypeDispatch}, sim::ExternModuleSimulation, + ty::TraceAsString, util::{HashMap, HashSet}, }; use hashbrown::hash_map::Entry; @@ -103,6 +105,10 @@ enum ResetsLayout { element: Interned, reset_count: usize, }, + Transparent { + inner: Interned, + reset_count: usize, + }, } impl ResetsLayout { @@ -112,7 +118,8 @@ impl ResetsLayout { ResetsLayout::Reset | ResetsLayout::SyncReset | ResetsLayout::AsyncReset => 1, ResetsLayout::Bundle { reset_count, .. } | ResetsLayout::Enum { reset_count, .. } - | ResetsLayout::Array { reset_count, .. } => reset_count, + | ResetsLayout::Array { reset_count, .. } + | ResetsLayout::Transparent { reset_count, .. } => reset_count, } } fn new(ty: CanonicalType) -> Self { @@ -166,6 +173,13 @@ impl ResetsLayout { CanonicalType::Clock(_) => ResetsLayout::NoResets, CanonicalType::PhantomConst(_) => ResetsLayout::NoResets, CanonicalType::DynSimOnly(_) => ResetsLayout::NoResets, + CanonicalType::TraceAsString(ty) => { + let inner = ResetsLayout::new(ty.inner_ty()).intern_sized(); + ResetsLayout::Transparent { + inner, + reset_count: inner.reset_count(), + } + } } } } @@ -315,6 +329,12 @@ impl ResetGraph { } => { self.append_new_nodes_for_layout(*element, node_indexes, source_location); } + ResetsLayout::Transparent { + inner, + reset_count: _, + } => { + self.append_new_nodes_for_layout(*inner, node_indexes, source_location); + } } } } @@ -357,6 +377,21 @@ impl Resets { node_indexes: self.node_indexes, } } + fn trace_as_string_inner(self) -> Self { + let trace_as_string = TraceAsString::from_canonical(self.ty); + let ResetsLayout::Transparent { + inner, + reset_count: _, + } = self.layout + else { + unreachable!(); + }; + Self { + ty: trace_as_string.inner_ty(), + layout: *inner, + node_indexes: self.node_indexes, + } + } fn bundle_fields(self) -> impl Iterator { let bundle = Bundle::from_canonical(self.ty); let ResetsLayout::Bundle { @@ -480,6 +515,17 @@ impl Resets { CanonicalType::SyncReset(SyncReset) }, ), + CanonicalType::TraceAsString(ty) => Ok(CanonicalType::TraceAsString( + ty.with_new_inner_ty( + self.array_elements() + .substituted_type( + reset_graph, + fallback_to_sync_reset, + fallback_error_source_location, + )? + .intern_sized(), + ), + )), } } } @@ -1013,7 +1059,8 @@ fn cast_bit_op( | CanonicalType::Bundle(_) | CanonicalType::Reset(_) | CanonicalType::PhantomConst(_) - | CanonicalType::DynSimOnly(_) => unreachable!(), + | CanonicalType::DynSimOnly(_) + | CanonicalType::TraceAsString(_) => unreachable!(), $(CanonicalType::$Variant(ty) => Expr::expr_enum($arg.cast_to(ty)),)* } }; @@ -1024,7 +1071,8 @@ fn cast_bit_op( CanonicalType::Array(_) | CanonicalType::Enum(_) | CanonicalType::Bundle(_) - | CanonicalType::Reset(_) => unreachable!(), + | CanonicalType::Reset(_) + | CanonicalType::TraceAsString(_) => unreachable!(), CanonicalType::PhantomConst(_) | CanonicalType::DynSimOnly(_) => Expr::expr_enum(arg), $(CanonicalType::$Variant(_) => { @@ -1156,6 +1204,10 @@ impl RunPass

for ExprEnum { ExprEnum::SliceSInt(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)), ExprEnum::CastToBits(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)), ExprEnum::CastBitsTo(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)), + ExprEnum::TraceAsStringAsInner(expr) => { + Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)) + } + ExprEnum::ToTraceAsString(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)), ExprEnum::ModuleIO(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)), ExprEnum::Instance(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)), ExprEnum::Wire(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)), @@ -1536,6 +1588,67 @@ impl RunPassExpr for ops::CastBitsTo { } } +impl RunPassExpr for ops::TraceAsStringAsInner { + type Args<'a> = [Expr; 1]; + + fn args<'a>(&'a self) -> Self::Args<'a> { + [Expr::canonical(self.arg())] + } + + fn source_location(&self) -> Option { + None + } + + fn union_parts( + &self, + resets: Resets, + args_resets: Vec, + mut pass_args: PassArgs<'_, BuildResetGraph>, + ) -> Result<(), DeduceResetsError> { + pass_args.union(resets, args_resets[0].trace_as_string_inner(), None) + } + + fn new( + &self, + _ty: CanonicalType, + new_args: Vec>, + ) -> Result { + Ok(Self::new(Expr::from_canonical(new_args[0]))) + } +} + +impl RunPassExpr for ops::ToTraceAsString { + type Args<'a> = [Expr; 1]; + + fn args<'a>(&'a self) -> Self::Args<'a> { + [Expr::canonical(self.inner())] + } + + fn source_location(&self) -> Option { + None + } + + fn union_parts( + &self, + resets: Resets, + args_resets: Vec, + mut pass_args: PassArgs<'_, BuildResetGraph>, + ) -> Result<(), DeduceResetsError> { + pass_args.union(resets.trace_as_string_inner(), args_resets[0], None) + } + + fn new( + &self, + _ty: CanonicalType, + new_args: Vec>, + ) -> Result { + Ok(Self::new( + new_args[0], + self.ty().with_new_inner_ty(new_args[0].ty().intern_sized()), + )) + } +} + impl RunPassExpr for ModuleIO { type Args<'a> = [Expr; 0]; @@ -1691,7 +1804,8 @@ impl RunPassDispatch for AnyReg { | CanonicalType::Reset(_) | CanonicalType::Clock(_) | CanonicalType::PhantomConst(_) - | CanonicalType::DynSimOnly(_) => unreachable!(), + | CanonicalType::DynSimOnly(_) + | CanonicalType::TraceAsString(_) => unreachable!(), } }) } @@ -2173,30 +2287,6 @@ impl RunPass

for StmtDeclaration { } } -impl_run_pass_for_struct! { - impl[] RunPass for TargetPathBundleField { - name: _, - } -} - -impl_run_pass_for_struct! { - impl[] RunPass for TargetPathArrayElement { - index: _, - } -} - -impl_run_pass_for_struct! { - impl[] RunPass for TargetPathDynArrayElement {} -} - -impl_run_pass_for_enum! { - impl[] RunPass for TargetPathElement { - BundleField(v), - ArrayElement(v), - DynArrayElement(v), - } -} - impl_run_pass_for_enum! { impl[] RunPass for Target { Base(v), @@ -2204,11 +2294,28 @@ impl_run_pass_for_enum! { } } -impl_run_pass_for_struct! { - #[constructor = TargetChild::new(parent, path_element)] - impl[] RunPass for TargetChild { - parent(): _, - path_element(): _, +impl RunPass

for TargetChild { + fn run_pass( + &self, + mut pass_args: PassArgs<'_, P>, + ) -> Result, DeduceResetsError> { + Ok(self.parent().run_pass(pass_args.as_mut())?.map(|parent| { + let path_element = match *self.path_element() { + TargetPathElement::BundleField(TargetPathBundleField { name: _ }) + | TargetPathElement::ArrayElement(TargetPathArrayElement { index: _ }) + | TargetPathElement::DynArrayElement(TargetPathDynArrayElement {}) + | TargetPathElement::TraceAsStringInner(TargetPathTraceAsStringInner {}) => { + self.path_element() + } + TargetPathElement::ToTraceAsString(TargetPathToTraceAsString { ty }) => { + TargetPathElement::from(TargetPathToTraceAsString { + ty: ty.with_new_inner_ty(parent.canonical_ty().intern_sized()), + }) + .intern_sized() + } + }; + TargetChild::new(parent, path_element) + })) } } diff --git a/crates/fayalite/src/module/transform/simplify_enums.rs b/crates/fayalite/src/module/transform/simplify_enums.rs index 8902921..5f136f2 100644 --- a/crates/fayalite/src/module/transform/simplify_enums.rs +++ b/crates/fayalite/src/module/transform/simplify_enums.rs @@ -17,7 +17,7 @@ use crate::{ transform::visit::{Fold, Folder}, }, source_location::SourceLocation, - ty::{CanonicalType, Type}, + ty::{CanonicalType, TraceAsString, Type}, util::HashMap, wire::Wire, }; @@ -64,6 +64,7 @@ fn contains_any_enum_types(ty: CanonicalType) -> bool { .fields() .iter() .any(|field| contains_any_enum_types(field.ty)), + CanonicalType::TraceAsString(ty) => contains_any_enum_types(ty.inner_ty()), CanonicalType::UInt(_) | CanonicalType::SInt(_) | CanonicalType::Bool(_) @@ -313,6 +314,24 @@ impl State { } Ok(()) } + fn handle_stmt_connect_trace_as_string( + &mut self, + unfolded_lhs_ty: TraceAsString, + unfolded_rhs_ty: TraceAsString, + folded_lhs: Expr, + folded_rhs: Expr, + source_location: SourceLocation, + output_stmts: &mut Vec, + ) -> Result<(), SimplifyEnumsError> { + self.handle_stmt_connect( + unfolded_lhs_ty.inner_ty(), + unfolded_rhs_ty.inner_ty(), + ops::TraceAsStringAsInner::new(folded_lhs).to_expr(), + ops::TraceAsStringAsInner::new(folded_rhs).to_expr(), + source_location, + output_stmts, + ) + } fn handle_stmt_connect_bundle( &mut self, unfolded_lhs_ty: Bundle, @@ -509,6 +528,15 @@ impl State { source_location, output_stmts, ), + CanonicalType::TraceAsString(unfolded_lhs_ty) => self + .handle_stmt_connect_trace_as_string( + unfolded_lhs_ty, + TraceAsString::from_canonical(unfolded_rhs_ty), + Expr::from_canonical(folded_lhs), + Expr::from_canonical(folded_rhs), + source_location, + output_stmts, + ), CanonicalType::UInt(_) | CanonicalType::SInt(_) | CanonicalType::Bool(_) @@ -528,6 +556,8 @@ fn connect_port( rhs: Expr, source_location: SourceLocation, ) { + let lhs = Expr::unwrap_transparent_types(lhs); + let rhs = Expr::unwrap_transparent_types(rhs); if lhs.ty() == rhs.ty() { stmts.push( StmtConnect { @@ -573,6 +603,9 @@ fn connect_port( connect_port(stmts, lhs[index], rhs[index], source_location); } } + (CanonicalType::TraceAsString(_), CanonicalType::TraceAsString(_)) => { + unreachable!("handled by unwrap_transparent_types") + } (CanonicalType::Bundle(_), _) | (CanonicalType::Enum(_), _) | (CanonicalType::Array(_), _) @@ -584,7 +617,8 @@ fn connect_port( | (CanonicalType::SyncReset(_), _) | (CanonicalType::Reset(_), _) | (CanonicalType::PhantomConst(_), _) - | (CanonicalType::DynSimOnly(_), _) => unreachable!( + | (CanonicalType::DynSimOnly(_), _) + | (CanonicalType::TraceAsString(_), _) => unreachable!( "trying to connect memory ports:\n{:?}\n{:?}", lhs.ty(), rhs.ty(), @@ -772,6 +806,8 @@ impl Folder for State { | ExprEnum::SliceSInt(_) | ExprEnum::CastToBits(_) | ExprEnum::CastBitsTo(_) + | ExprEnum::TraceAsStringAsInner(_) + | ExprEnum::ToTraceAsString(_) | ExprEnum::ModuleIO(_) | ExprEnum::Instance(_) | ExprEnum::Wire(_) @@ -936,7 +972,8 @@ impl Folder for State { | CanonicalType::SyncReset(_) | CanonicalType::Reset(_) | CanonicalType::PhantomConst(_) - | CanonicalType::DynSimOnly(_) => canonical_type.default_fold(self), + | CanonicalType::DynSimOnly(_) + | CanonicalType::TraceAsString(_) => canonical_type.default_fold(self), } } diff --git a/crates/fayalite/src/module/transform/simplify_memories.rs b/crates/fayalite/src/module/transform/simplify_memories.rs index d741836..4a97353 100644 --- a/crates/fayalite/src/module/transform/simplify_memories.rs +++ b/crates/fayalite/src/module/transform/simplify_memories.rs @@ -90,7 +90,7 @@ impl MemSplit { } } fn new(element_type: CanonicalType) -> Self { - match element_type { + match element_type.unwrap_transparent_types() { CanonicalType::Bundle(bundle_ty) => MemSplit::Bundle { fields: bundle_ty .fields() @@ -195,6 +195,7 @@ impl MemSplit { | CanonicalType::SyncReset(_) | CanonicalType::Reset(_) => unreachable!("memory element type is a storable type"), CanonicalType::DynSimOnly(_) => todo!("memory containing sim-only values"), + CanonicalType::TraceAsString(_) => unreachable!("handled by unwrap_transparent_types"), } } } @@ -306,7 +307,9 @@ impl SplitMemState<'_, '_> { let outer_mem_name_path_len = self.mem_name_path.len(); match self.split { MemSplit::Bundle { fields } => { - let CanonicalType::Bundle(bundle_type) = self.element_type else { + let CanonicalType::Bundle(bundle_type) = + self.element_type.unwrap_transparent_types() + else { unreachable!(); }; for ((field, field_offset), split) in bundle_type @@ -321,7 +324,10 @@ impl SplitMemState<'_, '_> { let field_ty_bit_width = field.ty.bit_width(); self.split_state_stack.push_map( |e: Expr| { - Expr::field(Expr::::from_canonical(e), &field.name) + Expr::field( + Expr::::from_canonical(Expr::unwrap_transparent_types(e)), + &field.name, + ) }, |initial_value_element| { let Some(field_offset) = field_offset.only_bit_width() else { @@ -377,8 +383,8 @@ impl SplitMemState<'_, '_> { }; self.output_stmts.push( StmtConnect { - lhs: Expr::field(port_expr, name), - rhs: Expr::field(wire_expr, name), + lhs: Expr::unwrap_transparent_types(Expr::field(port_expr, name)), + rhs: Expr::unwrap_transparent_types(Expr::field(wire_expr, name)), source_location: port.source_location(), } .into(), @@ -389,7 +395,8 @@ impl SplitMemState<'_, '_> { self.output_mems.push(new_mem); } MemSplit::Array { elements } => { - let CanonicalType::Array(array_type) = self.element_type else { + let CanonicalType::Array(array_type) = self.element_type.unwrap_transparent_types() + else { unreachable!(); }; let element_type = array_type.element(); @@ -398,7 +405,7 @@ impl SplitMemState<'_, '_> { self.mem_name_path.truncate(outer_mem_name_path_len); write!(self.mem_name_path, "_{index}").unwrap(); self.split_state_stack.push_map( - |e| Expr::::from_canonical(e)[index], + |e| Expr::::from_canonical(Expr::unwrap_transparent_types(e))[index], |initial_value_element| { &initial_value_element[index * element_bit_width..][..element_bit_width] }, @@ -464,7 +471,7 @@ impl ModuleState { assert_eq!(memory_element_array_range_len % input_array_type.len(), 0); let chunk_size = memory_element_array_range_len / input_array_type.len(); for index in 0..input_array_type.len() { - let map = |e| Expr::::from_canonical(e)[index]; + let map = |e| Expr::::from_canonical(Expr::unwrap_transparent_types(e))[index]; let wire_rdata = wire_rdata.map(map); let wire_wdata = wire_wdata.map(map); let wire_wmask = wire_wmask.map(map); @@ -505,8 +512,8 @@ impl ModuleState { port_read: Expr| { output_stmts.push( StmtConnect { - lhs: wire_read, - rhs: port_read, + lhs: Expr::unwrap_transparent_types(wire_read), + rhs: Expr::unwrap_transparent_types(port_read), source_location, } .into(), @@ -517,8 +524,8 @@ impl ModuleState { port_write: Expr| { output_stmts.push( StmtConnect { - lhs: port_write, - rhs: wire_write, + lhs: Expr::unwrap_transparent_types(port_write), + rhs: Expr::unwrap_transparent_types(wire_write), source_location, } .into(), @@ -530,7 +537,8 @@ impl ModuleState { connect_read( output_stmts, wire_read, - Expr::::from_canonical(port_read).cast_bits_to(wire_read.ty()), + Expr::::from_canonical(Expr::unwrap_transparent_types(port_read)) + .cast_bits_to(wire_read.ty()), ); }; let connect_write_enum = @@ -544,7 +552,7 @@ impl ModuleState { ); }; loop { - match input_element_type { + match input_element_type.unwrap_transparent_types() { CanonicalType::Bundle(_) => { unreachable!("bundle types are always split") } @@ -625,6 +633,9 @@ impl ModuleState { | CanonicalType::SyncReset(_) | CanonicalType::Reset(_) => unreachable!("memory element type is a storable type"), CanonicalType::DynSimOnly(_) => todo!("memory containing sim-only values"), + CanonicalType::TraceAsString(_) => { + unreachable!("handled by unwrap_transparent_types") + } } break; } diff --git a/crates/fayalite/src/module/transform/visit.rs b/crates/fayalite/src/module/transform/visit.rs index 2869a49..7b4cd2a 100644 --- a/crates/fayalite/src/module/transform/visit.rs +++ b/crates/fayalite/src/module/transform/visit.rs @@ -14,7 +14,8 @@ use crate::{ Expr, ExprEnum, ValueType, ops, target::{ Target, TargetBase, TargetChild, TargetPathArrayElement, TargetPathBundleField, - TargetPathDynArrayElement, TargetPathElement, + TargetPathDynArrayElement, TargetPathElement, TargetPathToTraceAsString, + TargetPathTraceAsStringInner, }, }, formal::FormalKind, @@ -32,7 +33,7 @@ use crate::{ reset::{AsyncReset, Reset, ResetType, SyncReset}, sim::{ExternModuleSimulation, value::DynSimOnly}, source_location::SourceLocation, - ty::{CanonicalType, Type}, + ty::{CanonicalType, TraceAsString, Type}, vendor::xilinx::{ XdcCreateClockAnnotation, XdcIOStandardAnnotation, XdcLocationAnnotation, XilinxAnnotation, }, diff --git a/crates/fayalite/src/phantom_const.rs b/crates/fayalite/src/phantom_const.rs index 32e9d6b..ba85817 100644 --- a/crates/fayalite/src/phantom_const.rs +++ b/crates/fayalite/src/phantom_const.rs @@ -4,12 +4,12 @@ use crate::{ expr::{Expr, HdlPartialEqImpl, HdlPartialOrdImpl, ToExpr, ValueType}, int::Bool, - intern::{Intern, Interned, InternedCompare, LazyInterned, LazyInternedTrait, Memoize}, + intern::{Intern, Interned, InternedCompare, LazyInterned, Memoize}, sim::value::{SimValue, ToSimValue, ToSimValueWithType}, source_location::SourceLocation, ty::{ CanonicalType, OpaqueSimValueSlice, OpaqueSimValueWriter, OpaqueSimValueWritten, - StaticType, Type, TypeProperties, impl_match_variant_as_self, + SimValueDebug, StaticType, Type, TypeProperties, impl_match_variant_as_self, serde_impls::{SerdeCanonicalType, SerdePhantomConst}, }, }; @@ -240,11 +240,17 @@ impl PhantomConst { { Self::new_interned(value.intern_deref()) } - pub const fn new_lazy(v: &'static dyn LazyInternedTrait) -> Self { + pub const fn new_const>>() -> Self { Self { - value: LazyInterned::new_lazy(v), + value: LazyInterned::new_const::(), } } + pub const fn new_const_default() -> Self + where + Interned: Default, + { + Self::new_const::>() + } pub fn get(self) -> Interned { self.value.interned() } @@ -321,6 +327,15 @@ impl Type for PhantomConst { } } +impl SimValueDebug for PhantomConst { + fn sim_value_debug( + value: &::SimValue, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + fmt::Debug::fmt(value, f) + } +} + impl Default for PhantomConst where Interned: Default, @@ -334,9 +349,7 @@ impl StaticType for PhantomConst where Interned: Default, { - const TYPE: Self = PhantomConst { - value: LazyInterned::new_lazy(&Interned::::default), - }; + const TYPE: Self = Self::new_const_default(); const MASK_TYPE: Self::MaskType = (); const TYPE_PROPERTIES: TypeProperties = <()>::TYPE_PROPERTIES; const MASK_TYPE_PROPERTIES: TypeProperties = <()>::TYPE_PROPERTIES; diff --git a/crates/fayalite/src/prelude.rs b/crates/fayalite/src/prelude.rs index 4c5bfdf..42038ca 100644 --- a/crates/fayalite/src/prelude.rs +++ b/crates/fayalite/src/prelude.rs @@ -13,7 +13,7 @@ pub use crate::{ enum_::{Enum, HdlNone, HdlOption, HdlSome}, expr::{ CastBitsTo, CastTo, CastToBits, Expr, HdlPartialEq, HdlPartialOrd, MakeUninitExpr, - ReduceBits, ToExpr, ValueType, repeat, + ReduceBits, ToExpr, ToTraceAsString, ValueType, repeat, }, formal::{ MakeFormalExpr, all_const, all_seq, any_const, any_seq, formal_global_clock, formal_reset, @@ -38,7 +38,7 @@ pub use crate::{ }, source_location::SourceLocation, testing::{FormalMode, assert_formal}, - ty::{AsMask, CanonicalType, Type}, + ty::{AsMask, CanonicalType, TraceAsString, Type}, util::{ConstUsize, GenericConstUsize}, wire::Wire, }; diff --git a/crates/fayalite/src/reset.rs b/crates/fayalite/src/reset.rs index 13273ac..ddc3651 100644 --- a/crates/fayalite/src/reset.rs +++ b/crates/fayalite/src/reset.rs @@ -1,5 +1,6 @@ // SPDX-License-Identifier: LGPL-3.0-or-later // See Notices.txt for copyright information + use crate::{ clock::Clock, expr::{CastToImpl, Expr, ValueType}, @@ -8,11 +9,13 @@ use crate::{ source_location::SourceLocation, ty::{ CanonicalType, OpaqueSimValueSize, OpaqueSimValueSlice, OpaqueSimValueWriter, - OpaqueSimValueWritten, StaticType, Type, TypeProperties, impl_match_variant_as_self, + OpaqueSimValueWritten, SimValueDebug, StaticType, Type, TypeProperties, + impl_match_variant_as_self, }, util::ConstUsize, }; use bitvec::{bits, order::Lsb0}; +use std::fmt; mod sealed { pub trait ResetTypeSealed {} @@ -100,6 +103,15 @@ macro_rules! reset_type { } } + impl SimValueDebug for $name { + fn sim_value_debug( + value: &::SimValue, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + fmt::Debug::fmt(value, f) + } + } + impl $name { pub fn type_properties(self) -> TypeProperties { Self::TYPE_PROPERTIES diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs index a59a4c7..1247fd8 100644 --- a/crates/fayalite/src/sim.rs +++ b/crates/fayalite/src/sim.rs @@ -9,6 +9,7 @@ use crate::{ Flow, target::{ GetTarget, Target, TargetPathArrayElement, TargetPathBundleField, TargetPathElement, + TargetPathTraceAsStringInner, }, }, int::BoolOrIntType, @@ -38,9 +39,9 @@ use crate::{ }, ty::{ OpaqueSimValue, OpaqueSimValueSize, OpaqueSimValueSizeRange, OpaqueSimValueSlice, - OpaqueSimValueWriter, + OpaqueSimValueWriter, TraceAsString, }, - util::{BitSliceWriteWithBase, DebugAsDisplay, HashMap, HashSet}, + util::{BitSliceWriteWithBase, DebugAsDisplay, HashMap, HashSet, copy_le_bytes_to_bitslice}, }; use bitvec::{bits, order::Lsb0, slice::BitSlice, vec::BitVec, view::BitView}; use num_bigint::BigInt; @@ -432,6 +433,15 @@ impl_trace_decl! { ty: DynSimOnly, flow: Flow, }), + TraceAsString(TraceTraceAsString { + fn location(self) -> _ { + self.location + } + location: TraceLocation, + name: Interned, + ty: TraceAsString, + flow: Flow, + }), }), } @@ -543,6 +553,7 @@ pub trait TraceWriter: fmt::Debug + 'static { id: TraceScalarId, value: &DynSimOnlyValue, ) -> Result<(), Self::Error>; + fn set_signal_string(&mut self, id: TraceScalarId, value: &str) -> Result<(), Self::Error>; } pub struct DynTraceWriterDecls(Box); @@ -607,6 +618,7 @@ trait TraceWriterDynTrait: fmt::Debug + 'static { id: TraceScalarId, value: &DynSimOnlyValue, ) -> std::io::Result<()>; + fn set_signal_string_dyn(&mut self, id: TraceScalarId, value: &str) -> std::io::Result<()>; } impl TraceWriterDynTrait for T { @@ -680,6 +692,9 @@ impl TraceWriterDynTrait for T { ) -> std::io::Result<()> { Ok(TraceWriter::set_signal_sim_only_value(self, id, value).map_err(err_into_io)?) } + fn set_signal_string_dyn(&mut self, id: TraceScalarId, value: &str) -> std::io::Result<()> { + Ok(TraceWriter::set_signal_string(self, id, value).map_err(err_into_io)?) + } } pub struct DynTraceWriter(Box); @@ -758,6 +773,9 @@ impl TraceWriter for DynTraceWriter { ) -> Result<(), Self::Error> { self.0.set_signal_sim_only_value_dyn(id, value) } + fn set_signal_string(&mut self, id: TraceScalarId, value: &str) -> Result<(), Self::Error> { + self.0.set_signal_string_dyn(id, value) + } } #[derive(Debug)] @@ -828,6 +846,7 @@ where #[derive(Clone, PartialEq, Eq, Hash, Debug)] pub(crate) struct SimTrace { kind: K, + maybe_changed: bool, state: S, last_state: S, } @@ -848,12 +867,14 @@ impl SimTraceDebug for SimTrace { fn fmt(&self, id: TraceScalarId, f: &mut fmt::Formatter<'_>) -> fmt::Result { let Self { kind, + maybe_changed, state, last_state, } = self; f.debug_struct("SimTrace") .field("id", &id) .field("kind", kind) + .field("maybe_changed", maybe_changed) .field("state", state) .field("last_state", last_state) .finish() @@ -864,12 +885,14 @@ impl SimTraceDebug for SimTrace fn fmt(&self, id: TraceScalarId, f: &mut fmt::Formatter<'_>) -> fmt::Result { let Self { kind, + maybe_changed, state, last_state, } = self; f.debug_struct("SimTrace") .field("id", &id) .field("kind", kind) + .field("maybe_changed", maybe_changed) .field("state", state) .field("last_state", last_state) .finish() @@ -929,6 +952,10 @@ pub(crate) enum SimTraceKind { PhantomConst { ty: PhantomConst, }, + TraceAsString { + layout: compiler::CompiledTypeLayout, + range: TypeIndexRange, + }, } #[derive(PartialEq, Eq)] @@ -936,6 +963,7 @@ pub(crate) enum SimTraceState { Bits(BitVec), SimOnly(DynSimOnlyValue), PhantomConst, + OpaqueSimValue(OpaqueSimValue), } impl Clone for SimTraceState { @@ -944,6 +972,7 @@ impl Clone for SimTraceState { Self::Bits(v) => Self::Bits(v.clone()), Self::SimOnly(v) => Self::SimOnly(v.clone()), Self::PhantomConst => Self::PhantomConst, + Self::OpaqueSimValue(v) => Self::OpaqueSimValue(v.clone()), } } fn clone_from(&mut self, source: &Self) { @@ -951,6 +980,9 @@ impl Clone for SimTraceState { (SimTraceState::Bits(dest), SimTraceState::Bits(source)) => { dest.clone_from_bitslice(source); } + (SimTraceState::OpaqueSimValue(dest), SimTraceState::OpaqueSimValue(source)) => { + dest.clone_from(source); + } _ => *self = source.clone(), } } @@ -985,6 +1017,20 @@ impl SimTraceState { unreachable!() } } + fn unwrap_opaque_sim_value_ref(&self) -> &OpaqueSimValue { + if let SimTraceState::OpaqueSimValue(v) = self { + v + } else { + unreachable!() + } + } + fn unwrap_opaque_sim_value_mut(&mut self) -> &mut OpaqueSimValue { + if let SimTraceState::OpaqueSimValue(v) = self { + v + } else { + unreachable!() + } + } } impl fmt::Debug for SimTraceState { @@ -993,6 +1039,7 @@ impl fmt::Debug for SimTraceState { SimTraceState::Bits(v) => BitSliceWriteWithBase(v).fmt(f), SimTraceState::SimOnly(v) => v.fmt(f), SimTraceState::PhantomConst => f.debug_tuple("PhantomConst").finish(), + SimTraceState::OpaqueSimValue(v) => v.fmt(f), } } } @@ -1021,6 +1068,13 @@ impl SimTraceKind { } SimTraceKind::PhantomConst { .. } => SimTraceState::PhantomConst, SimTraceKind::SimOnly { index: _, ty } => SimTraceState::SimOnly(ty.default_value()), + SimTraceKind::TraceAsString { layout, range: _ } => { + let type_properties = layout.ty.type_properties(); + SimTraceState::OpaqueSimValue(OpaqueSimValue::from_bits_and_sim_only_values( + UIntValue::new_dyn(Arc::new(BitVec::repeat(false, type_properties.bit_width))), + Vec::with_capacity(type_properties.sim_only_values_len), + )) + } } } } @@ -1175,6 +1229,31 @@ impl SimulationModuleState { true } } + CompiledTypeLayoutBody::Transparent { .. } => { + let value = value.map_ty(|ty| match ty { + CanonicalType::UInt(_) + | CanonicalType::SInt(_) + | CanonicalType::Bool(_) + | CanonicalType::Array(_) + | CanonicalType::Enum(_) + | CanonicalType::Bundle(_) + | CanonicalType::AsyncReset(_) + | CanonicalType::SyncReset(_) + | CanonicalType::Reset(_) + | CanonicalType::Clock(_) + | CanonicalType::PhantomConst(_) + | CanonicalType::DynSimOnly(_) => unreachable!(), + CanonicalType::TraceAsString(ty) => ty, + }); + let sub_target = target + .join(TargetPathElement::from(TargetPathTraceAsStringInner {}).intern_sized()); + if self.parse_io(sub_target, value.inner()) { + self.uninitialized_ios.insert(target, vec![sub_target]); + true + } else { + false + } + } } } fn mark_target_as_initialized(&mut self, mut target: Target) { @@ -1225,7 +1304,10 @@ impl SimulationModuleState { Target::Base(_) => break, Target::Child(child) => { match *child.path_element() { - TargetPathElement::BundleField(_) | TargetPathElement::ArrayElement(_) => {} + TargetPathElement::BundleField(_) + | TargetPathElement::ArrayElement(_) + | TargetPathElement::TraceAsStringInner(_) + | TargetPathElement::ToTraceAsString(_) => {} TargetPathElement::DynArrayElement(_) => panic!( "simulator read/write expression must not have dynamic array indexes" ), @@ -1268,7 +1350,8 @@ impl SimulationModuleState { | CanonicalType::Reset(_) | CanonicalType::Clock(_) | CanonicalType::PhantomConst(_) - | CanonicalType::DynSimOnly(_) => unreachable!(), + | CanonicalType::DynSimOnly(_) + | CanonicalType::TraceAsString(_) => unreachable!(), CanonicalType::AsyncReset(_) => true, CanonicalType::SyncReset(_) => false, } @@ -1295,10 +1378,16 @@ impl SimulationModuleState { if !self.uninitialized_ios.is_empty() { match which_module { WhichModule::Main => { - panic!("can't read from an output before initializing all inputs"); + panic!( + "can't read from an output before initializing all inputs\nuninitialized_ios={:#?}", + SortedSetDebug(&self.uninitialized_ios), + ); } WhichModule::Extern { .. } => { - panic!("can't read from an input before initializing all outputs"); + panic!( + "can't read from an input before initializing all outputs\nuninitialized_ios={:#?}", + SortedSetDebug(&self.uninitialized_ios), + ); } } } @@ -1427,6 +1516,26 @@ impl SimulationExternModuleClockForPast { ); } } + CompiledTypeLayoutBody::Transparent { .. } => { + let map_ty_fn = |ty| match ty { + CanonicalType::UInt(_) + | CanonicalType::SInt(_) + | CanonicalType::Bool(_) + | CanonicalType::Array(_) + | CanonicalType::Enum(_) + | CanonicalType::Bundle(_) + | CanonicalType::AsyncReset(_) + | CanonicalType::SyncReset(_) + | CanonicalType::Reset(_) + | CanonicalType::Clock(_) + | CanonicalType::PhantomConst(_) + | CanonicalType::DynSimOnly(_) => unreachable!(), + CanonicalType::TraceAsString(ty) => ty, + }; + let current = current.map_ty(map_ty_fn); + let past = past.map_ty(map_ty_fn); + self.add_current_to_past_mapping(current.inner(), past.inner()); + } } } } @@ -1895,6 +2004,7 @@ struct SimulationImpl { ), >, waiting_sensitivity_sets_by_address: HashMap<*const SensitivitySet, Rc>, + trace_as_string_buf: String, } impl fmt::Debug for SimulationImpl { @@ -1984,6 +2094,7 @@ impl SimulationImpl { next_sensitivity_set_debug_id: _, waiting_sensitivity_sets_by_compiled_value, waiting_sensitivity_sets_by_address, + trace_as_string_buf: _, } = self; f.debug_struct("Simulation") .field("state", state) @@ -2072,10 +2183,12 @@ impl SimulationImpl { traces: SimTraces(Box::from_iter(compiled.traces.0.iter().map( |&SimTrace { kind, + maybe_changed: _, state: _, last_state: _, }| SimTrace { kind, + maybe_changed: true, state: kind.make_state(), last_state: kind.make_state(), }, @@ -2088,6 +2201,7 @@ impl SimulationImpl { next_sensitivity_set_debug_id: 0, waiting_sensitivity_sets_by_compiled_value: HashMap::default(), waiting_sensitivity_sets_by_address: HashMap::default(), + trace_as_string_buf: String::with_capacity(256), } } fn write_traces( @@ -2120,13 +2234,16 @@ impl SimulationImpl { id, &SimTrace { kind, + maybe_changed, ref state, ref last_state, }, ) in self.traces.0.iter().enumerate() { - if ONLY_IF_CHANGED && state == last_state { - continue; + if ONLY_IF_CHANGED { + if !(maybe_changed && state != last_state) { + continue; + } } let id = TraceScalarId(id); match kind { @@ -2165,6 +2282,15 @@ impl SimulationImpl { SimTraceKind::SimOnly { .. } => { trace_writer.set_signal_sim_only_value(id, state.unwrap_sim_only_ref())? } + SimTraceKind::TraceAsString { layout, .. } => { + self.trace_as_string_buf.clear(); + layout.ty.trace_fmt_append_to_string( + &mut self.trace_as_string_buf, + state.unwrap_opaque_sim_value_ref().as_slice(), + ); + trace_writer.set_signal_string(id, &self.trace_as_string_buf)?; + self.trace_as_string_buf.clear(); + } } } Ok(trace_writer) @@ -2187,10 +2313,48 @@ impl SimulationImpl { fn read_traces(&mut self) { for &mut SimTrace { kind, + ref mut maybe_changed, ref mut state, ref mut last_state, } in &mut self.traces.0 { + let new_maybe_changed = match kind { + SimTraceKind::BigUInt { index, ty: _ } + | SimTraceKind::BigSInt { index, ty: _ } + | SimTraceKind::BigBool { index } + | SimTraceKind::BigAsyncReset { index } + | SimTraceKind::BigSyncReset { index } + | SimTraceKind::BigClock { index } => self + .state + .big_slots + .state_index_fetch_maybe_modified_flag(index), + SimTraceKind::SmallUInt { index, ty: _ } + | SimTraceKind::SmallSInt { index, ty: _ } + | SimTraceKind::SmallBool { index } + | SimTraceKind::SmallAsyncReset { index } + | SimTraceKind::SmallSyncReset { index } + | SimTraceKind::SmallClock { index } + | SimTraceKind::EnumDiscriminant { index, ty: _ } => self + .state + .small_slots + .state_index_fetch_maybe_modified_flag(index), + SimTraceKind::SimOnly { index, ty: _ } => self + .state + .sim_only_slots + .state_index_fetch_maybe_modified_flag(index), + SimTraceKind::PhantomConst { ty: _ } => IS_INITIAL_STEP, + SimTraceKind::TraceAsString { layout: _, range } => self + .state + .type_index_range_fetch_maybe_modified_flags(range), + }; + if !new_maybe_changed && !IS_INITIAL_STEP { + if *maybe_changed { + last_state.clone_from(state); + } + *maybe_changed = false; + continue; + } + *maybe_changed = new_maybe_changed; if !IS_INITIAL_STEP { mem::swap(state, last_state); } @@ -2198,14 +2362,11 @@ impl SimulationImpl { SimTraceKind::BigUInt { index, ty: _ } | SimTraceKind::BigSInt { index, ty: _ } => { let state = state.unwrap_bits_mut(); let bigint = &self.state.big_slots[index]; - let mut bytes = bigint.to_signed_bytes_le(); - bytes.resize( - state.len().div_ceil(8), - if bigint.is_negative() { 0xFF } else { 0 }, + copy_le_bytes_to_bitslice( + state, + &bigint.to_signed_bytes_le(), + bigint.is_negative(), ); - let bitslice = BitSlice::::from_slice(&bytes); - let bitslice = &bitslice[..state.len()]; - state.clone_from_bitslice(bitslice); } SimTraceKind::BigBool { index } | SimTraceKind::BigAsyncReset { index } @@ -2238,11 +2399,26 @@ impl SimulationImpl { .unwrap_sim_only_mut() .clone_from(&self.state.sim_only_slots[index]); } + SimTraceKind::TraceAsString { layout, range } => { + let CompiledTypeLayoutBody::Transparent { inner } = layout.body else { + unreachable!() + }; + Self::read_opaque_no_settle( + &mut self.state, + CompiledValue { + layout: *inner, + range, + write: None, + }, + state.unwrap_opaque_sim_value_mut(), + ); + } } if IS_INITIAL_STEP { last_state.clone_from(state); } } + self.state.clear_all_maybe_modified_flags(); } #[track_caller] fn advance_time(this_ref: &Rc>, duration: SimDuration) { @@ -2769,6 +2945,7 @@ impl SimulationImpl { + Copy, read_write_sim_only_scalar: impl Fn(usize, &mut Opaque, &mut DynSimOnlyValue) + Copy, ) { + let compiled_value = compiled_value.unwrap_transparent_types(); match compiled_value.layout.body { CompiledTypeLayoutBody::Scalar => { let signed = match compiled_value.layout.ty { @@ -2784,6 +2961,7 @@ impl SimulationImpl { CanonicalType::Clock(_) => false, CanonicalType::PhantomConst(_) => unreachable!(), CanonicalType::DynSimOnly(_) => false, + CanonicalType::TraceAsString(_) => unreachable!(), }; let indexes = OpaqueSimValueSizeRange::from( start_index..start_index + compiled_value.layout.ty.size(), @@ -2860,14 +3038,17 @@ impl SimulationImpl { ); } } + CompiledTypeLayoutBody::Transparent { .. } => { + unreachable!("handled by unwrap_transparent_types") + } } } #[track_caller] - fn read_no_settle_helper( + fn read_opaque_no_settle( state: &mut interpreter::State, - io: Expr, compiled_value: CompiledValue, - ) -> SimValue { + opaque: &mut OpaqueSimValue, + ) { #[track_caller] fn read_write_sim_only_scalar( index: usize, @@ -2888,8 +3069,7 @@ impl SimulationImpl { }, ); } - let size = io.ty().size(); - let mut opaque = OpaqueSimValue::with_capacity(size); + let size = compiled_value.layout.ty.size(); opaque.rewrite_with(size, |mut writer| { SimulationImpl::read_write_sim_value_helper( state, @@ -2921,6 +3101,16 @@ impl SimulationImpl { ); writer.fill_cloned_from_slice(OpaqueSimValueSlice::empty()) }); + } + #[track_caller] + fn read_no_settle_helper( + state: &mut interpreter::State, + io: Expr, + compiled_value: CompiledValue, + ) -> SimValue { + let size = io.ty().size(); + let mut opaque = OpaqueSimValue::with_capacity(size); + Self::read_opaque_no_settle(state, compiled_value, &mut opaque); SimValue::from_opaque(io.ty(), opaque) } /// doesn't modify `opaque` diff --git a/crates/fayalite/src/sim/compiler.rs b/crates/fayalite/src/sim/compiler.rs index 07621c5..4d6d9bc 100644 --- a/crates/fayalite/src/sim/compiler.rs +++ b/crates/fayalite/src/sim/compiler.rs @@ -10,7 +10,7 @@ use crate::{ ExprEnum, Flow, ValueType, ops, target::{ GetTarget, Target, TargetBase, TargetPathArrayElement, TargetPathBundleField, - TargetPathElement, + TargetPathElement, TargetPathToTraceAsString, TargetPathTraceAsStringInner, }, }, int::BoolOrIntType, @@ -29,7 +29,8 @@ use crate::{ TraceBool, TraceBundle, TraceClock, TraceDecl, TraceEnumDiscriminant, TraceEnumWithFields, TraceFieldlessEnum, TraceInstance, TraceLocation, TraceMem, TraceMemPort, TraceMemoryId, TraceMemoryLocation, TraceModule, TraceModuleIO, TracePhantomConst, TraceReg, TraceSInt, - TraceScalarId, TraceScope, TraceSimOnly, TraceSyncReset, TraceUInt, TraceWire, + TraceScalarId, TraceScope, TraceSimOnly, TraceSyncReset, TraceTraceAsString, TraceUInt, + TraceWire, interpreter::{ self, Insn, InsnField, InsnFieldKind, InsnFieldType, InsnOrLabel, Insns, InsnsBuilding, InsnsBuildingDone, InsnsBuildingKind, Label, PrefixLinesWrapper, SmallUInt, @@ -42,7 +43,7 @@ use crate::{ }, }, }, - ty::{OpaqueSimValueSize, StaticType}, + ty::{OpaqueSimValueSize, StaticType, TraceAsString}, util::{HashMap, chain}, }; use bitvec::vec::BitVec; @@ -110,6 +111,9 @@ pub(crate) enum CompiledTypeLayoutBody { Bundle { fields: Interned<[CompiledBundleField]>, }, + Transparent { + inner: Interned>, + }, } impl CompiledTypeLayoutBody { @@ -128,6 +132,9 @@ impl CompiledTypeLayoutBody { .map(|field| field.with_prefixed_debug_names(prefix)) .collect(), }, + CompiledTypeLayoutBody::Transparent { inner } => CompiledTypeLayoutBody::Transparent { + inner: inner.with_prefixed_debug_names(prefix).intern_sized(), + }, } } fn with_anonymized_debug_info(self) -> Self { @@ -145,6 +152,9 @@ impl CompiledTypeLayoutBody { .map(|field| field.with_anonymized_debug_info()) .collect(), }, + CompiledTypeLayoutBody::Transparent { inner } => CompiledTypeLayoutBody::Transparent { + inner: inner.with_anonymized_debug_info().intern_sized(), + }, } } } @@ -179,7 +189,7 @@ impl CompiledTypeLayout { impl Memoize for MyMemoize { type Input = CanonicalType; type InputOwned = CanonicalType; - type Output = CompiledTypeLayout; + type Output = (TypeLayout, CompiledTypeLayoutBody); fn inner(self, input: &Self::Input) -> Self::Output { match input { @@ -197,11 +207,7 @@ impl CompiledTypeLayout { ty: *input, }; layout.big_slots = StatePartLayout::scalar(debug_data, ()); - CompiledTypeLayout { - ty: *input, - layout: layout.into(), - body: CompiledTypeLayoutBody::Scalar, - } + (layout.into(), CompiledTypeLayoutBody::Scalar) } CanonicalType::Array(array) => { let mut layout = TypeLayout::empty(); @@ -215,19 +221,16 @@ impl CompiledTypeLayout { if array.is_empty() { elements_non_empty.push(element.with_prefixed_debug_names("[]")); } - CompiledTypeLayout { - ty: *input, - layout: layout.into(), - body: CompiledTypeLayoutBody::Array { + ( + layout.into(), + CompiledTypeLayoutBody::Array { elements_non_empty: elements_non_empty.intern_deref(), }, - } + ) + } + CanonicalType::PhantomConst(_) => { + (TypeLayout::empty(), CompiledTypeLayoutBody::PhantomConst) } - CanonicalType::PhantomConst(_) => CompiledTypeLayout { - ty: *input, - layout: TypeLayout::empty(), - body: CompiledTypeLayoutBody::PhantomConst, - }, CanonicalType::Bundle(bundle) => { let mut layout = TypeLayout::empty(); let fields = bundle @@ -246,11 +249,7 @@ impl CompiledTypeLayout { }, ) .collect(); - CompiledTypeLayout { - ty: *input, - layout: layout.into(), - body: CompiledTypeLayoutBody::Bundle { fields }, - } + (layout.into(), CompiledTypeLayoutBody::Bundle { fields }) } CanonicalType::DynSimOnly(ty) => { let mut layout = TypeLayout::empty(); @@ -259,24 +258,30 @@ impl CompiledTypeLayout { ty: *input, }; layout.sim_only_slots = StatePartLayout::scalar(debug_data, *ty); - CompiledTypeLayout { - ty: *input, - layout: layout.into(), - body: CompiledTypeLayoutBody::Scalar, - } + (layout.into(), CompiledTypeLayoutBody::Scalar) + } + CanonicalType::TraceAsString(ty) => { + let inner = CompiledTypeLayout::get(ty.inner_ty()).intern_sized(); + (inner.layout, CompiledTypeLayoutBody::Transparent { inner }) } } } } - let CompiledTypeLayout { - ty: _, - layout, - body, - } = MyMemoize.get_owned(ty.canonical()); + let (layout, body) = MyMemoize.get_owned(ty.canonical()); Self { ty, layout, body } } } +impl CompiledTypeLayout { + #[must_use] + fn unwrap_transparent_types(mut self) -> Self { + while let CompiledTypeLayoutBody::Transparent { inner } = self.body { + self = *inner; + } + self + } +} + #[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)] pub(crate) struct CompiledValue { pub(crate) layout: CompiledTypeLayout, @@ -324,6 +329,29 @@ impl CompiledValue { } } +impl CompiledValue { + #[must_use] + pub(crate) fn unwrap_transparent_types(self) -> Self { + let Self { + layout, + range, + write, + } = self; + Self { + layout: layout.unwrap_transparent_types(), + range, + write: write.map(|(layout, range)| (layout.unwrap_transparent_types(), range)), + } + } + #[must_use] + pub(crate) fn wrap_in_trace_as_string(self, ty: TraceAsString) -> CompiledValue { + self.map(|layout, range| { + assert_eq!(layout.ty, ty.inner_ty()); + (CompiledTypeLayout::get(ty), range) + }) + } +} + pub(crate) struct DebugCompiledValueStateAsMap<'a> { pub(crate) compiled_value: CompiledValue, pub(crate) state_layout: &'a interpreter::parts::StateLayout, @@ -402,6 +430,17 @@ impl CompiledValue { } } +impl CompiledValue { + pub(crate) fn inner(self) -> CompiledValue { + self.map(|layout, range| { + let CompiledTypeLayoutBody::Transparent { inner } = layout.body else { + unreachable!(); + }; + (*inner, range) + }) + } +} + macro_rules! make_type_array_indexes { ( type_plural_fields = [$($type_plural_field:ident,)*]; @@ -618,6 +657,16 @@ impl CompiledExpr { } } +impl CompiledExpr { + #[must_use] + pub(crate) fn wrap_in_trace_as_string(self, ty: TraceAsString) -> CompiledExpr { + CompiledExpr { + static_part: self.static_part.wrap_in_trace_as_string(ty), + indexes: self.indexes, + } + } +} + impl CompiledExpr { fn field_by_index(self, field_index: usize) -> CompiledExpr { CompiledExpr { @@ -666,6 +715,15 @@ impl CompiledExpr { } } +impl CompiledExpr { + pub(crate) fn inner(self) -> CompiledExpr { + CompiledExpr { + static_part: self.static_part.inner(), + indexes: self.indexes, + } + } +} + macro_rules! make_assignment_graph { ( type_plural_fields = [$($type_plural_field:ident,)*]; @@ -1977,6 +2035,39 @@ macro_rules! impl_compiler { flow, } .into(), + CanonicalType::TraceAsString(ty) => { + let location = match target { + MakeTraceDeclTarget::Expr(target) => { + let compiled_value = self.compile_expr(instantiated_module, target); + let CompiledValue { layout, range, write: _ } = + self.compiled_expr_to_value(compiled_value, source_location).map_ty(Type::from_canonical); + TraceLocation::Scalar(self.new_sim_trace(SimTraceKind::TraceAsString { + layout, + range, + })) + } + MakeTraceDeclTarget::Memory { + id, + depth, + stride, + start, + ty: _, + } => TraceLocation::Memory(TraceMemoryLocation { + id, + depth, + stride, + start, + len: ty.type_properties().bit_width, + }), + }; + TraceTraceAsString { + location, + name, + ty, + flow, + } + .into() + } } } fn compiled_expr_to_value( @@ -2234,6 +2325,7 @@ impl Compiler { let id = TraceScalarId(self.traces.0.len()); self.traces.0.push(SimTrace { kind, + maybe_changed: true, state: (), last_state: (), }); @@ -2420,7 +2512,8 @@ impl Compiler { | CanonicalType::Reset(_) | CanonicalType::Clock(_) | CanonicalType::DynSimOnly(_) - | CanonicalType::PhantomConst(_) => { + | CanonicalType::PhantomConst(_) + | CanonicalType::TraceAsString(_) => { self.make_trace_scalar(instantiated_module, target, name, source_location) } } @@ -2590,6 +2683,12 @@ impl Compiler { parent.map_ty(Array::from_canonical).element(index) } TargetPathElement::DynArrayElement(_) => unreachable!(), + TargetPathElement::TraceAsStringInner(TargetPathTraceAsStringInner {}) => { + parent.map_ty(TraceAsString::from_canonical).inner() + } + TargetPathElement::ToTraceAsString(TargetPathToTraceAsString { ty }) => parent + .wrap_in_trace_as_string(ty) + .map_ty(|ty| ty.canonical()), } } }; @@ -2822,6 +2921,12 @@ impl Compiler { CanonicalType::PhantomConst(_) | CanonicalType::DynSimOnly(_) => { self.compile_cast_aggregate_to_bits(instantiated_module, []) } + CanonicalType::TraceAsString(_) => self.compile_cast_to_bits( + instantiated_module, + ops::CastToBits::new( + ops::TraceAsStringAsInner::new(Expr::from_canonical(expr.arg())).to_expr(), + ), + ), } } fn compile_cast_bits_to_or_uninit( @@ -2911,6 +3016,16 @@ impl Compiler { vec![] }); } + CanonicalType::TraceAsString(ty) => Expr::canonical( + ops::ToTraceAsString::new( + match arg { + Some(arg) => arg.cast_bits_to(ty.inner_ty()), + None => ty.inner_ty().uninit(), + }, + ty, + ) + .to_expr(), + ), }; let retval = self.compile_expr(instantiated_module, Expr::canonical(retval)); self.compiled_expr_to_value(retval, instantiated_module.leaf_module().source_location()) @@ -2962,6 +3077,7 @@ impl Compiler { CanonicalType::Clock(_) => false, CanonicalType::PhantomConst(_) => unreachable!(), CanonicalType::DynSimOnly(_) => unreachable!(), + CanonicalType::TraceAsString(_) => unreachable!(), }; let dest_signed = match expr.ty() { CanonicalType::UInt(_) => false, @@ -2976,6 +3092,7 @@ impl Compiler { CanonicalType::Clock(_) => false, CanonicalType::PhantomConst(_) => unreachable!(), CanonicalType::DynSimOnly(_) => unreachable!(), + CanonicalType::TraceAsString(_) => unreachable!(), }; self.simple_nary_big_expr(instantiated_module, expr.ty(), [arg], |dest, [src]| match ( src_signed, @@ -3721,6 +3838,14 @@ impl Compiler { ExprEnum::CastBitsTo(expr) => self .compile_cast_bits_to_or_uninit(instantiated_module, Some(expr.arg()), expr.ty()) .into(), + ExprEnum::ToTraceAsString(expr) => self + .compile_expr(instantiated_module, expr.inner()) + .wrap_in_trace_as_string(expr.ty()) + .map_ty(|ty| ty.canonical()), + ExprEnum::TraceAsStringAsInner(expr) => self + .compile_expr(instantiated_module, Expr::canonical(expr.arg())) + .map_ty(TraceAsString::from_canonical) + .inner(), ExprEnum::ModuleIO(expr) => self .compile_value(TargetInInstantiatedModule { instantiated_module, @@ -3868,6 +3993,21 @@ impl Compiler { CanonicalType::DynSimOnly(_) => { unreachable!("DynSimOnly mismatch"); } + CanonicalType::TraceAsString(_) => { + let lhs = Expr::::from_canonical(lhs); + let rhs = Expr::::from_canonical(rhs); + let lhs_expr = ops::TraceAsStringAsInner::new(lhs).to_expr(); + let rhs_expr = ops::TraceAsStringAsInner::new(rhs).to_expr(); + return self.compile_connect( + lhs_instantiated_module, + lhs_conditions, + lhs_expr, + rhs_instantiated_module, + rhs_conditions, + rhs_expr, + source_location, + ); + } } } let Some(target) = lhs.target() else { @@ -4087,6 +4227,15 @@ impl Compiler { let init = self.compiled_expr_to_value(init, reg.source_location()); (reg.clock_domain().rst, init) }); + + // next value defaults to current value + self.compile_simple_connect( + [].intern_slice(), + value.into(), + value, + reg.source_location(), + ); + self.compile_reg( clk, reset_and_init, @@ -4234,6 +4383,8 @@ impl Compiler { mut read: Option>, mut write: Option>, ) { + let data_layout = data_layout.unwrap_transparent_types(); + let mask_layout = mask_layout.unwrap_transparent_types(); match data_layout.body { CompiledTypeLayoutBody::Scalar => { let CompiledTypeLayoutBody::Scalar = mask_layout.body else { @@ -4252,6 +4403,7 @@ impl Compiler { CanonicalType::Clock(_) => false, CanonicalType::PhantomConst(_) => unreachable!(), CanonicalType::DynSimOnly(_) => false, + CanonicalType::TraceAsString(_) => unreachable!(), }; let width = data_layout.ty.bit_width(); if let Some(MemoryPortReadInsns { @@ -4474,6 +4626,9 @@ impl Compiler { start = start + field.ty.ty.bit_width(); } } + CompiledTypeLayoutBody::Transparent { .. } => { + unreachable!("handled by unwrap_transparent_types") + } } } fn compile_memory_port_rw( diff --git a/crates/fayalite/src/sim/interpreter.rs b/crates/fayalite/src/sim/interpreter.rs index 2b121b5..6b3eced 100644 --- a/crates/fayalite/src/sim/interpreter.rs +++ b/crates/fayalite/src/sim/interpreter.rs @@ -6,9 +6,9 @@ use crate::{ int::{BoolOrIntType, SInt, UInt}, intern::{Intern, Interned, Memoize}, sim::interpreter::parts::{ - StateLayout, StatePartIndex, StatePartKind, StatePartKindBigSlots, StatePartKindMemories, - StatePartKindSimOnlySlots, StatePartKindSmallSlots, StatePartLen, TypeIndexRange, - TypeLayout, get_state_part_kinds, + StateLayout, StatePartIndex, StatePartIndexRange, StatePartKind, StatePartKindBigSlots, + StatePartKindMemories, StatePartKindSimOnlySlots, StatePartKindSmallSlots, StatePartLen, + TypeIndexRange, TypeLayout, get_state_part_kinds, }, source_location::SourceLocation, util::{HashMap, HashSet}, @@ -17,12 +17,11 @@ use bitvec::slice::BitSlice; use num_bigint::BigInt; use num_traits::{One, Signed, ToPrimitive, Zero}; use std::{ - borrow::BorrowMut, convert::Infallible, fmt::{self, Write}, hash::Hash, marker::PhantomData, - ops::{ControlFlow, Deref, DerefMut, Index, IndexMut}, + ops::{ControlFlow, Deref, Index, IndexMut}, }; use vec_map::VecMap; @@ -915,6 +914,21 @@ impl StatePart { value: K::borrow_state(&mut self.value), } } + pub(crate) fn state_index_fetch_maybe_modified_flag( + &self, + part_index: StatePartIndex, + ) -> bool { + K::state_index_fetch_maybe_modified_flag(&self.value, part_index) + } + pub(crate) fn state_index_range_fetch_maybe_modified_flags( + &self, + part_index_range: StatePartIndexRange, + ) -> bool { + K::state_index_range_fetch_maybe_modified_flags(&self.value, part_index_range) + } + pub(crate) fn clear_all_maybe_modified_flags(&mut self) { + K::clear_all_maybe_modified_flags(&mut self.value) + } } #[derive(Clone, PartialEq, Eq, Hash, Debug)] @@ -922,56 +936,38 @@ pub(crate) struct BorrowedStatePart<'a, K: StatePartKind> { pub(crate) value: K::BorrowedState<'a>, } -impl< - 'a, - K: StatePartKind< - BorrowedState<'a>: DerefMut + BorrowMut<[T]>>, - >, - T, -> BorrowedStatePart<'a, K> -{ +impl BorrowedStatePart<'_, K> { pub(crate) fn get_disjoint_mut( &mut self, indexes: [StatePartIndex; N], - ) -> [&mut T; N] { - (*self.value) - .borrow_mut() - .get_disjoint_mut(indexes.map(|v| v.value as usize)) - .expect("indexes are disjoint") + ) -> [&mut K::StateElement; N] { + K::borrowed_state_get_disjoint_mut(&mut self.value, indexes) } } -impl>>, T> Index> - for StatePart -{ - type Output = T; +impl Index> for StatePart { + type Output = K::StateElement; fn index(&self, index: StatePartIndex) -> &Self::Output { - &self.value[index.value as usize] + K::state_index(&self.value, index) } } -impl>>, T> - IndexMut> for StatePart -{ +impl IndexMut> for StatePart { fn index_mut(&mut self, index: StatePartIndex) -> &mut Self::Output { - &mut self.value[index.value as usize] + K::state_index_mut(&mut self.value, index) } } -impl<'a, K: StatePartKind: Deref>>, T> - Index> for BorrowedStatePart<'a, K> -{ - type Output = T; +impl Index> for BorrowedStatePart<'_, K> { + type Output = K::StateElement; fn index(&self, index: StatePartIndex) -> &Self::Output { - &self.value[index.value as usize] + K::borrowed_state_index(&self.value, index) } } -impl<'a, K: StatePartKind: DerefMut>>, T> - IndexMut> for BorrowedStatePart<'a, K> -{ +impl IndexMut> for BorrowedStatePart<'_, K> { fn index_mut(&mut self, index: StatePartIndex) -> &mut Self::Output { - &mut self.value[index.value as usize] + K::borrowed_state_index_mut(&mut self.value, index) } } @@ -1028,6 +1024,15 @@ macro_rules! make_state { $($type_plural_field: self.$type_plural_field.borrow(),)* } } + pub(crate) fn type_index_range_fetch_maybe_modified_flags(&self, range: TypeIndexRange) -> bool { + $(self.$type_plural_field.state_index_range_fetch_maybe_modified_flags( + range.$type_plural_field, + ))||* + } + pub(crate) fn clear_all_maybe_modified_flags(&mut self) { + $(self.$state_plural_field.clear_all_maybe_modified_flags();)* + $(self.$type_plural_field.clear_all_maybe_modified_flags();)* + } } #[derive(Debug)] diff --git a/crates/fayalite/src/sim/interpreter/parts.rs b/crates/fayalite/src/sim/interpreter/parts.rs index 75427c9..0d98c06 100644 --- a/crates/fayalite/src/sim/interpreter/parts.rs +++ b/crates/fayalite/src/sim/interpreter/parts.rs @@ -236,6 +236,7 @@ pub(crate) trait StatePartKind: type LayoutData: Send + Sync + Eq + Hash + fmt::Debug + 'static + Copy; type State: fmt::Debug + 'static + Clone; type BorrowedState<'a>: 'a; + type StateElement; fn new_state(layout_data: &[Self::LayoutData]) -> Self::State; fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a>; fn part_debug_data( @@ -247,6 +248,35 @@ pub(crate) trait StatePartKind: index: StatePartIndex, f: &mut impl fmt::Write, ) -> fmt::Result; + fn state_index<'a>( + state: &'a Self::State, + part_index: StatePartIndex, + ) -> &'a Self::StateElement; + fn state_index_mut<'a>( + state: &'a mut Self::State, + part_index: StatePartIndex, + ) -> &'a mut Self::StateElement; + fn state_index_fetch_maybe_modified_flag( + state: &Self::State, + part_index: StatePartIndex, + ) -> bool; + fn state_index_range_fetch_maybe_modified_flags( + state: &Self::State, + part_index_range: StatePartIndexRange, + ) -> bool; + fn clear_all_maybe_modified_flags(state: &mut Self::State); + fn borrowed_state_index<'a, 'b>( + state: &'a Self::BorrowedState<'b>, + part_index: StatePartIndex, + ) -> &'a Self::StateElement; + fn borrowed_state_index_mut<'a, 'b>( + state: &'a mut Self::BorrowedState<'b>, + part_index: StatePartIndex, + ) -> &'a mut Self::StateElement; + fn borrowed_state_get_disjoint_mut<'a, 'b, const N: usize>( + state: &'a mut Self::BorrowedState<'b>, + part_indexes: [StatePartIndex; N], + ) -> [&'a mut Self::StateElement; N]; } macro_rules! make_state_part_kinds { @@ -272,6 +302,7 @@ impl StatePartKind for StatePartKindMemories { type LayoutData = MemoryData>; type State = Box<[MemoryData]>; type BorrowedState<'a> = &'a mut [MemoryData]; + type StateElement = MemoryData; fn new_state(layout_data: &[Self::LayoutData]) -> Self::State { layout_data .iter() @@ -297,19 +328,95 @@ impl StatePartKind for StatePartKindMemories { ) -> fmt::Result { write!(f, "{:#?}", &state.memories[index]) } + fn state_index<'a>( + state: &'a Self::State, + part_index: StatePartIndex, + ) -> &'a Self::StateElement { + &state[part_index.as_usize()] + } + fn state_index_mut<'a>( + state: &'a mut Self::State, + part_index: StatePartIndex, + ) -> &'a mut Self::StateElement { + &mut state[part_index.as_usize()] + } + fn state_index_fetch_maybe_modified_flag( + _state: &Self::State, + _part_index: StatePartIndex, + ) -> bool { + true + } + fn state_index_range_fetch_maybe_modified_flags( + _state: &Self::State, + part_index_range: StatePartIndexRange, + ) -> bool { + part_index_range.len.value > 0 + } + fn clear_all_maybe_modified_flags(_state: &mut Self::State) {} + fn borrowed_state_index<'a, 'b>( + state: &'a Self::BorrowedState<'b>, + part_index: StatePartIndex, + ) -> &'a Self::StateElement { + &state[part_index.as_usize()] + } + fn borrowed_state_index_mut<'a, 'b>( + state: &'a mut Self::BorrowedState<'b>, + part_index: StatePartIndex, + ) -> &'a mut Self::StateElement { + &mut state[part_index.as_usize()] + } + fn borrowed_state_get_disjoint_mut<'a, 'b, const N: usize>( + state: &'a mut Self::BorrowedState<'b>, + part_indexes: [StatePartIndex; N], + ) -> [&'a mut Self::StateElement; N] { + state + .get_disjoint_mut(part_indexes.map(StatePartIndex::as_usize)) + .expect("indexes are disjoint") + } +} + +#[derive(Copy, Clone, PartialEq, Eq, Hash, Default)] +pub(crate) struct StateAndModified { + pub(crate) state: T, + pub(crate) modified: M, +} + +impl, M: Deref, E: fmt::Debug> fmt::Debug + for StateAndModified +{ + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_list() + .entries(self.state.iter().zip(self.modified.iter().copied()).map( + |(state, modified)| { + fmt::from_fn(move |f| { + state.fmt(f)?; + if modified { + f.write_str(" (modified)")?; + } + Ok(()) + }) + }, + )) + .finish() + } } impl StatePartKind for StatePartKindSmallSlots { const NAME: &'static str = "SmallSlots"; type DebugData = SlotDebugData; type LayoutData = (); - type State = Box<[SmallUInt]>; - type BorrowedState<'a> = &'a mut [SmallUInt]; + type State = StateAndModified, Box<[bool]>>; + type BorrowedState<'a> = StateAndModified<&'a mut [Self::StateElement], &'a mut [bool]>; + type StateElement = SmallUInt; fn new_state(layout_data: &[Self::LayoutData]) -> Self::State { - vec![0; layout_data.len()].into_boxed_slice() + StateAndModified { + state: vec![0; layout_data.len()].into_boxed_slice(), + modified: vec![false; layout_data.len()].into_boxed_slice(), + } } fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a> { - state + let StateAndModified { state, modified } = state; + StateAndModified { state, modified } } fn part_debug_data( state_layout: &StateLayout, @@ -330,19 +437,80 @@ impl StatePartKind for StatePartKindSmallSlots { write!(f, "{value:#x} {}", value as SmallSInt)?; Ok(()) } + fn state_index<'a>( + state: &'a Self::State, + part_index: StatePartIndex, + ) -> &'a Self::StateElement { + &state.state[part_index.as_usize()] + } + fn state_index_mut<'a>( + state: &'a mut Self::State, + part_index: StatePartIndex, + ) -> &'a mut Self::StateElement { + state.modified[part_index.as_usize()] = true; + &mut state.state[part_index.as_usize()] + } + fn state_index_fetch_maybe_modified_flag( + state: &Self::State, + part_index: StatePartIndex, + ) -> bool { + state.modified[part_index.as_usize()] + } + fn state_index_range_fetch_maybe_modified_flags( + state: &Self::State, + part_index_range: StatePartIndexRange, + ) -> bool { + state.modified[part_index_range.start.as_usize()..] + [..part_index_range.len.as_index().as_usize()] + .contains(&true) + } + fn clear_all_maybe_modified_flags(state: &mut Self::State) { + state.modified.fill(false); + } + fn borrowed_state_index<'a, 'b>( + state: &'a Self::BorrowedState<'b>, + part_index: StatePartIndex, + ) -> &'a Self::StateElement { + &state.state[part_index.as_usize()] + } + fn borrowed_state_index_mut<'a, 'b>( + state: &'a mut Self::BorrowedState<'b>, + part_index: StatePartIndex, + ) -> &'a mut Self::StateElement { + state.modified[part_index.as_usize()] = true; + &mut state.state[part_index.as_usize()] + } + fn borrowed_state_get_disjoint_mut<'a, 'b, const N: usize>( + state: &'a mut Self::BorrowedState<'b>, + part_indexes: [StatePartIndex; N], + ) -> [&'a mut Self::StateElement; N] { + for part_index in part_indexes { + state.modified[part_index.as_usize()] = true; + } + state + .state + .get_disjoint_mut(part_indexes.map(StatePartIndex::as_usize)) + .expect("indexes are disjoint") + } } impl StatePartKind for StatePartKindBigSlots { const NAME: &'static str = "BigSlots"; type DebugData = SlotDebugData; type LayoutData = (); - type State = Box<[BigInt]>; - type BorrowedState<'a> = &'a mut [BigInt]; + type State = StateAndModified, Box<[bool]>>; + type BorrowedState<'a> = StateAndModified<&'a mut [Self::StateElement], &'a mut [bool]>; + type StateElement = BigInt; fn new_state(layout_data: &[Self::LayoutData]) -> Self::State { - layout_data.iter().map(|_| BigInt::default()).collect() + let state: Box<[_]> = layout_data.iter().map(|_| BigInt::default()).collect(); + StateAndModified { + modified: vec![false; state.len()].into_boxed_slice(), + state, + } } fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a> { - state + let StateAndModified { state, modified } = state; + StateAndModified { state, modified } } fn part_debug_data( state_layout: &StateLayout, @@ -361,19 +529,80 @@ impl StatePartKind for StatePartKindBigSlots { ) -> fmt::Result { write!(f, "{:#x}", state.big_slots[index]) } + fn state_index<'a>( + state: &'a Self::State, + part_index: StatePartIndex, + ) -> &'a Self::StateElement { + &state.state[part_index.as_usize()] + } + fn state_index_mut<'a>( + state: &'a mut Self::State, + part_index: StatePartIndex, + ) -> &'a mut Self::StateElement { + state.modified[part_index.as_usize()] = true; + &mut state.state[part_index.as_usize()] + } + fn state_index_fetch_maybe_modified_flag( + state: &Self::State, + part_index: StatePartIndex, + ) -> bool { + state.modified[part_index.as_usize()] + } + fn state_index_range_fetch_maybe_modified_flags( + state: &Self::State, + part_index_range: StatePartIndexRange, + ) -> bool { + state.modified[part_index_range.start.as_usize()..] + [..part_index_range.len.as_index().as_usize()] + .contains(&true) + } + fn clear_all_maybe_modified_flags(state: &mut Self::State) { + state.modified.fill(false); + } + fn borrowed_state_index<'a, 'b>( + state: &'a Self::BorrowedState<'b>, + part_index: StatePartIndex, + ) -> &'a Self::StateElement { + &state.state[part_index.as_usize()] + } + fn borrowed_state_index_mut<'a, 'b>( + state: &'a mut Self::BorrowedState<'b>, + part_index: StatePartIndex, + ) -> &'a mut Self::StateElement { + state.modified[part_index.as_usize()] = true; + &mut state.state[part_index.as_usize()] + } + fn borrowed_state_get_disjoint_mut<'a, 'b, const N: usize>( + state: &'a mut Self::BorrowedState<'b>, + part_indexes: [StatePartIndex; N], + ) -> [&'a mut Self::StateElement; N] { + for part_index in part_indexes { + state.modified[part_index.as_usize()] = true; + } + state + .state + .get_disjoint_mut(part_indexes.map(StatePartIndex::as_usize)) + .expect("indexes are disjoint") + } } impl StatePartKind for StatePartKindSimOnlySlots { const NAME: &'static str = "SimOnlySlots"; type DebugData = SlotDebugData; type LayoutData = DynSimOnly; - type State = Box<[DynSimOnlyValue]>; - type BorrowedState<'a> = &'a mut [DynSimOnlyValue]; + type State = StateAndModified, Box<[bool]>>; + type BorrowedState<'a> = StateAndModified<&'a mut [Self::StateElement], &'a mut [bool]>; + type StateElement = DynSimOnlyValue; fn new_state(layout_data: &[Self::LayoutData]) -> Self::State { - layout_data.iter().map(|ty| ty.default_value()).collect() + let state: Box<[_]> = layout_data.iter().map(|ty| ty.default_value()).collect(); + StateAndModified { + modified: vec![false; state.len()].into_boxed_slice(), + state, + } } fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a> { - state + let StateAndModified { state, modified } = state; + StateAndModified { state, modified } } fn part_debug_data( state_layout: &StateLayout, @@ -392,6 +621,61 @@ impl StatePartKind for StatePartKindSimOnlySlots { ) -> fmt::Result { write!(f, "{:?}", state.sim_only_slots[index]) } + fn state_index<'a>( + state: &'a Self::State, + part_index: StatePartIndex, + ) -> &'a Self::StateElement { + &state.state[part_index.as_usize()] + } + fn state_index_mut<'a>( + state: &'a mut Self::State, + part_index: StatePartIndex, + ) -> &'a mut Self::StateElement { + state.modified[part_index.as_usize()] = true; + &mut state.state[part_index.as_usize()] + } + fn state_index_fetch_maybe_modified_flag( + state: &Self::State, + part_index: StatePartIndex, + ) -> bool { + state.modified[part_index.as_usize()] + } + fn state_index_range_fetch_maybe_modified_flags( + state: &Self::State, + part_index_range: StatePartIndexRange, + ) -> bool { + state.modified[part_index_range.start.as_usize()..] + [..part_index_range.len.as_index().as_usize()] + .contains(&true) + } + fn clear_all_maybe_modified_flags(state: &mut Self::State) { + state.modified.fill(false); + } + fn borrowed_state_index<'a, 'b>( + state: &'a Self::BorrowedState<'b>, + part_index: StatePartIndex, + ) -> &'a Self::StateElement { + &state.state[part_index.as_usize()] + } + fn borrowed_state_index_mut<'a, 'b>( + state: &'a mut Self::BorrowedState<'b>, + part_index: StatePartIndex, + ) -> &'a mut Self::StateElement { + state.modified[part_index.as_usize()] = true; + &mut state.state[part_index.as_usize()] + } + fn borrowed_state_get_disjoint_mut<'a, 'b, const N: usize>( + state: &'a mut Self::BorrowedState<'b>, + part_indexes: [StatePartIndex; N], + ) -> [&'a mut Self::StateElement; N] { + for part_index in part_indexes { + state.modified[part_index.as_usize()] = true; + } + state + .state + .get_disjoint_mut(part_indexes.map(StatePartIndex::as_usize)) + .expect("indexes are disjoint") + } } #[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash)] diff --git a/crates/fayalite/src/sim/value.rs b/crates/fayalite/src/sim/value.rs index b6a4e4b..24bc1ef 100644 --- a/crates/fayalite/src/sim/value.rs +++ b/crates/fayalite/src/sim/value.rs @@ -15,23 +15,23 @@ use crate::{ source_location::SourceLocation, ty::{ CanonicalType, OpaqueSimValue, OpaqueSimValueSize, OpaqueSimValueSlice, - OpaqueSimValueWriter, StaticType, Type, TypeProperties, impl_match_variant_as_self, + OpaqueSimValueWriter, SimValueDebug, StaticType, Type, TypeProperties, + impl_match_variant_as_self, }, util::{ - ConstUsize, HashMap, + ConstUsize, alternating_cell::{AlternatingCell, AlternatingCellMethods}, + serde_by_id::{SerdeById, SerdeByIdProperties, SerdeByIdTable, SerdeByIdTrait}, }, }; use bitvec::{slice::BitSlice, vec::BitVec}; -use hashbrown::hash_map::Entry; use serde::{Deserialize, Deserializer, Serialize, Serializer, de::Error as _, ser::Error as _}; use std::{ borrow::{Borrow, BorrowMut, Cow}, - fmt::{self, Write}, - hash::{BuildHasher, Hash, Hasher, RandomState}, + fmt, num::NonZero, ops::{Deref, DerefMut, Index, IndexMut}, - sync::{Arc, Mutex}, + sync::Arc, }; pub(crate) mod sim_only_value_unsafe; @@ -551,113 +551,119 @@ impl_sim_value_cmp_as_bool!(AsyncReset); #[doc(hidden)] pub mod match_sim_value { - use crate::{ - sim::value::{SimValue, ToSimValue}, - ty::Type, - }; + use crate::{sim::value::SimValue, ty::Type}; + use std::ops::{Deref, DerefMut}; + + macro_rules! wrapper { + ( + $(pub struct $wrapper:ident<$T:ident>($inner:ty);)* + ) => { + $(#[doc(hidden)] + pub struct $wrapper<$T>($inner); + + impl<$T> $wrapper<$T> { + #[inline(always)] + pub fn new(value: $T) -> Self { + Self(<$inner>::new(value)) + } + } + + impl<$T> Deref for $wrapper<$T> { + type Target = $inner; + + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } + } + + impl<$T> DerefMut for $wrapper<$T> { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } + })* + }; + } + + wrapper! { + pub struct MatchSimValueHelperCheckSimValue(MatchSimValueHelperCheckMutSimValue); + pub struct MatchSimValueHelperCheckMutSimValue(MatchSimValueHelperCheckRefSimValue); + pub struct MatchSimValueHelperCheckRefSimValue(MatchSimValueHelperCheckRefRefSimValue); + pub struct MatchSimValueHelperCheckRefRefSimValue(MatchSimValueHelperCheckRefMutSimValue); + pub struct MatchSimValueHelperCheckRefMutSimValue(MatchSimValueHelperCheckMutRefSimValue); + pub struct MatchSimValueHelperCheckMutRefSimValue(MatchSimValueHelperCheckMutMutSimValue); + pub struct MatchSimValueHelperCheckMutMutSimValue(MatchSimValueHelperIdentity); + } + + impl MatchSimValueHelperCheckSimValue> { + #[inline(always)] + pub fn __fayalite_match_sim_value(&mut self) -> T::SimValue { + SimValue::into_value(self.take()) + } + } + + impl<'a, T: Type> MatchSimValueHelperCheckMutSimValue<&'a mut SimValue> { + #[inline(always)] + pub fn __fayalite_match_sim_value(&mut self) -> &'a mut T::SimValue { + self.take() + } + } + + impl<'a, T: Type> MatchSimValueHelperCheckRefSimValue<&'a SimValue> { + #[inline(always)] + pub fn __fayalite_match_sim_value(&mut self) -> &'a T::SimValue { + self.take() + } + } + + impl<'a, 'b, T: Type> MatchSimValueHelperCheckRefRefSimValue<&'a &'b SimValue> { + #[inline(always)] + pub fn __fayalite_match_sim_value(&mut self) -> &'b T::SimValue { + self.take() + } + } + + impl<'a, 'b, T: Type> MatchSimValueHelperCheckRefMutSimValue<&'a &'b mut SimValue> { + #[inline(always)] + pub fn __fayalite_match_sim_value(&mut self) -> &'a T::SimValue { + self.take() + } + } + + impl<'a, 'b, T: Type> MatchSimValueHelperCheckMutRefSimValue<&'a mut &'b SimValue> { + #[inline(always)] + pub fn __fayalite_match_sim_value(&mut self) -> &'b T::SimValue { + self.take() + } + } + + impl<'a, 'b, T: Type> MatchSimValueHelperCheckMutMutSimValue<&'a mut &'b mut SimValue> { + #[inline(always)] + pub fn __fayalite_match_sim_value(&mut self) -> &'a mut T::SimValue { + self.take() + } + } #[doc(hidden)] - pub struct MatchSimValueHelper(Option); + pub struct MatchSimValueHelperIdentity(Option); - impl MatchSimValueHelper { - pub fn new(v: T) -> Self { + impl MatchSimValueHelperIdentity { + fn new(v: T) -> Self { Self(Some(v)) } - } - - #[doc(hidden)] - pub trait MatchSimValue { - type MatchValue; - - /// use `self` so it comes first in the method resolution order - fn __fayalite_match_sim_value(self) -> Self::MatchValue - where - Self: Sized; - } - - impl MatchSimValue for MatchSimValueHelper> { - type MatchValue = T::SimValue; - - fn __fayalite_match_sim_value(self) -> Self::MatchValue { - SimValue::into_value(self.0.expect("should be Some")) + #[inline(always)] + fn take(&mut self) -> T { + self.0.take().expect("known to be Some") } - } - - impl<'a, T: Type> MatchSimValue for MatchSimValueHelper<&'a SimValue> { - type MatchValue = &'a T::SimValue; - - fn __fayalite_match_sim_value(self) -> Self::MatchValue { - SimValue::value(self.0.expect("should be Some")) - } - } - - impl<'a, T: Type> MatchSimValue for MatchSimValueHelper<&'a mut SimValue> { - type MatchValue = &'a mut T::SimValue; - - fn __fayalite_match_sim_value(self) -> Self::MatchValue { - SimValue::value_mut(self.0.expect("should be Some")) - } - } - - impl<'a, T> MatchSimValue for MatchSimValueHelper<&'_ &'a T> - where - MatchSimValueHelper<&'a T>: MatchSimValue, - { - type MatchValue = as MatchSimValue>::MatchValue; - - fn __fayalite_match_sim_value(self) -> Self::MatchValue { - MatchSimValue::__fayalite_match_sim_value(MatchSimValueHelper(self.0.map(|v| *v))) - } - } - - impl<'a, T> MatchSimValue for MatchSimValueHelper<&'_ mut &'a T> - where - MatchSimValueHelper<&'a T>: MatchSimValue, - { - type MatchValue = as MatchSimValue>::MatchValue; - - fn __fayalite_match_sim_value(self) -> Self::MatchValue { - MatchSimValue::__fayalite_match_sim_value(MatchSimValueHelper(self.0.map(|v| *v))) - } - } - - impl<'a, T> MatchSimValue for MatchSimValueHelper<&'a &'_ mut T> - where - MatchSimValueHelper<&'a T>: MatchSimValue, - { - type MatchValue = as MatchSimValue>::MatchValue; - - fn __fayalite_match_sim_value(self) -> Self::MatchValue { - MatchSimValue::__fayalite_match_sim_value(MatchSimValueHelper(self.0.map(|v| &**v))) - } - } - - impl<'a, T> MatchSimValue for MatchSimValueHelper<&'a mut &'_ mut T> - where - MatchSimValueHelper<&'a mut T>: MatchSimValue, - { - type MatchValue = as MatchSimValue>::MatchValue; - - fn __fayalite_match_sim_value(self) -> Self::MatchValue { - MatchSimValue::__fayalite_match_sim_value(MatchSimValueHelper(self.0.map(|v| &mut **v))) + #[inline(always)] + pub fn __fayalite_match_sim_value(&mut self) -> T { + self.take() } } #[doc(hidden)] - pub trait MatchSimValueFallback { - type MatchValue; - - /// use `&mut self` so it comes later in the method resolution order than MatchSimValue - fn __fayalite_match_sim_value(&mut self) -> Self::MatchValue; - } - - impl MatchSimValueFallback for MatchSimValueHelper { - type MatchValue = ::SimValue; - - fn __fayalite_match_sim_value(&mut self) -> Self::MatchValue { - SimValue::into_value(self.0.take().expect("should be Some").into_sim_value()) - } - } + pub type MatchSimValueHelper = MatchSimValueHelperCheckSimValue; } pub trait ToSimValue: ToSimValueWithType<::Type> + ValueType { @@ -1091,7 +1097,8 @@ impl ToSimValueWithType for bool { | CanonicalType::Enum(_) | CanonicalType::Bundle(_) | CanonicalType::PhantomConst(_) - | CanonicalType::DynSimOnly(_) => { + | CanonicalType::DynSimOnly(_) + | CanonicalType::TraceAsString(_) => { panic!("can't create SimValue from bool: expected value of type: {ty:?}"); } CanonicalType::Bool(_) @@ -1220,80 +1227,17 @@ macro_rules! impl_to_sim_value_for_int_value { impl_to_sim_value_for_int_value!(UIntValue, UInt, UIntType); impl_to_sim_value_for_int_value!(SIntValue, SInt, SIntType); -#[derive(Default)] -struct DynSimOnlySerdeTableRest { - from_serde: HashMap, - serde_id_random_state: RandomState, - buffer: String, -} - -impl DynSimOnlySerdeTableRest { - #[cold] - fn add_new(&mut self, ty: DynSimOnly) -> DynSimOnlySerdeId { - let mut try_number = 0u64; - let mut hasher = self.serde_id_random_state.build_hasher(); - // extract more bits of randomness from TypeId -- its Hash impl only hashes 64-bits - write!(self.buffer, "{:?}", ty.type_id()).expect("shouldn't ever fail"); - self.buffer.hash(&mut hasher); - loop { - let mut hasher = hasher.clone(); - try_number.hash(&mut hasher); - try_number += 1; - let retval = DynSimOnlySerdeId(std::array::from_fn(|i| { - let mut hasher = hasher.clone(); - i.hash(&mut hasher); - hasher.finish() as u32 - })); - match self.from_serde.entry(retval) { - Entry::Occupied(_) => continue, - Entry::Vacant(e) => { - e.insert(ty); - return retval; - } - } - } +impl SerdeByIdTrait for DynSimOnly { + fn serde_by_id_properties(&self) -> SerdeByIdProperties { + self.serde_by_id_properties_inner() } -} -#[derive(Default)] -struct DynSimOnlySerdeTable { - to_serde: HashMap, - rest: DynSimOnlySerdeTableRest, -} - -static DYN_SIM_ONLY_VALUE_TYPE_SERDE_TABLE: Mutex> = Mutex::new(None); - -#[derive(Copy, Clone, Eq, PartialEq, Hash, Debug, Serialize, Deserialize)] -#[serde(transparent)] -struct DynSimOnlySerdeId([u32; 4]); - -impl From for DynSimOnlySerdeId { - fn from(ty: DynSimOnly) -> Self { - let mut locked = DYN_SIM_ONLY_VALUE_TYPE_SERDE_TABLE - .lock() - .expect("shouldn't be poison"); - let DynSimOnlySerdeTable { to_serde, rest } = locked.get_or_insert_default(); - match to_serde.entry(ty) { - Entry::Occupied(occupied_entry) => *occupied_entry.get(), - Entry::Vacant(vacant_entry) => *vacant_entry.insert(rest.add_new(ty)), - } + fn static_table() -> &'static SerdeByIdTable { + static TABLE: SerdeByIdTable = SerdeByIdTable::new(); + &TABLE } -} -impl DynSimOnlySerdeId { - fn ty(self) -> Option { - let locked = DYN_SIM_ONLY_VALUE_TYPE_SERDE_TABLE - .lock() - .expect("shouldn't be poison"); - Some(*locked.as_ref()?.rest.from_serde.get(&self)?) - } -} - -#[derive(Clone, Eq, PartialEq, Hash, Debug, Serialize, Deserialize)] -struct DynSimOnlySerde<'a> { - random_id: DynSimOnlySerdeId, - #[serde(borrow)] - type_name: Cow<'a, str>, + const NAME: &'static str = "DynSimOnly"; } impl Serialize for DynSimOnly { @@ -1301,11 +1245,7 @@ impl Serialize for DynSimOnly { where S: Serializer, { - DynSimOnlySerde { - random_id: (*self).into(), - type_name: Cow::Borrowed(self.type_name()), - } - .serialize(serializer) + SerdeById { inner: *self }.serialize(serializer) } } @@ -1314,16 +1254,7 @@ impl<'de> Deserialize<'de> for DynSimOnly { where D: Deserializer<'de>, { - let deserialized = DynSimOnlySerde::deserialize(deserializer)?; - let retval = deserialized - .random_id - .ty() - .filter(|ty| ty.type_name() == deserialized.type_name); - retval.ok_or_else(|| { - D::Error::custom( - "doesn't match any DynSimOnly that was serialized this time this program was run", - ) - }) + Ok(SerdeById::deserialize(deserializer)?.inner) } } @@ -1394,6 +1325,15 @@ impl Type for DynSimOnly { } } +impl SimValueDebug for DynSimOnly { + fn sim_value_debug( + value: &::SimValue, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + fmt::Debug::fmt(value, f) + } +} + impl Type for SimOnly { type BaseType = DynSimOnly; type MaskType = Bool; @@ -1459,6 +1399,15 @@ impl Type for SimOnly { } } +impl SimValueDebug for SimOnly { + fn sim_value_debug( + value: &::SimValue, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + fmt::Debug::fmt(value, f) + } +} + impl StaticType for SimOnly { const TYPE: Self = Self::new(); diff --git a/crates/fayalite/src/sim/value/sim_only_value_unsafe.rs b/crates/fayalite/src/sim/value/sim_only_value_unsafe.rs index 2424c03..bcbcdc6 100644 --- a/crates/fayalite/src/sim/value/sim_only_value_unsafe.rs +++ b/crates/fayalite/src/sim/value/sim_only_value_unsafe.rs @@ -3,7 +3,10 @@ //! `unsafe` parts of [`DynSimOnlyValue`] -use crate::expr::{ValueType, value_category::ValueCategoryValue}; +use crate::{ + expr::{ValueType, value_category::ValueCategoryValue}, + util::serde_by_id::SerdeByIdProperties, +}; use serde::{Serialize, de::DeserializeOwned}; use std::{ any::{self, TypeId}, @@ -33,6 +36,7 @@ unsafe trait DynSimOnlyTrait: 'static + Send + Sync { &self, json_str: &str, ) -> serde_json::Result>; + fn serde_by_id_properties_inner(&self) -> SerdeByIdProperties; } /// Safety: `type_id_dyn` is implemented correctly @@ -55,6 +59,9 @@ unsafe impl DynSimOnlyTrait for SimOnly { ) -> serde_json::Result> { Ok(Rc::::new(serde_json::from_str(json_str)?)) } + fn serde_by_id_properties_inner(&self) -> SerdeByIdProperties { + SerdeByIdProperties::of::() + } } /// Safety: @@ -151,6 +158,9 @@ impl DynSimOnly { pub fn default_value(self) -> DynSimOnlyValue { DynSimOnlyValue(self.ty.default_value()) } + pub(super) fn serde_by_id_properties_inner(self) -> SerdeByIdProperties { + self.ty.serde_by_id_properties_inner() + } } impl PartialEq for DynSimOnly { diff --git a/crates/fayalite/src/sim/vcd.rs b/crates/fayalite/src/sim/vcd.rs index 6ba37b3..09e7d66 100644 --- a/crates/fayalite/src/sim/vcd.rs +++ b/crates/fayalite/src/sim/vcd.rs @@ -12,23 +12,41 @@ use crate::{ TraceEnumDiscriminant, TraceEnumWithFields, TraceFieldlessEnum, TraceInstance, TraceLocation, TraceMem, TraceMemPort, TraceMemoryId, TraceMemoryLocation, TraceModule, TraceModuleIO, TracePhantomConst, TraceReg, TraceSInt, TraceScalar, TraceScalarId, - TraceScope, TraceSimOnly, TraceSyncReset, TraceUInt, TraceWire, TraceWriter, - TraceWriterDecls, + TraceScope, TraceSimOnly, TraceSyncReset, TraceTraceAsString, TraceUInt, TraceWire, + TraceWriter, TraceWriterDecls, time::{SimDuration, SimInstant}, value::DynSimOnlyValue, }, + ty::{OpaqueSimValueSlice, TraceAsString}, util::HashMap, }; use bitvec::{order::Lsb0, slice::BitSlice}; use hashbrown::hash_map::Entry; +use sha2::{Digest, Sha256}; use std::{ + collections::BTreeMap, fmt::{self, Write as _}, io, mem, + num::NonZeroU64, }; -#[derive(Default)] +#[derive(Default, Clone)] +struct PathHash(Sha256); + +impl PathHash { + fn joined(mut self, segment: impl AsRef<[u8]>) -> Self { + let segment = segment.as_ref(); + self.0.update(u32::to_le_bytes( + segment.len().try_into().expect("path segment is too big"), + )); + self.0.update(segment); + self + } +} + struct Scope { last_inserted: HashMap, usize>, + path_hash: PathHash, } #[derive(Copy, Clone)] @@ -61,6 +79,13 @@ impl fmt::Display for VerilogIdentifier { } impl Scope { + fn new(path_hash: PathHash) -> Self { + Self { + last_inserted: Default::default(), + path_hash, + } + } + fn new_identifier(&mut self, unescaped_name: Interned) -> VerilogIdentifier { let next_disambiguator = match self.last_inserted.entry(unescaped_name) { Entry::Vacant(entry) => { @@ -163,6 +188,26 @@ impl fmt::Debug for VcdWriterDecls { } } +/// pass in scope to ensure it's not available in child scope +fn try_write_vcd_scope( + writer: &mut W, + scope_type: &str, + scope_name: Interned, + scope: Option<&mut Scope>, + f: impl FnOnce(&mut W, Option<&mut Scope>) -> io::Result, +) -> io::Result { + let Some(scope) = scope else { + return f(writer, None); + }; + write_vcd_scope( + writer, + scope_type, + scope_name, + scope, + move |writer, scope| f(writer, Some(scope)), + ) +} + /// pass in scope to ensure it's not available in child scope fn write_vcd_scope( writer: &mut W, @@ -171,12 +216,10 @@ fn write_vcd_scope( scope: &mut Scope, f: impl FnOnce(&mut W, &mut Scope) -> io::Result, ) -> io::Result { - writeln!( - writer, - "$scope {scope_type} {} $end", - scope.new_identifier(scope_name), - )?; - let retval = f(writer, &mut Scope::default())?; + let path_hash = scope.path_hash.clone().joined(scope_name); + let scope_name = scope.new_identifier(scope_name); + writeln!(writer, "$scope {scope_type} {scope_name} $end")?; + let retval = f(writer, &mut Scope::new(path_hash))?; writeln!(writer, "$upscope $end")?; Ok(retval) } @@ -216,6 +259,7 @@ trait_arg! { struct ArgModule<'a> { properties: &'a mut VcdWriterProperties, scope: &'a mut Scope, + instance_name: Option>, } impl<'a> ArgModule<'a> { @@ -223,6 +267,7 @@ impl<'a> ArgModule<'a> { ArgModule { properties: self.properties, scope: self.scope, + instance_name: self.instance_name, } } } @@ -246,7 +291,7 @@ struct ArgInType<'a> { sink_var_type: &'static str, duplex_var_type: &'static str, properties: &'a mut VcdWriterProperties, - scope: &'a mut Scope, + scope: Option<&'a mut Scope>, } impl<'a> ArgInType<'a> { @@ -256,7 +301,7 @@ impl<'a> ArgInType<'a> { sink_var_type: self.sink_var_type, duplex_var_type: self.duplex_var_type, properties: self.properties, - scope: self.scope, + scope: self.scope.as_deref_mut(), } } } @@ -287,23 +332,83 @@ impl WriteTrace for TraceScalar { Self::AsyncReset(v) => v.write_trace(writer, arg), Self::PhantomConst(v) => v.write_trace(writer, arg), Self::SimOnly(v) => v.write_trace(writer, arg), + Self::TraceAsString(v) => v.write_trace(writer, arg), } } } -fn write_vcd_id(writer: &mut W, mut id: usize) -> io::Result<()> { - let min_char = b'!'; - let max_char = b'~'; - let base = (max_char - min_char + 1) as usize; - loop { - let digit = (id % base) as u8 + min_char; - id /= base; - writer.write_all(&[digit])?; - if id == 0 { - break; +#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)] +#[repr(transparent)] +struct VcdId(NonZeroU64); + +impl VcdId { + const CHAR_RANGE: std::ops::RangeInclusive = b'!'..=b'~'; + const BASE: u8 = *Self::CHAR_RANGE.end() - *Self::CHAR_RANGE.start() + 1; + const LOW_HALF_CHARS: u32 = 5; + const LOW_HALF_MODULUS: u64 = (Self::BASE as u64).pow(Self::LOW_HALF_CHARS); + + const fn from_str(s: &str) -> Option { + if s.is_empty() { + return None; } + let mut retval = 0u64; + let mut bytes = s.as_bytes(); + while let [ref rest @ .., digit] = *bytes { + bytes = rest; + let Some(digit) = digit.checked_sub(*Self::CHAR_RANGE.start()) else { + return None; + }; + if digit >= Self::BASE { + return None; + } + let Some(v) = retval.checked_mul(Self::BASE as _) else { + return None; + }; + let Some(v) = v.checked_add(digit as _) else { + return None; + }; + retval = v; + } + let Some(retval) = NonZeroU64::new(retval) else { + return None; + }; + Some(Self(retval)) } - Ok(()) + #[must_use] + const fn write(self, out: &mut [u8]) -> usize { + let mut id = self.0.get(); + let mut len = 0; + loop { + let digit = (id % Self::BASE as u64) as u8 + *Self::CHAR_RANGE.start(); + id /= Self::BASE as u64; + if len < out.len() { + out[len] = digit; + } + len += 1; + if id == 0 { + break; + } + } + len + } + const MAX_ID_LEN: usize = Self(NonZeroU64::MAX).write(&mut []); +} + +/// check that VcdId properly round-trips +const _: () = { + let s = "RoundTrip"; + let Some(id) = VcdId::from_str(s) else { + unreachable!(); + }; + let mut buf = [0u8; VcdId::MAX_ID_LEN]; + let len = id.write(&mut buf); + assert!(crate::util::const_bytes_cmp(buf.split_at(len).0, s.as_bytes()).is_eq()); +}; + +fn write_vcd_id(writer: &mut W, id: VcdId) -> io::Result<()> { + let mut buf = [0u8; VcdId::MAX_ID_LEN]; + let len = id.write(&mut buf); + writer.write_all(&buf[..len]) } struct Escaped(T); @@ -346,12 +451,13 @@ impl fmt::Display for Escaped { fn write_vcd_var( properties: &mut VcdWriterProperties, + scope: Option<&mut Scope>, memory_element_part_body: MemoryElementPartBody, writer: &mut W, var_type: &str, size: usize, location: TraceLocation, - name: VerilogIdentifier, + name: Interned, ) -> io::Result<()> { let id = match location { TraceLocation::Scalar(id) => id.as_usize(), @@ -384,9 +490,21 @@ fn write_vcd_var( first_id + *element_index } }; - write!(writer, "$var {var_type} {size} ")?; - write_vcd_id(writer, id)?; - writeln!(writer, " {name} $end") + if let Some(scope) = scope { + let path_hash = scope.path_hash.clone().joined(name); + let name = scope.new_identifier(name); + let id = properties + .scalar_id_to_vcd_id_map + .builder_get_or_insert(id, &path_hash); + write!(writer, "$var {var_type} {size} ")?; + write_vcd_id(writer, id)?; + writeln!(writer, " {name} $end") + } else { + properties + .scalar_id_to_vcd_id_map + .builder_unused_scalar_id(id); + Ok(()) + } } impl WriteTrace for TraceUInt { @@ -414,12 +532,13 @@ impl WriteTrace for TraceUInt { } write_vcd_var( properties, + scope, MemoryElementPartBody::Scalar, writer, var_type, ty.width(), location, - scope.new_identifier(name), + name, ) } } @@ -494,12 +613,13 @@ impl WriteTrace for TraceEnumDiscriminant { } = self; write_vcd_var( properties, + scope, MemoryElementPartBody::EnumDiscriminant { ty }, writer, "string", 1, location, - scope.new_identifier(name), + name, ) } } @@ -569,12 +689,13 @@ impl WriteTrace for TracePhantomConst { } = self; write_vcd_var( properties, + scope, MemoryElementPartBody::Scalar, writer, "string", 1, location, - scope.new_identifier(name), + name, ) } } @@ -596,12 +717,41 @@ impl WriteTrace for TraceSimOnly { } = self; write_vcd_var( properties, + scope, MemoryElementPartBody::Scalar, writer, "string", 1, location, - scope.new_identifier(name), + name, + ) + } +} + +impl WriteTrace for TraceTraceAsString { + fn write_trace(self, writer: &mut W, mut arg: A) -> io::Result<()> { + let ArgInType { + source_var_type: _, + sink_var_type: _, + duplex_var_type: _, + properties, + scope, + } = arg.in_type(); + let Self { + location, + name, + ty, + flow: _, + } = self; + write_vcd_var( + properties, + scope, + MemoryElementPartBody::TraceAsString { ty }, + writer, + "string", + 1, + location, + name, ) } } @@ -625,14 +775,24 @@ impl WriteTrace for TraceScope { impl WriteTrace for TraceModule { fn write_trace(self, writer: &mut W, mut arg: A) -> io::Result<()> { - let ArgModule { properties, scope } = arg.module(); + let ArgModule { + properties, + scope, + instance_name, + } = arg.module(); let Self { name, children } = self; - write_vcd_scope(writer, "module", name, scope, |writer, scope| { - for child in children { - child.write_trace(writer, ArgModuleBody { properties, scope })?; - } - Ok(()) - }) + write_vcd_scope( + writer, + "module", + instance_name.unwrap_or(name), + scope, + |writer, scope| { + for child in children { + child.write_trace(writer, ArgModuleBody { properties, scope })?; + } + Ok(()) + }, + ) } } @@ -640,7 +800,7 @@ impl WriteTrace for TraceInstance { fn write_trace(self, writer: &mut W, mut arg: A) -> io::Result<()> { let ArgModuleBody { properties, scope } = arg.module_body(); let Self { - name: _, + name, instance_io, module, ty: _, @@ -652,10 +812,17 @@ impl WriteTrace for TraceInstance { sink_var_type: "wire", duplex_var_type: "wire", properties, - scope, + scope: None, }, )?; - module.write_trace(writer, ArgModule { properties, scope }) + module.write_trace( + writer, + ArgModule { + properties, + scope, + instance_name: Some(name), + }, + ) } } @@ -694,7 +861,7 @@ impl WriteTrace for TraceMem { sink_var_type: "reg", duplex_var_type: "reg", properties, - scope, + scope: Some(scope), }, ) }, @@ -726,7 +893,7 @@ impl WriteTrace for TraceMemPort { sink_var_type: "wire", duplex_var_type: "wire", properties, - scope, + scope: Some(scope), }, ) } @@ -747,7 +914,7 @@ impl WriteTrace for TraceWire { sink_var_type: "wire", duplex_var_type: "wire", properties, - scope, + scope: Some(scope), }, ) } @@ -768,7 +935,7 @@ impl WriteTrace for TraceReg { sink_var_type: "reg", duplex_var_type: "reg", properties, - scope, + scope: Some(scope), }, ) } @@ -790,7 +957,7 @@ impl WriteTrace for TraceModuleIO { sink_var_type: "wire", duplex_var_type: "wire", properties, - scope, + scope: Some(scope), }, ) } @@ -811,7 +978,7 @@ impl WriteTrace for TraceBundle { ty: _, flow: _, } = self; - write_vcd_scope(writer, "struct", name, scope, |writer, scope| { + try_write_vcd_scope(writer, "struct", name, scope, |writer, mut scope| { for field in fields { field.write_trace( writer, @@ -820,7 +987,7 @@ impl WriteTrace for TraceBundle { sink_var_type, duplex_var_type, properties, - scope, + scope: scope.as_deref_mut(), }, )?; } @@ -844,7 +1011,7 @@ impl WriteTrace for TraceArray { ty: _, flow: _, } = self; - write_vcd_scope(writer, "struct", name, scope, |writer, scope| { + try_write_vcd_scope(writer, "struct", name, scope, |writer, mut scope| { for element in elements { element.write_trace( writer, @@ -853,7 +1020,7 @@ impl WriteTrace for TraceArray { sink_var_type, duplex_var_type, properties, - scope, + scope: scope.as_deref_mut(), }, )?; } @@ -878,7 +1045,7 @@ impl WriteTrace for TraceEnumWithFields { ty: _, flow: _, } = self; - write_vcd_scope(writer, "struct", name, scope, |writer, scope| { + try_write_vcd_scope(writer, "struct", name, scope, |writer, mut scope| { discriminant.write_trace( writer, ArgInType { @@ -886,7 +1053,7 @@ impl WriteTrace for TraceEnumWithFields { sink_var_type, duplex_var_type, properties, - scope, + scope: scope.as_deref_mut(), }, )?; for field in non_empty_fields { @@ -897,7 +1064,7 @@ impl WriteTrace for TraceEnumWithFields { sink_var_type, duplex_var_type, properties, - scope, + scope: scope.as_deref_mut(), }, )?; } @@ -923,6 +1090,9 @@ impl TraceWriterDecls for VcdWriterDecls { writeln!(writer, "$timescale {} $end", vcd_timescale(timescale))?; let mut properties = VcdWriterProperties { next_scalar_id: trace_scalar_id_count, + scalar_id_to_vcd_id_map: ScalarIdToVcdIdMapOrBuilder::Builder( + ScalarIdToVcdIdMapBuilder::default(), + ), memory_properties: (0..trace_memory_id_count) .map(|_| MemoryProperties { element_parts: Vec::with_capacity(8), @@ -935,9 +1105,17 @@ impl TraceWriterDecls for VcdWriterDecls { &mut writer, ArgModule { properties: &mut properties, - scope: &mut Scope::default(), + scope: &mut Scope::new(PathHash::default()), + instance_name: None, }, )?; + let ScalarIdToVcdIdMapOrBuilder::Builder(scalar_id_to_vcd_id_map_builder) = + properties.scalar_id_to_vcd_id_map + else { + unreachable!(); + }; + properties.scalar_id_to_vcd_id_map = + ScalarIdToVcdIdMapOrBuilder::Built(scalar_id_to_vcd_id_map_builder.build()); writeln!(writer, "$enddefinitions $end")?; writeln!(writer, "$dumpvars")?; Ok(VcdWriter { @@ -945,6 +1123,7 @@ impl TraceWriterDecls for VcdWriterDecls { finished_init: false, timescale, properties, + trace_as_string_buf: String::with_capacity(256), }) } } @@ -952,6 +1131,7 @@ impl TraceWriterDecls for VcdWriterDecls { enum MemoryElementPartBody { Scalar, EnumDiscriminant { ty: Enum }, + TraceAsString { ty: TraceAsString }, } struct MemoryElementPart { @@ -967,8 +1147,100 @@ struct MemoryProperties { element_index: usize, } +struct ScalarIdToVcdIdMap { + scalar_id_to_vcd_id_map: Box<[Option]>, +} + +#[derive(Default)] +struct ScalarIdToVcdIdMapBuilder { + scalar_id_to_vcd_id_map: BTreeMap>, + lower_half_to_next_upper_half_map: HashMap, +} + +impl ScalarIdToVcdIdMapBuilder { + fn unused_scalar_id(&mut self, scalar_id: usize) { + self.scalar_id_to_vcd_id_map + .entry(scalar_id) + .or_insert(None); + } + /// `VcdId`s are based off of `path_hash` (and not `scalar_id`) since the hash doesn't change + /// when unrelated variables are added/removed, making the generated VCD more friendly for git diff. + fn get_or_insert(&mut self, scalar_id: usize, path_hash: &PathHash) -> VcdId { + *self + .scalar_id_to_vcd_id_map + .entry(scalar_id) + .or_insert(None) + .get_or_insert_with(|| { + let hash = u128::from_le_bytes( + *path_hash + .0 + .clone() + .finalize() + .first_chunk() + .expect("known to be bigger than u128"), + ); + let lower_half = (hash % VcdId::LOW_HALF_MODULUS as u128) as u64; + let next_upper_half = self + .lower_half_to_next_upper_half_map + .entry(lower_half) + .or_insert(if lower_half == 0 { 1 } else { 0 }); + let upper_half = *next_upper_half; + *next_upper_half += 1; + let Some(id) = upper_half + .checked_mul(VcdId::LOW_HALF_MODULUS) + .and_then(|v| v.checked_add(lower_half)) + else { + panic!("too many VcdIds"); + }; + VcdId(NonZeroU64::new(id).expect("known to not be zero")) + }) + } + fn build(self) -> ScalarIdToVcdIdMap { + ScalarIdToVcdIdMap { + scalar_id_to_vcd_id_map: self + .scalar_id_to_vcd_id_map + .into_iter() + .enumerate() + .map(|(index, (scalar_id, vcd_id))| { + if index != scalar_id { + panic!("missing scalar id {index}"); + } + vcd_id + }) + .collect(), + } + } +} + +enum ScalarIdToVcdIdMapOrBuilder { + Builder(ScalarIdToVcdIdMapBuilder), + Built(ScalarIdToVcdIdMap), +} + +impl ScalarIdToVcdIdMapOrBuilder { + fn built_scalar_id_to_vcd_id(&self, scalar_id: usize) -> Option { + let Self::Built(v) = self else { + panic!("ScalarIdToVcdIdMap isn't built yet"); + }; + v.scalar_id_to_vcd_id_map[scalar_id] + } + fn builder_get_or_insert(&mut self, scalar_id: usize, path_hash: &PathHash) -> VcdId { + let Self::Builder(v) = self else { + panic!("ScalarIdToVcdIdMap is already built"); + }; + v.get_or_insert(scalar_id, path_hash) + } + fn builder_unused_scalar_id(&mut self, scalar_id: usize) { + let Self::Builder(v) = self else { + panic!("ScalarIdToVcdIdMap is already built"); + }; + v.unused_scalar_id(scalar_id) + } +} + struct VcdWriterProperties { next_scalar_id: usize, + scalar_id_to_vcd_id_map: ScalarIdToVcdIdMapOrBuilder, memory_properties: Box<[MemoryProperties]>, } @@ -977,6 +1249,7 @@ pub struct VcdWriter { finished_init: bool, timescale: SimDuration, properties: VcdWriterProperties, + trace_as_string_buf: String, } impl VcdWriter { @@ -988,8 +1261,11 @@ impl VcdWriter { fn write_string_value_change( writer: &mut impl io::Write, value: impl fmt::Display, - id: usize, + id: Option, ) -> io::Result<()> { + let Some(id) = id else { + return Ok(()); + }; write!(writer, "s{} ", Escaped(value))?; write_vcd_id(writer, id)?; writer.write_all(b"\n") @@ -998,8 +1274,11 @@ fn write_string_value_change( fn write_bits_value_change( writer: &mut impl io::Write, value: &BitSlice, - id: usize, + id: Option, ) -> io::Result<()> { + let Some(id) = id else { + return Ok(()); + }; match value.len() { 0 => writer.write_all(b"s0 ")?, 1 => writer.write_all(if value[0] { b"1" } else { b"0" })?, @@ -1028,7 +1307,7 @@ fn write_enum_discriminant_value_change( writer: &mut impl io::Write, variant_index: usize, ty: Enum, - id: usize, + id: Option, ) -> io::Result<()> { write_string_value_change( writer, @@ -1063,7 +1342,9 @@ impl TraceWriter for VcdWriter { MemoryElementPartBody::Scalar => write_bits_value_change( &mut self.writer, &element_data[start..start + len], - first_id + element_index, + self.properties + .scalar_id_to_vcd_id_map + .built_scalar_id_to_vcd_id(first_id + element_index), )?, MemoryElementPartBody::EnumDiscriminant { ty } => { let mut variant_index = 0; @@ -1073,20 +1354,49 @@ impl TraceWriter for VcdWriter { &mut self.writer, variant_index, *ty, - first_id + element_index, + self.properties + .scalar_id_to_vcd_id_map + .built_scalar_id_to_vcd_id(first_id + element_index), )? } + MemoryElementPartBody::TraceAsString { ty } => { + self.trace_as_string_buf.clear(); + ty.trace_fmt_append_to_string( + &mut self.trace_as_string_buf, + OpaqueSimValueSlice::from_bitslice(&element_data[start..start + len]), + ); + write_string_value_change( + &mut self.writer, + &self.trace_as_string_buf, + self.properties + .scalar_id_to_vcd_id_map + .built_scalar_id_to_vcd_id(first_id + element_index), + )?; + self.trace_as_string_buf.clear(); + } } } Ok(()) } fn set_signal_uint(&mut self, id: TraceScalarId, value: &BitSlice) -> Result<(), Self::Error> { - write_bits_value_change(&mut self.writer, value, id.as_usize()) + write_bits_value_change( + &mut self.writer, + value, + self.properties + .scalar_id_to_vcd_id_map + .built_scalar_id_to_vcd_id(id.as_usize()), + ) } fn set_signal_sint(&mut self, id: TraceScalarId, value: &BitSlice) -> Result<(), Self::Error> { - write_bits_value_change(&mut self.writer, value, id.as_usize()) + write_bits_value_change( + &mut self.writer, + value, + self.properties + .scalar_id_to_vcd_id_map + .built_scalar_id_to_vcd_id(id.as_usize()), + ) } fn finish_init(&mut self) -> Result<(), Self::Error> { @@ -1118,7 +1428,14 @@ impl TraceWriter for VcdWriter { variant_index: usize, ty: Enum, ) -> Result<(), Self::Error> { - write_enum_discriminant_value_change(&mut self.writer, variant_index, ty, id.as_usize()) + write_enum_discriminant_value_change( + &mut self.writer, + variant_index, + ty, + self.properties + .scalar_id_to_vcd_id_map + .built_scalar_id_to_vcd_id(id.as_usize()), + ) } fn set_signal_phantom_const( @@ -1128,7 +1445,13 @@ impl TraceWriter for VcdWriter { ) -> Result<(), Self::Error> { // avoid multi-line strings because GTKWave can't display them properly: // https://github.com/gtkwave/gtkwave/issues/460 - write_string_value_change(&mut self.writer, format_args!("{ty:?}"), id.as_usize()) + write_string_value_change( + &mut self.writer, + format_args!("{ty:?}"), + self.properties + .scalar_id_to_vcd_id_map + .built_scalar_id_to_vcd_id(id.as_usize()), + ) } fn set_signal_sim_only_value( @@ -1136,7 +1459,23 @@ impl TraceWriter for VcdWriter { id: TraceScalarId, value: &DynSimOnlyValue, ) -> Result<(), Self::Error> { - write_string_value_change(&mut self.writer, format_args!("{value:?}"), id.as_usize()) + write_string_value_change( + &mut self.writer, + format_args!("{value:?}"), + self.properties + .scalar_id_to_vcd_id_map + .built_scalar_id_to_vcd_id(id.as_usize()), + ) + } + + fn set_signal_string(&mut self, id: TraceScalarId, value: &str) -> Result<(), Self::Error> { + write_string_value_change( + &mut self.writer, + value, + self.properties + .scalar_id_to_vcd_id_map + .built_scalar_id_to_vcd_id(id.as_usize()), + ) } } @@ -1147,6 +1486,7 @@ impl fmt::Debug for VcdWriter { finished_init, timescale, properties: _, + trace_as_string_buf: _, } = self; f.debug_struct("VcdWriter") .field("finished_init", finished_init) @@ -1161,7 +1501,7 @@ mod tests { #[test] fn test_scope() { - let mut scope = Scope::default(); + let mut scope = Scope::new(PathHash::default()); assert_eq!(&*scope.new_identifier("foo".intern()).unescaped_name, "foo"); assert_eq!( &*scope.new_identifier("foo_0".intern()).unescaped_name, diff --git a/crates/fayalite/src/ty.rs b/crates/fayalite/src/ty.rs index 76c0955..ab69532 100644 --- a/crates/fayalite/src/ty.rs +++ b/crates/fayalite/src/ty.rs @@ -3,22 +3,28 @@ use crate::{ array::Array, - bundle::Bundle, + bundle::{Bundle, BundleField, BundleType}, clock::Clock, - enum_::Enum, - expr::Expr, + enum_::{Enum, EnumType, EnumVariant}, + expr::{Expr, HdlPartialEqImpl, HdlPartialOrdImpl, ToExpr, ValueType, Valueless, ops}, int::{Bool, SInt, UInt, UIntValue}, - intern::{Intern, Interned}, + intern::{Intern, Interned, LazyInterned, Memoize, SupportsPtrEqWithTypeId}, + module::transform::visit::{Fold, Folder, Visit, Visitor}, phantom_const::PhantomConst, reset::{AsyncReset, Reset, SyncReset}, - sim::value::{DynSimOnly, DynSimOnlyValue, SimValue, ToSimValueWithType}, + sim::value::{DynSimOnly, DynSimOnlyValue, SimValue, ToSimValue, ToSimValueWithType}, source_location::SourceLocation, - util::{ConstUsize, slice_range, try_slice_range}, + util::{ + ConstUsize, iter_eq_by, + serde_by_id::{SerdeByIdProperties, SerdeByIdTable, SerdeByIdTrait}, + slice_range, try_slice_range, + }, }; use bitvec::{slice::BitSlice, vec::BitVec}; use serde::{Deserialize, Deserializer, Serialize, Serializer, de::DeserializeOwned}; use std::{ - fmt, + borrow::Cow, + fmt::{self, Write}, hash::Hash, iter::{FusedIterator, Sum}, marker::PhantomData, @@ -69,6 +75,7 @@ pub enum CanonicalType { Clock(Clock), PhantomConst(PhantomConst), DynSimOnly(DynSimOnly), + TraceAsString(TraceAsString), } impl fmt::Debug for CanonicalType { @@ -86,6 +93,7 @@ impl fmt::Debug for CanonicalType { Self::Clock(v) => v.fmt(f), Self::PhantomConst(v) => v.fmt(f), Self::DynSimOnly(v) => v.fmt(f), + Self::TraceAsString(v) => v.fmt(f), } } } @@ -123,6 +131,7 @@ impl CanonicalType { CanonicalType::Clock(v) => v.type_properties(), CanonicalType::PhantomConst(v) => v.type_properties(), CanonicalType::DynSimOnly(v) => v.type_properties(), + CanonicalType::TraceAsString(v) => v.type_properties(), } } pub fn is_passive(self) -> bool { @@ -217,11 +226,134 @@ impl CanonicalType { }; lhs.can_connect(rhs) } + CanonicalType::TraceAsString(lhs) => { + let CanonicalType::TraceAsString(rhs) = rhs else { + return false; + }; + lhs.can_connect(rhs) + } } } pub(crate) fn as_serde_unexpected_str(self) -> &'static str { serde_impls::SerdeCanonicalType::from(self).as_serde_unexpected_str() } + /// Unwrap transparent types until reaching a non-transparent type. Currently [`TraceAsString`] is the only transparent type. + /// + /// [`TraceAsString`]: struct@TraceAsString + pub fn unwrap_transparent_types(mut self) -> Self { + loop { + self = match self { + Self::UInt(_) + | Self::SInt(_) + | Self::Bool(_) + | Self::Array(_) + | Self::Enum(_) + | Self::Bundle(_) + | Self::AsyncReset(_) + | Self::SyncReset(_) + | Self::Reset(_) + | Self::Clock(_) + | Self::PhantomConst(_) + | Self::DynSimOnly(_) => return self, + Self::TraceAsString(ty) => ty.inner_ty(), + }; + } + } + pub fn is_layout_equivalent(self, other: Self) -> bool { + fn is_bit(ty: CanonicalType) -> bool { + match ty { + CanonicalType::UInt(ty) => ty.width() == 1, + CanonicalType::SInt(_) => false, // SInt<1> doesn't count since it would be -1/0 instead of 1/0 + CanonicalType::Bool(_) + | CanonicalType::AsyncReset(_) + | CanonicalType::SyncReset(_) + | CanonicalType::Reset(_) + | CanonicalType::Clock(_) => true, + CanonicalType::Array(_) + | CanonicalType::Enum(_) + | CanonicalType::Bundle(_) + | CanonicalType::PhantomConst(_) + | CanonicalType::DynSimOnly(_) => false, + CanonicalType::TraceAsString(_) => { + unreachable!("handled by unwrap_transparent_types") + } + } + } + #[derive(Copy, Clone, PartialEq, Eq, Hash)] + struct MyMemoize; + impl Memoize for MyMemoize { + type Input = (CanonicalType, CanonicalType); + type InputOwned = (CanonicalType, CanonicalType); + type Output = bool; + + fn inner(self, input: &Self::Input) -> Self::Output { + let (this, other) = *input; + let this = this.unwrap_transparent_types(); + let other = other.unwrap_transparent_types(); + let this_is_bit = is_bit(this); + let other_is_bit = is_bit(other); + if this_is_bit || other_is_bit { + return this_is_bit && other_is_bit; + } + let this_is_empty = this.size().is_empty(); + let other_is_empty = other.size().is_empty(); + if this_is_empty || other_is_empty { + return this_is_empty && other_is_empty; + } + match this { + CanonicalType::UInt(_) + | CanonicalType::SInt(_) + | CanonicalType::DynSimOnly(_) => this == other, + CanonicalType::Array(this) => { + let CanonicalType::Array(other) = other else { + return false; + }; + this.len() == other.len() + && this.element().is_layout_equivalent(other.element()) + } + CanonicalType::Enum(this) => { + let CanonicalType::Enum(other) = other else { + return false; + }; + iter_eq_by( + this.variants(), + other.variants(), + |EnumVariant { name, ty }, other_variant| { + name == other_variant.name + && ty.unwrap_or_else(|| ().canonical()).is_layout_equivalent( + other_variant.ty.unwrap_or_else(|| ().canonical()), + ) + }, + ) + } + CanonicalType::Bundle(this) => { + let CanonicalType::Bundle(other) = other else { + return false; + }; + iter_eq_by( + this.fields().iter().filter(|f| !f.ty.size().is_empty()), + other.fields().iter().filter(|f| !f.ty.size().is_empty()), + |&BundleField { name, flipped, ty }, other_field| { + name == other_field.name + && flipped == other_field.flipped + && ty.is_layout_equivalent(other_field.ty) + }, + ) + } + CanonicalType::Bool(_) + | CanonicalType::AsyncReset(_) + | CanonicalType::SyncReset(_) + | CanonicalType::Reset(_) + | CanonicalType::Clock(_) => unreachable!("handled by is_bit"), + CanonicalType::PhantomConst(_) => unreachable!("handled by is_empty"), + CanonicalType::TraceAsString(_) => { + unreachable!("handled by unwrap_transparent_types") + } + } + } + } + MyMemoize.get_owned((self, other)) + } } pub trait MatchVariantAndInactiveScope: Sized { @@ -328,6 +460,7 @@ impl_base_type!(Reset); impl_base_type!(Clock); impl_base_type!(PhantomConst); impl_base_type!(DynSimOnly); +impl_base_type!(TraceAsString); impl_base_type_serde!(Bool, "a Bool"); impl_base_type_serde!(Enum, "an Enum"); @@ -336,6 +469,7 @@ impl_base_type_serde!(AsyncReset, "an AsyncReset"); impl_base_type_serde!(SyncReset, "a SyncReset"); impl_base_type_serde!(Reset, "a Reset"); impl_base_type_serde!(Clock, "a Clock"); +impl_base_type_serde!(TraceAsString, "a TraceAsString"); impl sealed::BaseTypeSealed for CanonicalType {} @@ -367,7 +501,15 @@ impl TypeOrDefault for crate::__ { } pub trait Type: - Copy + Hash + Eq + fmt::Debug + Send + Sync + 'static + FillInDefaultedGenerics + Copy + + Hash + + Eq + + fmt::Debug + + Send + + Sync + + 'static + + FillInDefaultedGenerics + + SimValueDebug { type BaseType: BaseType; type MaskType: Type; @@ -402,6 +544,16 @@ pub trait Type: ) -> OpaqueSimValueWritten<'w>; } +pub trait SimValueDebug { + fn sim_value_debug(value: &::SimValue, f: &mut fmt::Formatter<'_>) -> fmt::Result + where + Self: Type; +} + +pub trait SimValueDisplay: Type { + fn sim_value_display(value: &Self::SimValue, f: &mut fmt::Formatter<'_>) -> fmt::Result; +} + pub trait BaseType: Type< BaseType = Self, @@ -455,6 +607,7 @@ impl Type for CanonicalType { CanonicalType::Clock(v) => v.mask_type().canonical(), CanonicalType::PhantomConst(v) => v.mask_type().canonical(), CanonicalType::DynSimOnly(v) => v.mask_type().canonical(), + CanonicalType::TraceAsString(v) => v.mask_type().canonical(), } } fn canonical(&self) -> CanonicalType { @@ -490,6 +643,15 @@ impl Type for CanonicalType { } } +impl SimValueDebug for CanonicalType { + fn sim_value_debug( + value: &::SimValue, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + fmt::Debug::fmt(value, f) + } +} + #[derive(Clone, PartialEq, Eq, Hash, Debug, Serialize, Deserialize, Default)] #[non_exhaustive] pub struct OpaqueSimValueSizeRange { @@ -730,13 +892,34 @@ impl Sum for OpaqueSimValueSize { } } -#[derive(Clone, PartialEq, Eq, Hash, Debug, Serialize, Deserialize)] +#[derive(PartialEq, Eq, Hash, Debug, Serialize, Deserialize)] pub struct OpaqueSimValue { bits: UIntValue, #[serde(skip_serializing_if = "Vec::is_empty", default)] sim_only_values: Vec, } +impl Clone for OpaqueSimValue { + fn clone(&self) -> Self { + Self { + bits: self.bits.clone(), + sim_only_values: self.sim_only_values.clone(), + } + } + fn clone_from(&mut self, source: &Self) { + let Self { + bits, + sim_only_values, + } = self; + if let Some(bits) = Arc::get_mut(bits.arc_bitvec_mut()) { + bits.clone_from(source.bits.bits()); + } else { + *bits = source.bits.clone(); + } + sim_only_values.clone_from(&source.sim_only_values); + } +} + impl OpaqueSimValue { pub fn empty() -> Self { Self { @@ -1116,3 +1299,786 @@ impl Index for AsMaskWithoutGenerics { Interned::into_inner(Intern::intern_sized(ty.mask_type())) } } + +trait TraceAsStringTrait: fmt::Debug + 'static + Send + Sync + SupportsPtrEqWithTypeId { + fn trace_fmt(&self, opaque: OpaqueSimValueSlice<'_>, f: &mut fmt::Formatter<'_>) + -> fmt::Result; + fn serde_by_id_properties(&self) -> SerdeByIdProperties> { + SerdeByIdProperties::of::() + } + fn can_substitute_type(&self, new_type: CanonicalType) -> bool; +} + +impl TraceAsStringTrait for T { + fn trace_fmt( + &self, + opaque: OpaqueSimValueSlice<'_>, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + fmt::Debug::fmt(&Type::sim_value_from_opaque(self, opaque), f) + } + fn can_substitute_type(&self, new_type: CanonicalType) -> bool { + self.canonical().is_layout_equivalent(new_type) + } +} + +impl crate::intern::InternedCompare for dyn TraceAsStringTrait { + type InternedCompareKey = crate::intern::PtrEqWithTypeId; + + fn interned_compare_key_ref(this: &Self) -> Self::InternedCompareKey { + this.get_ptr_eq_with_type_id() + } +} + +impl SerdeByIdTrait for Interned { + fn serde_by_id_properties(&self) -> SerdeByIdProperties { + TraceAsStringTrait::serde_by_id_properties(&**self) + } + + fn static_table() -> &'static SerdeByIdTable { + static TABLE: SerdeByIdTable> = SerdeByIdTable::new(); + &TABLE + } + + const NAME: &'static str = "dyn TraceAsStringTrait"; +} + +/// When running the fayalite simulator, outputs a single string signal containing a formatted version of the inner value (uses [`fmt::Debug`] by default). +/// This is a transparent type, meaning [`CanonicalType::unwrap_transparent_types`] will unwrap this type. +#[derive(Copy, Clone, PartialEq, Eq, Hash)] +pub struct TraceAsString { + inner_ty: LazyInterned, + trace_as_string: LazyInterned, +} + +#[expect(non_upper_case_globals)] +pub const TraceAsString: TraceAsStringWithoutGenerics = TraceAsStringWithoutGenerics; + +impl fmt::Debug for TraceAsString { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let Self { + inner_ty, + trace_as_string: _, + } = self; + f.debug_struct("TraceAsString") + .field("inner_ty", &inner_ty.interned()) + .finish_non_exhaustive() + } +} + +impl TraceAsString { + pub fn new(inner_ty: T) -> Self { + Self::new_interned(inner_ty.intern_sized()) + } + pub fn new_interned(inner_ty: Interned) -> Self { + Self { + inner_ty: LazyInterned::Interned(inner_ty), + trace_as_string: LazyInterned::Interned(Interned::cast_unchecked( + inner_ty, + |v| -> &dyn TraceAsStringTrait { v }, + )), + } + } + pub fn interned_inner_ty(self) -> Interned { + self.inner_ty.interned() + } + pub fn inner_ty(self) -> T { + *self.interned_inner_ty() + } + /// create a new `TraceAsString` but try to keep the old formatting method + pub fn with_new_inner_ty(self, inner_ty: Interned) -> TraceAsString { + if self + .trace_as_string + .can_substitute_type(inner_ty.canonical()) + { + TraceAsString { + inner_ty: LazyInterned::Interned(inner_ty), + trace_as_string: self.trace_as_string, + } + } else { + TraceAsString::new_interned(inner_ty) + } + } + pub fn canonical_trace_as_string(self) -> TraceAsString { + let Self { + inner_ty, + trace_as_string, + } = self; + TraceAsString { + inner_ty: LazyInterned::Interned(inner_ty.interned().canonical().intern_sized()), + trace_as_string, + } + } + pub fn from_canonical_trace_as_string(canonical: TraceAsString) -> Self { + let TraceAsString { + inner_ty, + trace_as_string, + } = canonical; + Self { + inner_ty: LazyInterned::Interned( + T::from_canonical(*inner_ty.interned()).intern_sized(), + ), + trace_as_string, + } + } + pub fn type_properties(self) -> TypeProperties { + self.interned_inner_ty().canonical().type_properties() + } + pub fn can_connect(self, rhs: TraceAsString) -> bool { + self.interned_inner_ty() + .canonical() + .can_connect(rhs.interned_inner_ty().canonical()) + } + pub fn trace_fmt( + self, + opaque: OpaqueSimValueSlice<'_>, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + self.trace_as_string.interned().trace_fmt(opaque, f) + } + pub fn trace_fmt_append_to_string(self, output: &mut String, opaque: OpaqueSimValueSlice<'_>) { + fn impl_fn( + trace_as_string: Interned, + output: &mut String, + opaque: OpaqueSimValueSlice<'_>, + ) { + let initial_len = output.len(); + if let Err(fmt::Error {}) = write!( + output, + "{}", + fmt::from_fn(|f| trace_as_string.trace_fmt(opaque, f)) + ) { + output.truncate(initial_len); + output.push_str(""); + } + } + impl_fn(self.trace_as_string.interned(), output, opaque) + } +} + +impl SimValueDebug for TraceAsString { + fn sim_value_debug( + value: &::SimValue, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + T::sim_value_debug(value.inner(), f) + } +} + +impl Type for TraceAsString { + type BaseType = TraceAsString; + type MaskType = T::MaskType; + type SimValue = TraceAsStringSimValue; + type MatchVariant = Expr; + type MatchActiveScope = (); + type MatchVariantAndInactiveScope = MatchVariantWithoutScope; + type MatchVariantsIter = std::iter::Once; + + fn match_variants( + this: Expr, + source_location: SourceLocation, + ) -> Self::MatchVariantsIter { + let _ = source_location; + std::iter::once(MatchVariantWithoutScope( + ops::TraceAsStringAsInner::new(this).to_expr(), + )) + } + + fn mask_type(&self) -> Self::MaskType { + self.inner_ty.mask_type() + } + + fn canonical(&self) -> CanonicalType { + CanonicalType::TraceAsString(self.canonical_trace_as_string()) + } + + fn from_canonical(canonical_type: CanonicalType) -> Self { + let CanonicalType::TraceAsString(canonical) = canonical_type else { + panic!("expected TraceAsString"); + }; + Self::from_canonical_trace_as_string(canonical) + } + + fn source_location() -> SourceLocation { + SourceLocation::builtin() + } + + fn sim_value_from_opaque(&self, opaque: OpaqueSimValueSlice<'_>) -> Self::SimValue { + TraceAsStringSimValue { + inner: SimValue::from_opaque(self.inner_ty(), opaque.to_owned()), + trace_as_string: self.trace_as_string.interned(), + } + } + + fn sim_value_clone_from_opaque( + &self, + value: &mut Self::SimValue, + opaque: OpaqueSimValueSlice<'_>, + ) { + self.inner_ty + .sim_value_clone_from_opaque(&mut value.inner, opaque); + } + + fn sim_value_to_opaque<'w>( + &self, + value: &Self::SimValue, + writer: OpaqueSimValueWriter<'w>, + ) -> OpaqueSimValueWritten<'w> { + self.inner_ty.sim_value_to_opaque(&value.inner, writer) + } +} + +impl TypeWithDeref for TraceAsString { + fn expr_deref(this: &Expr) -> &Self::MatchVariant { + Interned::into_inner( + ops::TraceAsStringAsInner::new(*this) + .to_expr() + .intern_sized(), + ) + } +} + +struct TraceAsStringStaticTypeHelper(PhantomData); + +impl Default for TraceAsStringStaticTypeHelper { + fn default() -> Self { + Self(PhantomData) + } +} + +impl From> for Interned { + fn from(_value: TraceAsStringStaticTypeHelper) -> Self { + Interned::cast_unchecked(T::TYPE.intern_sized(), |v| -> &dyn TraceAsStringTrait { v }) + } +} + +impl Default for TraceAsString { + fn default() -> Self { + Self::TYPE + } +} + +struct MakeType(Interned); + +impl From> for Interned { + fn from(value: MakeType) -> Self { + value.0 + } +} + +impl Default for MakeType { + fn default() -> Self { + Self(T::TYPE.intern_sized()) + } +} + +impl StaticType for TraceAsString { + const TYPE: Self = Self { + inner_ty: LazyInterned::new_const::>(), + trace_as_string: LazyInterned::new_const::>(), + }; + const MASK_TYPE: Self::MaskType = T::MASK_TYPE; + const TYPE_PROPERTIES: TypeProperties = T::TYPE_PROPERTIES; + const MASK_TYPE_PROPERTIES: TypeProperties = T::MASK_TYPE_PROPERTIES; +} + +#[doc(hidden)] +pub struct TraceAsStringWithoutGenerics; + +impl Index for TraceAsStringWithoutGenerics { + type Output = TraceAsString; + + fn index(&self, inner_ty: T) -> &Self::Output { + Interned::into_inner(TraceAsString::new(inner_ty).intern_sized()) + } +} + +#[derive(Clone)] +pub struct TraceAsStringSimValue { + inner: SimValue, + trace_as_string: Interned, +} + +#[derive(Serialize, Deserialize)] +#[serde(rename = "TraceAsStringSimValue")] +struct TraceAsStringSimValueSerde { + inner: T, + trace_as_string: crate::util::serde_by_id::SerdeById>, +} + +impl + Serialize> Serialize for TraceAsStringSimValue { + fn serialize(&self, serializer: S) -> Result + where + S: Serializer, + { + let Self { + inner, + trace_as_string, + } = self; + TraceAsStringSimValueSerde { + inner, + trace_as_string: crate::util::serde_by_id::SerdeById { + inner: *trace_as_string, + }, + } + .serialize(serializer) + } +} + +impl<'de, T: Type> + Deserialize<'de>> Deserialize<'de> + for TraceAsStringSimValue +{ + fn deserialize(deserializer: D) -> Result + where + D: Deserializer<'de>, + { + let TraceAsStringSimValueSerde { + inner, + trace_as_string: + crate::util::serde_by_id::SerdeById { + inner: trace_as_string, + }, + } = Deserialize::deserialize(deserializer)?; + Ok(Self { + inner, + trace_as_string, + }) + } +} + +impl TraceAsStringSimValue { + pub fn new_with_ty(inner: impl ToSimValueWithType, ty: TraceAsString) -> Self { + Self { + inner: inner.into_sim_value_with_type(ty.inner_ty()), + trace_as_string: ty.trace_as_string.interned(), + } + } + pub fn new(inner: impl ToSimValue) -> Self { + let inner = inner.into_sim_value(); + Self { + trace_as_string: TraceAsString::new(inner.ty()).trace_as_string.interned(), + inner, + } + } + pub fn into_inner(self) -> SimValue { + self.inner + } + pub fn inner(&self) -> &SimValue { + &self.inner + } + pub fn inner_mut(&mut self) -> &mut SimValue { + &mut self.inner + } +} + +impl ValueType for TraceAsStringSimValue { + type Type = TraceAsString; + type ValueCategory = crate::expr::value_category::ValueCategoryValue; + + fn ty(&self) -> Self::Type { + let inner_ty = self.inner.ty().intern_sized(); + if self + .trace_as_string + .can_substitute_type(inner_ty.canonical()) + { + TraceAsString { + inner_ty: LazyInterned::Interned(inner_ty), + trace_as_string: LazyInterned::Interned(self.trace_as_string), + } + } else { + TraceAsString::new_interned(inner_ty) + } + } +} + +impl ToExpr for TraceAsStringSimValue { + #[track_caller] + fn to_expr(&self) -> Expr { + let inner = self.inner.to_expr(); + let inner_canonical = Expr::canonical(inner); + let inner_ty = inner.ty().intern_sized(); + let ty = if self + .trace_as_string + .can_substitute_type(inner_canonical.ty()) + { + TraceAsString { + inner_ty: LazyInterned::Interned(inner_ty), + trace_as_string: LazyInterned::Interned(self.trace_as_string), + } + } else { + TraceAsString::new_interned(inner_ty) + }; + ops::ToTraceAsString::new(inner_canonical, ty).to_expr() + } +} + +impl ToSimValueWithType> for TraceAsStringSimValue { + fn to_sim_value_with_type(&self, ty: TraceAsString) -> SimValue> { + let inner = self.inner.to_sim_value_with_type(ty.inner_ty()); + SimValue::from_value( + ty, + TraceAsStringSimValue { + inner, + trace_as_string: ty.trace_as_string.interned(), + }, + ) + } + fn into_sim_value_with_type(self, ty: TraceAsString) -> SimValue> { + let inner = self.inner.into_sim_value_with_type(ty.inner_ty()); + SimValue::from_value( + ty, + TraceAsStringSimValue { + inner, + trace_as_string: ty.trace_as_string.interned(), + }, + ) + } +} + +impl ToSimValue for TraceAsStringSimValue { + fn to_sim_value(&self) -> SimValue { + SimValue::from_value(self.ty(), self.clone()) + } + fn into_sim_value(self) -> SimValue { + SimValue::from_value(self.ty(), self) + } +} + +impl fmt::Debug for TraceAsStringSimValue { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + fmt::Debug::fmt(&self.inner, f) + } +} + +impl> fmt::Display for TraceAsStringSimValue { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + fmt::Display::fmt(&self.inner, f) + } +} + +impl Ord for TraceAsStringSimValue +where + SimValue: Ord, +{ + fn cmp(&self, other: &Self) -> std::cmp::Ordering { + self.inner.cmp(&other.inner) + } +} + +impl PartialOrd> for TraceAsStringSimValue +where + SimValue: PartialOrd>, +{ + fn partial_cmp(&self, other: &TraceAsStringSimValue) -> Option { + self.inner.partial_cmp(&other.inner) + } +} + +impl Eq for TraceAsStringSimValue where SimValue: Eq {} + +impl Hash for TraceAsStringSimValue +where + SimValue: Hash, +{ + fn hash(&self, state: &mut H) { + self.inner.hash(state); + } +} + +impl Default for TraceAsStringSimValue +where + SimValue: Default, +{ + fn default() -> Self { + let inner = SimValue::default(); + Self { + trace_as_string: TraceAsString::new(inner.ty()).trace_as_string.interned(), + inner, + } + } +} + +impl PartialEq> for TraceAsStringSimValue +where + SimValue: PartialEq>, +{ + fn eq(&self, other: &TraceAsStringSimValue) -> bool { + self.inner == other.inner + } +} + +impl, State: ?Sized + Folder> Fold for TraceAsString { + fn fold(self, state: &mut State) -> Result { + state.fold_trace_as_string(self) + } + + fn default_fold(self, state: &mut State) -> Result { + Ok(self.with_new_inner_ty(self.interned_inner_ty().fold(state)?)) + } +} + +impl, State: ?Sized + Visitor> Visit for TraceAsString { + fn visit(&self, state: &mut State) -> Result<(), ::Error> { + state.visit_trace_as_string(self) + } + + fn default_visit(&self, state: &mut State) -> Result<(), ::Error> { + self.interned_inner_ty().visit(state) + } +} + +fn trace_as_string_cow_into_inner( + this: Cow<'_, SimValue>>, +) -> Cow<'_, SimValue> { + match this { + Cow::Borrowed(v) => Cow::Borrowed(&v.inner), + Cow::Owned(v) => Cow::Owned(SimValue::into_value(v).inner), + } +} + +fn trace_as_string_cow_into_inner_value( + this: Cow<'_, TraceAsStringSimValue>, +) -> Cow<'_, T::SimValue> { + match this { + Cow::Borrowed(v) => Cow::Borrowed(&v.inner), + Cow::Owned(v) => Cow::Owned(SimValue::into_value(v.inner)), + } +} + +impl, U: Type> HdlPartialEqImpl> for TraceAsString { + #[track_caller] + fn cmp_value_eq( + lhs: Self, + lhs_value: Cow<'_, Self::SimValue>, + rhs: TraceAsString, + rhs_value: Cow<'_, as Type>::SimValue>, + ) -> bool { + HdlPartialEqImpl::cmp_value_eq( + lhs.inner_ty(), + trace_as_string_cow_into_inner_value(lhs_value), + rhs.inner_ty(), + trace_as_string_cow_into_inner_value(rhs_value), + ) + } + + #[track_caller] + fn cmp_value_ne( + lhs: Self, + lhs_value: Cow<'_, Self::SimValue>, + rhs: TraceAsString, + rhs_value: Cow<'_, as Type>::SimValue>, + ) -> bool { + HdlPartialEqImpl::cmp_value_ne( + lhs.inner_ty(), + trace_as_string_cow_into_inner_value(lhs_value), + rhs.inner_ty(), + trace_as_string_cow_into_inner_value(rhs_value), + ) + } + + #[track_caller] + fn cmp_sim_value_eq( + lhs: Cow<'_, SimValue>, + rhs: Cow<'_, SimValue>>, + ) -> SimValue { + HdlPartialEqImpl::cmp_sim_value_eq( + trace_as_string_cow_into_inner(lhs), + trace_as_string_cow_into_inner(rhs), + ) + } + + #[track_caller] + fn cmp_sim_value_ne( + lhs: Cow<'_, SimValue>, + rhs: Cow<'_, SimValue>>, + ) -> SimValue { + HdlPartialEqImpl::cmp_sim_value_ne( + trace_as_string_cow_into_inner(lhs), + trace_as_string_cow_into_inner(rhs), + ) + } + + #[track_caller] + fn cmp_expr_eq(lhs: Expr, rhs: Expr>) -> Expr { + HdlPartialEqImpl::cmp_expr_eq(*lhs, *rhs) + } + + #[track_caller] + fn cmp_expr_ne(lhs: Expr, rhs: Expr>) -> Expr { + HdlPartialEqImpl::cmp_expr_ne(*lhs, *rhs) + } + + #[track_caller] + fn cmp_valueless_eq(lhs: Valueless, rhs: Valueless>) -> Valueless { + HdlPartialEqImpl::cmp_valueless_eq( + Valueless::new(lhs.ty().inner_ty()), + Valueless::new(rhs.ty().inner_ty()), + ) + } + + #[track_caller] + fn cmp_valueless_ne(lhs: Valueless, rhs: Valueless>) -> Valueless { + HdlPartialEqImpl::cmp_valueless_ne( + Valueless::new(lhs.ty().inner_ty()), + Valueless::new(rhs.ty().inner_ty()), + ) + } +} + +impl, U: Type> HdlPartialOrdImpl> for TraceAsString { + #[track_caller] + fn cmp_value_lt( + lhs: Self, + lhs_value: Cow<'_, Self::SimValue>, + rhs: TraceAsString, + rhs_value: Cow<'_, as Type>::SimValue>, + ) -> bool { + HdlPartialOrdImpl::cmp_value_lt( + lhs.inner_ty(), + trace_as_string_cow_into_inner_value(lhs_value), + rhs.inner_ty(), + trace_as_string_cow_into_inner_value(rhs_value), + ) + } + + #[track_caller] + fn cmp_value_le( + lhs: Self, + lhs_value: Cow<'_, Self::SimValue>, + rhs: TraceAsString, + rhs_value: Cow<'_, as Type>::SimValue>, + ) -> bool { + HdlPartialOrdImpl::cmp_value_le( + lhs.inner_ty(), + trace_as_string_cow_into_inner_value(lhs_value), + rhs.inner_ty(), + trace_as_string_cow_into_inner_value(rhs_value), + ) + } + + #[track_caller] + fn cmp_value_gt( + lhs: Self, + lhs_value: Cow<'_, Self::SimValue>, + rhs: TraceAsString, + rhs_value: Cow<'_, as Type>::SimValue>, + ) -> bool { + HdlPartialOrdImpl::cmp_value_gt( + lhs.inner_ty(), + trace_as_string_cow_into_inner_value(lhs_value), + rhs.inner_ty(), + trace_as_string_cow_into_inner_value(rhs_value), + ) + } + + #[track_caller] + fn cmp_value_ge( + lhs: Self, + lhs_value: Cow<'_, Self::SimValue>, + rhs: TraceAsString, + rhs_value: Cow<'_, as Type>::SimValue>, + ) -> bool { + HdlPartialOrdImpl::cmp_value_ge( + lhs.inner_ty(), + trace_as_string_cow_into_inner_value(lhs_value), + rhs.inner_ty(), + trace_as_string_cow_into_inner_value(rhs_value), + ) + } + + #[track_caller] + fn cmp_sim_value_lt( + lhs: Cow<'_, SimValue>, + rhs: Cow<'_, SimValue>>, + ) -> SimValue { + HdlPartialOrdImpl::cmp_sim_value_lt( + trace_as_string_cow_into_inner(lhs), + trace_as_string_cow_into_inner(rhs), + ) + } + + #[track_caller] + fn cmp_sim_value_le( + lhs: Cow<'_, SimValue>, + rhs: Cow<'_, SimValue>>, + ) -> SimValue { + HdlPartialOrdImpl::cmp_sim_value_le( + trace_as_string_cow_into_inner(lhs), + trace_as_string_cow_into_inner(rhs), + ) + } + + #[track_caller] + fn cmp_sim_value_gt( + lhs: Cow<'_, SimValue>, + rhs: Cow<'_, SimValue>>, + ) -> SimValue { + HdlPartialOrdImpl::cmp_sim_value_gt( + trace_as_string_cow_into_inner(lhs), + trace_as_string_cow_into_inner(rhs), + ) + } + + #[track_caller] + fn cmp_sim_value_ge( + lhs: Cow<'_, SimValue>, + rhs: Cow<'_, SimValue>>, + ) -> SimValue { + HdlPartialOrdImpl::cmp_sim_value_ge( + trace_as_string_cow_into_inner(lhs), + trace_as_string_cow_into_inner(rhs), + ) + } + + #[track_caller] + fn cmp_expr_lt(lhs: Expr, rhs: Expr>) -> Expr { + HdlPartialOrdImpl::cmp_expr_lt(*lhs, *rhs) + } + + #[track_caller] + fn cmp_expr_le(lhs: Expr, rhs: Expr>) -> Expr { + HdlPartialOrdImpl::cmp_expr_le(*lhs, *rhs) + } + + #[track_caller] + fn cmp_expr_gt(lhs: Expr, rhs: Expr>) -> Expr { + HdlPartialOrdImpl::cmp_expr_gt(*lhs, *rhs) + } + + #[track_caller] + fn cmp_expr_ge(lhs: Expr, rhs: Expr>) -> Expr { + HdlPartialOrdImpl::cmp_expr_ge(*lhs, *rhs) + } + + #[track_caller] + fn cmp_valueless_lt(lhs: Valueless, rhs: Valueless>) -> Valueless { + HdlPartialOrdImpl::cmp_valueless_lt( + Valueless::new(lhs.ty().inner_ty()), + Valueless::new(rhs.ty().inner_ty()), + ) + } + + #[track_caller] + fn cmp_valueless_le(lhs: Valueless, rhs: Valueless>) -> Valueless { + HdlPartialOrdImpl::cmp_valueless_le( + Valueless::new(lhs.ty().inner_ty()), + Valueless::new(rhs.ty().inner_ty()), + ) + } + + #[track_caller] + fn cmp_valueless_gt(lhs: Valueless, rhs: Valueless>) -> Valueless { + HdlPartialOrdImpl::cmp_valueless_gt( + Valueless::new(lhs.ty().inner_ty()), + Valueless::new(rhs.ty().inner_ty()), + ) + } + + #[track_caller] + fn cmp_valueless_ge(lhs: Valueless, rhs: Valueless>) -> Valueless { + HdlPartialOrdImpl::cmp_valueless_ge( + Valueless::new(lhs.ty().inner_ty()), + Valueless::new(rhs.ty().inner_ty()), + ) + } +} diff --git a/crates/fayalite/src/ty/serde_impls.rs b/crates/fayalite/src/ty/serde_impls.rs index af324f9..d5b5551 100644 --- a/crates/fayalite/src/ty/serde_impls.rs +++ b/crates/fayalite/src/ty/serde_impls.rs @@ -12,7 +12,8 @@ use crate::{ prelude::PhantomConst, reset::{AsyncReset, Reset, SyncReset}, sim::value::DynSimOnly, - ty::{BaseType, CanonicalType}, + ty::{BaseType, CanonicalType, TraceAsString, TraceAsStringTrait}, + util::serde_by_id::SerdeById, }; use serde::{Deserialize, Deserializer, Serialize, Serializer}; @@ -38,6 +39,7 @@ impl<'de, T: ?Sized + PhantomConstValue> Deserialize<'de> for SerdePhantomConst< #[derive(Serialize, Deserialize)] #[serde(rename = "CanonicalType")] +#[expect(private_interfaces)] pub(crate) enum SerdeCanonicalType< ArrayElement = CanonicalType, ThePhantomConst = SerdePhantomConst>, @@ -65,6 +67,10 @@ pub(crate) enum SerdeCanonicalType< Clock, PhantomConst(ThePhantomConst), DynSimOnly(DynSimOnly), + TraceAsString { + inner_ty: Interned, + trace_as_string: SerdeById>, + }, } impl SerdeCanonicalType { @@ -82,6 +88,7 @@ impl SerdeCanonicalType "a Clock", Self::PhantomConst(_) => "a PhantomConst", Self::DynSimOnly(_) => "a SimOnlyValue", + Self::TraceAsString { .. } => "a TraceAsString", } } } @@ -109,6 +116,15 @@ impl From for SerdeCanonicalType { CanonicalType::Clock(Clock {}) => Self::Clock, CanonicalType::PhantomConst(ty) => Self::PhantomConst(SerdePhantomConst(ty.get())), CanonicalType::DynSimOnly(ty) => Self::DynSimOnly(ty), + CanonicalType::TraceAsString(TraceAsString { + inner_ty, + trace_as_string, + }) => Self::TraceAsString { + inner_ty: inner_ty.interned(), + trace_as_string: SerdeById { + inner: trace_as_string.interned(), + }, + }, } } } @@ -130,6 +146,13 @@ impl From for CanonicalType { Self::PhantomConst(PhantomConst::new_interned(value.0)) } SerdeCanonicalType::DynSimOnly(value) => Self::DynSimOnly(value), + SerdeCanonicalType::TraceAsString { + inner_ty, + trace_as_string, + } => Self::TraceAsString(TraceAsString { + inner_ty: crate::intern::LazyInterned::Interned(inner_ty), + trace_as_string: crate::intern::LazyInterned::Interned(trace_as_string.inner), + }), } } } diff --git a/crates/fayalite/src/util.rs b/crates/fayalite/src/util.rs index 9796488..6845d3c 100644 --- a/crates/fayalite/src/util.rs +++ b/crates/fayalite/src/util.rs @@ -41,8 +41,9 @@ pub use misc::{ os_str_strip_suffix, serialize_to_json_ascii, serialize_to_json_ascii_pretty, serialize_to_json_ascii_pretty_with_indent, slice_range, try_slice_range, }; -pub(crate) use misc::{InternedStrCompareAsStr, chain}; +pub(crate) use misc::{InternedStrCompareAsStr, chain, copy_le_bytes_to_bitslice}; pub mod job_server; pub mod prefix_sum; pub mod ready_valid; +pub(crate) mod serde_by_id; diff --git a/crates/fayalite/src/util/misc.rs b/crates/fayalite/src/util/misc.rs index 165ab3a..8879a8d 100644 --- a/crates/fayalite/src/util/misc.rs +++ b/crates/fayalite/src/util/misc.rs @@ -612,3 +612,43 @@ impl std::borrow::Borrow for InternedStrCompareAsStr { &self.0 } } + +pub(crate) fn copy_le_bytes_to_bitslice( + dest: &mut BitSlice, + bytes: &[u8], + msb_fill: bool, +) { + let (chunks, remainder) = bytes.as_chunks(); + let mut filled_to = 0; + for (i, chunk) in chunks.iter().enumerate() { + if let Some(start_bit_index) = i.checked_mul(usize::BITS as usize) + && start_bit_index < dest.len() + { + let end_bit_index = start_bit_index + .saturating_add(usize::BITS as usize) + .min(dest.len()); + let bit_len = end_bit_index - start_bit_index; + let chunk = usize::from_le_bytes(*chunk); + dest[start_bit_index..end_bit_index].copy_from_bitslice(&chunk.view_bits()[..bit_len]); + filled_to = end_bit_index; + } else { + break; + } + } + if !remainder.is_empty() { + if let Some(start_bit_index) = chunks.len().checked_mul(usize::BITS as usize) + && start_bit_index < dest.len() + { + let end_bit_index = start_bit_index + .saturating_add(usize::BITS as usize) + .min(dest.len()); + let bit_len = end_bit_index - start_bit_index; + let mut chunk = [if msb_fill { !0 } else { 0 }; _]; + chunk[..remainder.len()].copy_from_slice(remainder); + let chunk = usize::from_le_bytes(chunk); + dest[start_bit_index..end_bit_index].copy_from_bitslice(&chunk.view_bits()[..bit_len]); + filled_to = end_bit_index; + } + } + dest[filled_to..].fill(msb_fill); +} diff --git a/crates/fayalite/src/util/serde_by_id.rs b/crates/fayalite/src/util/serde_by_id.rs new file mode 100644 index 0000000..3db4ab6 --- /dev/null +++ b/crates/fayalite/src/util/serde_by_id.rs @@ -0,0 +1,234 @@ +// SPDX-License-Identifier: LGPL-3.0-or-later +// See Notices.txt for copyright information + +use crate::util::HashMap; +use hashbrown::hash_map::Entry; +use serde::{Deserialize, Serialize, de::Error}; +use std::{ + any::TypeId, + borrow::Cow, + fmt::Write, + hash::{BuildHasher, Hash, Hasher}, + marker::PhantomData, + sync::Mutex, +}; + +pub(crate) struct SerdeByIdProperties { + type_id: TypeId, + type_name: &'static str, + _phantom: PhantomData T>, +} + +impl Clone for SerdeByIdProperties { + fn clone(&self) -> Self { + *self + } +} + +impl Copy for SerdeByIdProperties {} + +impl SerdeByIdProperties { + pub fn of() -> Self { + Self { + type_id: TypeId::of::(), + type_name: std::any::type_name::(), + _phantom: PhantomData, + } + } +} + +pub(crate) trait SerdeByIdTrait: Hash + Eq + Clone + 'static + Send { + fn serde_by_id_properties(&self) -> SerdeByIdProperties; + fn static_table() -> &'static SerdeByIdTable; + const NAME: &'static str; +} + +#[derive(Copy, Clone, Eq, PartialEq, Hash, Debug, Serialize, Deserialize)] +#[serde(transparent)] +struct SerdeRandomId([u32; 4]); + +#[derive(Serialize, Deserialize)] +pub(crate) struct SerdeId<'a, T: SerdeByIdTrait> { + random_id: SerdeRandomId, + #[serde(borrow)] + type_name: Cow<'a, str>, + #[serde(skip)] + _phantom: PhantomData T>, +} + +impl<'a, T: SerdeByIdTrait> Clone for SerdeId<'a, T> { + fn clone(&self) -> Self { + Self { + random_id: self.random_id, + type_name: self.type_name.clone(), + _phantom: PhantomData, + } + } +} + +impl<'a, T: SerdeByIdTrait> Eq for SerdeId<'a, T> {} + +impl<'a, 'b, T: SerdeByIdTrait> PartialEq> for SerdeId<'a, T> { + fn eq(&self, other: &SerdeId<'b, T>) -> bool { + let Self { + random_id, + type_name, + _phantom: _, + } = self; + *random_id == other.random_id && *type_name == other.type_name + } +} + +impl<'a, T: SerdeByIdTrait> Hash for SerdeId<'a, T> { + fn hash(&self, state: &mut H) { + let Self { + random_id, + type_name: _, + _phantom: _, + } = self; + random_id.hash(state); + } +} + +struct SerdeByIdTableRest { + from_serde: HashMap, T>, + serde_id_random_state: std::hash::RandomState, + buffer: String, +} + +impl Default for SerdeByIdTableRest { + fn default() -> Self { + Self { + from_serde: Default::default(), + serde_id_random_state: Default::default(), + buffer: Default::default(), + } + } +} + +impl SerdeByIdTableRest { + fn add_new(&mut self, value: T) -> SerdeId<'static, T> { + let properties = value.serde_by_id_properties(); + let mut try_number = 0u64; + let mut hasher = self.serde_id_random_state.build_hasher(); + // extract more bits of randomness from TypeId -- its Hash impl only hashes 64-bits + write!(self.buffer, "{:?}", properties.type_id).expect("shouldn't ever fail"); + self.buffer.hash(&mut hasher); + loop { + let mut hasher = hasher.clone(); + try_number.hash(&mut hasher); + try_number += 1; + let key = SerdeId { + random_id: SerdeRandomId(std::array::from_fn(|i| { + let mut hasher = hasher.clone(); + i.hash(&mut hasher); + hasher.finish() as u32 + })), + type_name: Cow::Borrowed(properties.type_name), + _phantom: PhantomData, + }; + match self.from_serde.entry(key) { + Entry::Occupied(_) => continue, + Entry::Vacant(e) => { + let key = e.key().clone(); + e.insert(value); + return key; + } + } + } + } +} + +pub(crate) struct SerdeByIdTableMut { + to_serde: HashMap>, + rest: SerdeByIdTableRest, +} + +impl Default for SerdeByIdTableMut { + fn default() -> Self { + Self { + to_serde: Default::default(), + rest: Default::default(), + } + } +} + +impl SerdeByIdTableMut { + pub(crate) fn to_serde(&mut self, value: &T) -> SerdeId<'static, T> { + if let Some(retval) = self.to_serde.get(value) { + return retval.clone(); + } + self.to_serde_insert(value) + } + #[cold] + fn to_serde_insert(&mut self, value: &T) -> SerdeId<'static, T> { + let value = value.clone(); + let retval = self.rest.add_new(value.clone()); + self.to_serde.insert(value, retval.clone()); + retval + } + pub(crate) fn from_serde(&self, id: &SerdeId<'_, T>) -> Option { + self.rest.from_serde.get(id).cloned() + } +} + +pub(crate) struct SerdeByIdTable(Mutex>>); + +impl SerdeByIdTable { + pub(crate) const fn new() -> Self { + Self(Mutex::new(None)) + } + pub(crate) fn to_serde(&self, value: &T) -> SerdeId<'static, T> { + self.0 + .lock() + .expect("shouldn't be poison") + .get_or_insert_with( + #[cold] + || Default::default(), + ) + .to_serde(value) + } + pub(crate) fn from_serde(&self, id: &SerdeId<'_, T>) -> Option { + self.0 + .lock() + .expect("shouldn't be poison") + .get_or_insert_with( + #[cold] + || Default::default(), + ) + .from_serde(id) + } +} + +#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Default, Ord, PartialOrd)] +pub(crate) struct SerdeById { + pub(crate) inner: T, +} + +impl<'de, T: SerdeByIdTrait> Deserialize<'de> for SerdeById { + fn deserialize(deserializer: D) -> Result + where + D: serde::Deserializer<'de>, + { + let id = SerdeId::deserialize(deserializer)?; + let inner = T::static_table().from_serde(&id).ok_or_else(|| { + D::Error::custom(format_args!( + "doesn't match any {} that was serialized this time this program was run: type_name={:?}", + T::NAME, + id.type_name, + )) + })?; + Ok(Self { inner }) + } +} + +impl Serialize for SerdeById { + fn serialize(&self, serializer: S) -> Result + where + S: serde::Serializer, + { + T::static_table() + .to_serde(&self.inner) + .serialize(serializer) + } +} diff --git a/crates/fayalite/src/vendor/lattice.rs b/crates/fayalite/src/vendor/lattice.rs deleted file mode 100644 index 1c2d5c2..0000000 --- a/crates/fayalite/src/vendor/lattice.rs +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: LGPL-3.0-or-later -// See Notices.txt for copyright information - -use crate::{ - annotations::make_annotation_enum, - build::{GlobalParams, ToArgs, WriteArgs}, - intern::Interned, - prelude::{DynPlatform, Platform}, -}; -use clap::ValueEnum; -use ordered_float::NotNan; -use serde::{Deserialize, Serialize}; -use std::fmt; - -// copy of xilinx.rs with same header diff --git a/crates/fayalite/src/vendor/lattice/orangecrab.rs b/crates/fayalite/src/vendor/lattice/orangecrab.rs deleted file mode 100644 index 552eb4a..0000000 --- a/crates/fayalite/src/vendor/lattice/orangecrab.rs +++ /dev/null @@ -1,404 +0,0 @@ -// SPDX-License-Identifier: LGPL-3.0-or-later -// See Notices.txt for copyright information - -use crate::{ - intern::{Intern, Interned}, - module::{instance_with_loc, reg_builder_with_loc, wire_with_loc}, - platform::{ - DynPlatform, Peripheral, PeripheralRef, Peripherals, PeripheralsBuilderFactory, - PeripheralsBuilderFinished, Platform, PlatformAspectSet, - peripherals::{ClockInput, Led, RgbLed, Uart}, - }, - prelude::*, - vendor::xilinx::{ - Device, XdcCreateClockAnnotation, XdcIOStandardAnnotation, XdcLocationAnnotation, - primitives, - }, -}; -use ordered_float::NotNan; -use std::sync::OnceLock; - -macro_rules! arty_a7_platform { - ( - $vis:vis enum $ArtyA7Platform:ident { - $(#[name = $name:literal, device = $device:ident] - $Variant:ident,)* - } - ) => { - #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)] - #[non_exhaustive] - $vis enum $ArtyA7Platform { - $($Variant,)* - } - - impl $ArtyA7Platform { - $vis const VARIANTS: &'static [Self] = &[$(Self::$Variant,)*]; - $vis fn device(self) -> Device { - match self { - $(Self::$Variant => Device::$device,)* - } - } - $vis const fn as_str(self) -> &'static str { - match self { - $(Self::$Variant => $name,)* - } - } - fn get_aspects(self) -> &'static PlatformAspectSet { - match self { - $(Self::$Variant => { - static ASPECTS_SET: OnceLock = OnceLock::new(); - ASPECTS_SET.get_or_init(|| self.make_aspects()) - })* - } - } - } - }; -} - -arty_a7_platform! { - pub enum ArtyA7Platform { - #[name = "arty-a7-35t", device = Xc7a35ticsg324_1l] - ArtyA7_35T, - #[name = "arty-a7-100t", device = Xc7a100ticsg324_1l] - ArtyA7_100T, - } -} - -#[derive(Debug)] -pub struct ArtyA7Peripherals { - clk100_div_pow2: [Peripheral; 4], - rst: Peripheral, - rst_sync: Peripheral, - ld0: Peripheral, - ld1: Peripheral, - ld2: Peripheral, - ld3: Peripheral, - ld4: Peripheral, - ld5: Peripheral, - ld6: Peripheral, - ld7: Peripheral, - uart: Peripheral, - // TODO: add rest of peripherals when we need them -} - -impl Peripherals for ArtyA7Peripherals { - fn append_peripherals<'a>(&'a self, peripherals: &mut Vec>) { - let Self { - clk100_div_pow2, - rst, - rst_sync, - ld0, - ld1, - ld2, - ld3, - ld4, - ld5, - ld6, - ld7, - uart, - } = self; - clk100_div_pow2.append_peripherals(peripherals); - rst.append_peripherals(peripherals); - rst_sync.append_peripherals(peripherals); - ld0.append_peripherals(peripherals); - ld1.append_peripherals(peripherals); - ld2.append_peripherals(peripherals); - ld3.append_peripherals(peripherals); - ld4.append_peripherals(peripherals); - ld5.append_peripherals(peripherals); - ld6.append_peripherals(peripherals); - ld7.append_peripherals(peripherals); - uart.append_peripherals(peripherals); - } -} - -impl ArtyA7Platform { - fn make_aspects(self) -> PlatformAspectSet { - let mut retval = PlatformAspectSet::new(); - retval.insert_new(self.device()); - retval - } -} - -#[hdl_module(extern)] -fn reset_sync() { - #[hdl] - let clk: Clock = m.input(); - #[hdl] - let inp: Bool = m.input(); - #[hdl] - let out: SyncReset = m.output(); - m.annotate_module(BlackBoxInlineAnnotation { - path: "fayalite_arty_a7_reset_sync.v".intern(), - text: r#"module __fayalite_arty_a7_reset_sync(input clk, input inp, output out); - wire reset_0_out; - (* ASYNC_REG = "TRUE" *) - FDPE #( - .INIT(1'b1) - ) reset_0 ( - .Q(reset_0_out), - .C(clk), - .CE(1'b1), - .PRE(inp), - .D(1'b0) - ); - (* ASYNC_REG = "TRUE" *) - FDPE #( - .INIT(1'b1) - ) reset_1 ( - .Q(out), - .C(clk), - .CE(1'b1), - .PRE(inp), - .D(reset_0_out) - ); -endmodule -"# - .intern(), - }); - m.verilog_name("__fayalite_arty_a7_reset_sync"); -} - -impl Platform for ArtyA7Platform { - type Peripherals = ArtyA7Peripherals; - - fn name(&self) -> Interned { - self.as_str().intern() - } - - fn new_peripherals<'builder>( - &self, - builder_factory: PeripheralsBuilderFactory<'builder>, - ) -> (Self::Peripherals, PeripheralsBuilderFinished<'builder>) { - let mut builder = builder_factory.builder(); - - let clk100_div_pow2 = std::array::from_fn(|log2_divisor| { - let divisor = 1u64 << log2_divisor; - let name = if divisor != 1 { - format!("clk100_div_{divisor}") - } else { - "clk100".into() - }; - builder.input_peripheral(name, ClockInput::new(100e6 / divisor as f64)) - }); - builder.add_conflicts(Vec::from_iter(clk100_div_pow2.iter().map(|v| v.id()))); - ( - ArtyA7Peripherals { - clk100_div_pow2, - rst: builder.input_peripheral("rst", Reset), - rst_sync: builder.input_peripheral("rst_sync", SyncReset), - ld0: builder.output_peripheral("ld0", RgbLed), - ld1: builder.output_peripheral("ld1", RgbLed), - ld2: builder.output_peripheral("ld2", RgbLed), - ld3: builder.output_peripheral("ld3", RgbLed), - ld4: builder.output_peripheral("ld4", Led), - ld5: builder.output_peripheral("ld5", Led), - ld6: builder.output_peripheral("ld6", Led), - ld7: builder.output_peripheral("ld7", Led), - uart: builder.output_peripheral("uart", Uart), - }, - builder.finish(), - ) - } - - fn source_location(&self) -> SourceLocation { - SourceLocation::builtin() - } - - fn add_peripherals_in_wrapper_module(&self, m: &ModuleBuilder, peripherals: Self::Peripherals) { - let ArtyA7Peripherals { - clk100_div_pow2, - rst, - rst_sync, - ld0, - ld1, - ld2, - ld3, - ld4, - ld5, - ld6, - ld7, - uart, - } = peripherals; - let make_buffered_input = |name: &str, location: &str, io_standard: &str, invert: bool| { - let pin = m.input_with_loc(name, SourceLocation::builtin(), Bool); - annotate( - pin, - XdcLocationAnnotation { - location: location.intern(), - }, - ); - annotate( - pin, - XdcIOStandardAnnotation { - value: io_standard.intern(), - }, - ); - let buf = instance_with_loc( - &format!("{name}_buf"), - primitives::IBUF(), - SourceLocation::builtin(), - ); - connect(buf.I, pin); - if invert { !buf.O } else { buf.O } - }; - let make_buffered_output = |name: &str, location: &str, io_standard: &str| { - let pin = m.output_with_loc(name, SourceLocation::builtin(), Bool); - annotate( - pin, - XdcLocationAnnotation { - location: location.intern(), - }, - ); - annotate( - pin, - XdcIOStandardAnnotation { - value: io_standard.intern(), - }, - ); - let buf = instance_with_loc( - &format!("{name}_buf"), - primitives::OBUFT(), - SourceLocation::builtin(), - ); - connect(pin, buf.O); - connect(buf.T, false); - buf.I - }; - let mut frequency = clk100_div_pow2[0].ty().frequency(); - let mut log2_divisor = 0; - let mut clk = None; - for (cur_log2_divisor, p) in clk100_div_pow2.into_iter().enumerate() { - let Some(p) = p.into_used() else { - continue; - }; - debug_assert!( - clk.is_none(), - "conflict-handling logic should ensure at most one clock is used", - ); - frequency = p.ty().frequency(); - clk = Some(p); - log2_divisor = cur_log2_divisor; - } - let clk100_buf = make_buffered_input("clk100", "E3", "LVCMOS33", false); - let startup = instance_with_loc( - "startup", - primitives::STARTUPE2_default_inputs(), - SourceLocation::builtin(), - ); - let clk_global_buf = instance_with_loc( - "clk_global_buf", - primitives::BUFGCE(), - SourceLocation::builtin(), - ); - connect(clk_global_buf.CE, startup.EOS); - let mut clk_global_buf_in = clk100_buf.to_clock(); - for prev_log2_divisor in 0..log2_divisor { - let prev_divisor = 1u64 << prev_log2_divisor; - let clk_in = wire_with_loc( - &format!("clk_div_{prev_divisor}"), - SourceLocation::builtin(), - Clock, - ); - connect(clk_in, clk_global_buf_in); - annotate( - clk_in, - XdcCreateClockAnnotation { - period: NotNan::new(1e9 / (100e6 / prev_divisor as f64)) - .expect("known to be valid"), - }, - ); - annotate(clk_in, DontTouchAnnotation); - let cd = wire_with_loc( - &format!("clk_div_{prev_divisor}_in"), - SourceLocation::builtin(), - ClockDomain[AsyncReset], - ); - connect(cd.clk, clk_in); - connect(cd.rst, (!startup.EOS).to_async_reset()); - let divider = reg_builder_with_loc("divider", SourceLocation::builtin()) - .clock_domain(cd) - .reset(false) - .build(); - connect(divider, !divider); - clk_global_buf_in = divider.to_clock(); - } - connect(clk_global_buf.I, clk_global_buf_in); - let clk_out = wire_with_loc("clk_out", SourceLocation::builtin(), Clock); - connect(clk_out, clk_global_buf.O); - annotate( - clk_out, - XdcCreateClockAnnotation { - period: NotNan::new(1e9 / frequency).expect("known to be valid"), - }, - ); - annotate(clk_out, DontTouchAnnotation); - if let Some(clk) = clk { - connect(clk.instance_io_field().clk, clk_out); - } - let rst_value = { - let rst_buf = make_buffered_input("rst", "C2", "LVCMOS33", true); - let rst_sync = instance_with_loc("rst_sync", reset_sync(), SourceLocation::builtin()); - connect(rst_sync.clk, clk_out); - connect(rst_sync.inp, rst_buf | !startup.EOS); - rst_sync.out - }; - if let Some(rst) = rst.into_used() { - connect(rst.instance_io_field(), rst_value.to_reset()); - } - if let Some(rst_sync) = rst_sync.into_used() { - connect(rst_sync.instance_io_field(), rst_value); - } - let rgb_leds = [ - (ld0, ("G6", "F6", "E1")), - (ld1, ("G3", "J4", "G4")), - (ld2, ("J3", "J2", "H4")), - (ld3, ("K1", "H6", "K2")), - ]; - for (rgb_led, (r_loc, g_loc, b_loc)) in rgb_leds { - let r = make_buffered_output(&format!("{}_r", rgb_led.name()), r_loc, "LVCMOS33"); - let g = make_buffered_output(&format!("{}_g", rgb_led.name()), g_loc, "LVCMOS33"); - let b = make_buffered_output(&format!("{}_b", rgb_led.name()), b_loc, "LVCMOS33"); - if let Some(rgb_led) = rgb_led.into_used() { - connect(r, rgb_led.instance_io_field().r); - connect(g, rgb_led.instance_io_field().g); - connect(b, rgb_led.instance_io_field().b); - } else { - connect(r, false); - connect(g, false); - connect(b, false); - } - } - let leds = [(ld4, "H5"), (ld5, "J5"), (ld6, "T9"), (ld7, "T10")]; - for (led, loc) in leds { - let o = make_buffered_output(&led.name(), loc, "LVCMOS33"); - if let Some(led) = led.into_used() { - connect(o, led.instance_io_field().on); - } else { - connect(o, false); - } - } - let uart_tx = make_buffered_output("uart_tx", "D10", "LVCMOS33"); - let uart_rx = make_buffered_input("uart_rx", "A9", "LVCMOS33", false); - if let Some(uart) = uart.into_used() { - connect(uart_tx, uart.instance_io_field().tx); - connect(uart.instance_io_field().rx, uart_rx); - } else { - connect(uart_tx, true); // idle - } - } - - fn aspects(&self) -> PlatformAspectSet { - self.get_aspects().clone() - } -} - -pub(crate) fn built_in_job_kinds() -> impl IntoIterator { - [] -} - -pub(crate) fn built_in_platforms() -> impl IntoIterator { - ArtyA7Platform::VARIANTS - .iter() - .map(|&v| DynPlatform::new(v)) -} diff --git a/crates/fayalite/src/vendor/lattice/primitives.rs b/crates/fayalite/src/vendor/lattice/primitives.rs deleted file mode 100644 index 018eab3..0000000 --- a/crates/fayalite/src/vendor/lattice/primitives.rs +++ /dev/null @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: LGPL-3.0-or-later -// See Notices.txt for copyright information - -#![allow(non_snake_case)] - -use crate::prelude::*; - -//#[hdl_module(extern)] -//pub fn PLACEHOLDER() { -//do this first diff --git a/crates/fayalite/src/vendor/lattice/yosys_nextpnr_trellis.rs b/crates/fayalite/src/vendor/lattice/yosys_nextpnr_trellis.rs deleted file mode 100644 index 94ab863..0000000 --- a/crates/fayalite/src/vendor/lattice/yosys_nextpnr_trellis.rs +++ /dev/null @@ -1,1043 +0,0 @@ -// SPDX-License-Identifier: LGPL-3.0-or-later -// See Notices.txt for copyright information - -use crate::{ - annotations::{Annotation, TargetedAnnotation}, - build::{ - BaseJob, CommandParams, DynJobKind, GetJobPositionDependencies, GlobalParams, - JobAndDependencies, JobArgsAndDependencies, JobDependencies, JobItem, JobItemName, JobKind, - JobKindAndDependencies, ToArgs, WriteArgs, - external::{ - ExternalCommand, ExternalCommandJob, ExternalCommandJobKind, ExternalProgramTrait, - }, - verilog::{UnadjustedVerilog, VerilogDialect, VerilogJob, VerilogJobKind}, - }, - bundle::{Bundle, BundleType}, - expr::target::{Target, TargetBase}, - firrtl::{ScalarizedModuleABI, ScalarizedModuleABIAnnotations, ScalarizedModuleABIPort}, - intern::{Intern, InternSlice, Interned}, - module::{ - NameId, ScopedNameId, TargetName, - transform::visit::{Visit, Visitor}, - }, - prelude::*, - source_location::SourceLocation, - util::{HashSet, job_server::AcquiredJob}, - vendor::lattice::{ - Device, XdcCreateClockAnnotation, XdcIOStandardAnnotation, XdcLocationAnnotation, - LatticeAnnotation, LatticeArgs, - }, -}; -use eyre::Context; -use serde::{Deserialize, Serialize}; -use std::{ - convert::Infallible, - ffi::{OsStr, OsString}, - fmt::{self, Write}, - ops::ControlFlow, - path::{Path, PathBuf}, -}; - -#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Debug, Hash, Default)] -pub struct YosysNextpnrTrellisWriteYsFileJobKind; - -#[derive(Clone, PartialEq, Eq, Hash, Debug, clap::Args)] -pub struct YosysNextpnrTrellisWriteYsFileArgs {} - -impl ToArgs for YosysNextpnrTrellisWriteYsFileArgs { - fn to_args(&self, _args: &mut (impl WriteArgs + ?Sized)) { - let Self {} = self; - } -} - -#[derive(Clone, PartialEq, Eq, Hash, Debug, Serialize, Deserialize)] -pub struct YosysNextpnrTrellisWriteYsFile { - main_verilog_file: Interned, - ys_file: Interned, - json_file: Interned, - json_file_name: Interned, -} - -impl YosysNextpnrTrellisWriteYsFile { - pub fn main_verilog_file(&self) -> Interned { - self.main_verilog_file - } - pub fn ys_file(&self) -> Interned { - self.ys_file - } - pub fn json_file(&self) -> Interned { - self.json_file - } - pub fn json_file_name(&self) -> Interned { - self.json_file_name - } - fn write_ys( - &self, - output: &mut OsString, - additional_files: &[Interned], - main_module_name_id: NameId, - ) -> eyre::Result<()> { - let Self { - main_verilog_file, - ys_file: _, - json_file: _, - json_file_name, - } = self; - for verilog_file in VerilogJob::all_verilog_files(*main_verilog_file, additional_files)? { - output.push("read_verilog -sv \""); - output.push(verilog_file); - output.push("\"\n"); - } - let circuit_name = crate::firrtl::get_circuit_name(main_module_name_id); - writeln!( - output, - "synth_lattice -flatten -abc9 -nobram -arch xc7 -top {circuit_name}" - ) - .expect("writing to OsString can't fail"); - output.push("write_json \""); - output.push(json_file_name); - output.push("\"\n"); - Ok(()) - } -} - -impl JobKind for YosysNextpnrTrellisWriteYsFileJobKind { - type Args = YosysNextpnrTrellisWriteYsFileArgs; - type Job = YosysNextpnrTrellisWriteYsFile; - type Dependencies = JobKindAndDependencies; - - fn dependencies(self) -> Self::Dependencies { - Default::default() - } - - fn args_to_jobs( - mut args: JobArgsAndDependencies, - params: &JobParams, - global_params: &GlobalParams, - ) -> eyre::Result> { - args.dependencies - .dependencies - .args - .args - .additional_args - .verilog_dialect - .get_or_insert(VerilogDialect::Yosys); - args.args_to_jobs_simple(params, global_params, |_kind, args, dependencies| { - let YosysNextpnrTrellisWriteYsFileArgs {} = args; - let base_job = dependencies.get_job::(); - let verilog_job = dependencies.get_job::(); - let json_file = base_job.file_with_ext("json"); - Ok(YosysNextpnrTrellisWriteYsFile { - main_verilog_file: verilog_job.main_verilog_file(), - ys_file: base_job.file_with_ext("ys"), - json_file, - json_file_name: json_file - .interned_file_name() - .expect("known to have file name"), - }) - }) - } - - fn inputs(self, _job: &Self::Job) -> Interned<[JobItemName]> { - [JobItemName::DynamicPaths { - source_job_name: VerilogJobKind.name(), - }] - .intern_slice() - } - - fn outputs(self, job: &Self::Job) -> Interned<[JobItemName]> { - [JobItemName::Path { path: job.ys_file }].intern_slice() - } - - fn name(self) -> Interned { - "yosys-nextpnr-trellis-write-ys-file".intern() - } - - fn external_command_params(self, _job: &Self::Job) -> Option { - None - } - - fn run( - self, - job: &Self::Job, - inputs: &[JobItem], - params: &JobParams, - _global_params: &GlobalParams, - _acquired_job: &mut AcquiredJob, - ) -> eyre::Result> { - assert!(inputs.iter().map(JobItem::name).eq(self.inputs(job))); - let [additional_files] = inputs else { - unreachable!(); - }; - let additional_files = VerilogJob::unwrap_additional_files(additional_files); - let mut contents = OsString::new(); - job.write_ys( - &mut contents, - additional_files, - params.main_module().name_id(), - )?; - let path = job.ys_file; - std::fs::write(path, contents.as_encoded_bytes()) - .wrap_err_with(|| format!("writing {path:?} failed"))?; - Ok(vec![JobItem::Path { path }]) - } - - fn subcommand_hidden(self) -> bool { - true - } -} - -#[derive(Clone, PartialEq, Eq, Hash, Debug, clap::Args)] -pub struct YosysNextpnrTrellisSynthArgs {} - -impl ToArgs for YosysNextpnrTrellisSynthArgs { - fn to_args(&self, _args: &mut (impl WriteArgs + ?Sized)) { - let Self {} = self; - } -} - -#[derive(Clone, PartialEq, Eq, Hash, Deserialize, Serialize)] -pub struct YosysNextpnrTrellisSynth { - #[serde(flatten)] - write_ys_file: YosysNextpnrTrellisWriteYsFile, - ys_file_name: Interned, -} - -impl fmt::Debug for YosysNextpnrTrellisSynth { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - let Self { - write_ys_file: - YosysNextpnrTrellisWriteYsFile { - main_verilog_file, - ys_file, - json_file, - json_file_name, - }, - ys_file_name, - } = self; - f.debug_struct("YosysNextpnrTrellisSynth") - .field("main_verilog_file", main_verilog_file) - .field("ys_file", ys_file) - .field("ys_file_name", ys_file_name) - .field("json_file", json_file) - .field("json_file_name", json_file_name) - .finish() - } -} - -impl YosysNextpnrTrellisSynth { - pub fn main_verilog_file(&self) -> Interned { - self.write_ys_file.main_verilog_file() - } - pub fn ys_file(&self) -> Interned { - self.write_ys_file.ys_file() - } - pub fn ys_file_name(&self) -> Interned { - self.ys_file_name - } - pub fn json_file(&self) -> Interned { - self.write_ys_file.json_file() - } - pub fn json_file_name(&self) -> Interned { - self.write_ys_file.json_file_name() - } -} - -#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Default)] -pub struct Yosys; - -impl ExternalProgramTrait for Yosys { - fn default_program_name() -> Interned { - "yosys".intern() - } -} - -impl ExternalCommand for YosysNextpnrTrellisSynth { - type AdditionalArgs = YosysNextpnrTrellisSynthArgs; - type AdditionalJobData = Self; - type BaseJobPosition = GetJobPositionDependencies< - GetJobPositionDependencies< - GetJobPositionDependencies<::BaseJobPosition>, - >, - >; - type Dependencies = JobKindAndDependencies; - type ExternalProgram = Yosys; - - fn dependencies() -> Self::Dependencies { - Default::default() - } - - fn args_to_jobs( - args: JobArgsAndDependencies>, - params: &JobParams, - global_params: &GlobalParams, - ) -> eyre::Result<( - Self::AdditionalJobData, - ::JobsAndKinds, - )> { - args.args_to_jobs_external_simple(params, global_params, |args, dependencies| { - let YosysNextpnrTrellisSynthArgs {} = args.additional_args; - Ok(Self { - write_ys_file: dependencies.job.job.clone(), - ys_file_name: dependencies - .job - .job - .ys_file() - .interned_file_name() - .expect("known to have file name"), - }) - }) - } - - fn inputs(job: &ExternalCommandJob) -> Interned<[JobItemName]> { - [ - JobItemName::Path { - path: job.additional_job_data().ys_file(), - }, - JobItemName::Path { - path: job.additional_job_data().main_verilog_file(), - }, - JobItemName::DynamicPaths { - source_job_name: VerilogJobKind.name(), - }, - ] - .intern_slice() - } - - fn output_paths(job: &ExternalCommandJob) -> Interned<[Interned]> { - [job.additional_job_data().json_file()].intern_slice() - } - - fn command_line_args(job: &ExternalCommandJob, args: &mut W) { - args.write_arg("-s"); - args.write_interned_arg(job.additional_job_data().ys_file_name()); - } - - fn current_dir(job: &ExternalCommandJob) -> Option> { - Some(job.output_dir()) - } - - fn job_kind_name() -> Interned { - "yosys-nextpnr-trellis-synth".intern() - } - - fn subcommand_hidden() -> bool { - true - } -} - -#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Debug, Hash, Default)] -pub struct YosysNextpnrTrellisWriteXdcFileJobKind; - -#[derive(Clone, PartialEq, Eq, Hash, Debug, clap::Args)] -pub struct YosysNextpnrTrellisWriteXdcFileArgs {} - -impl ToArgs for YosysNextpnrTrellisWriteXdcFileArgs { - fn to_args(&self, _args: &mut (impl WriteArgs + ?Sized)) { - let Self {} = self; - } -} - -#[derive(Clone, PartialEq, Eq, Hash, Debug, Serialize, Deserialize)] -pub struct YosysNextpnrTrellisWriteXdcFile { - firrtl_export_options: crate::firrtl::ExportOptions, - output_dir: Interned, - xdc_file: Interned, -} - -struct WriteXdcContentsError(eyre::Report); - -impl From for WriteXdcContentsError { - fn from(v: eyre::Report) -> Self { - Self(v) - } -} - -impl From for WriteXdcContentsError { - fn from(_v: fmt::Error) -> Self { - unreachable!("String write can't fail") - } -} - -fn tcl_escape(s: impl AsRef) -> String { - let s = s.as_ref(); - if !s.contains(|ch: char| !ch.is_alphanumeric() && ch != '_') { - return s.into(); - } - let mut retval = String::with_capacity(s.len().saturating_add(2)); - retval.push('"'); - for ch in s.chars() { - if let '$' | '\\' | '[' = ch { - retval.push('\\'); - } - retval.push(ch); - } - retval.push('"'); - retval -} - -#[derive(Copy, Clone, Debug)] -enum AnnotationTarget { - None, - Module(Module), - Mem(Mem), - Target(Interned), -} - -impl AnnotationTarget { - fn source_location(self) -> SourceLocation { - match self { - AnnotationTarget::None => unreachable!(), - AnnotationTarget::Module(module) => module.source_location(), - AnnotationTarget::Mem(mem) => mem.source_location(), - AnnotationTarget::Target(target) => target.base().source_location(), - } - } -} - -struct XdcFileWriter { - output: W, - module_depth: usize, - annotation_target: AnnotationTarget, - dont_touch_targets: HashSet>, - required_dont_touch_targets: HashSet>, -} - -impl XdcFileWriter { - fn run(output: W, top_module: Module) -> Result<(), WriteXdcContentsError> { - let mut this = Self { - output, - module_depth: 0, - annotation_target: AnnotationTarget::None, - dont_touch_targets: HashSet::default(), - required_dont_touch_targets: HashSet::default(), - }; - top_module.visit(&mut this)?; - let Self { - output: _, - module_depth: _, - annotation_target: _, - dont_touch_targets, - required_dont_touch_targets, - } = this; - for &target in required_dont_touch_targets.difference(&dont_touch_targets) { - return Err(eyre::eyre!( - "a DontTouchAnnotation is required since the target is also annotated with a LatticeAnnotation:\ntarget: {target:?}\nat: {}", - target.base().source_location(), - ).into()); - } - Ok(()) - } - fn default_visit_with>( - &mut self, - module_depth: usize, - annotation_target: AnnotationTarget, - v: &T, - ) -> Result<(), WriteXdcContentsError> { - let Self { - output: _, - module_depth: old_module_depth, - annotation_target: old_annotation_target, - dont_touch_targets: _, - required_dont_touch_targets: _, - } = *self; - self.module_depth = module_depth; - self.annotation_target = annotation_target; - let retval = v.default_visit(self); - self.module_depth = old_module_depth; - self.annotation_target = old_annotation_target; - retval - } -} - -impl Visitor for XdcFileWriter { - type Error = WriteXdcContentsError; - - fn visit_targeted_annotation(&mut self, v: &TargetedAnnotation) -> Result<(), Self::Error> { - self.default_visit_with(self.module_depth, AnnotationTarget::Target(v.target()), v) - } - - fn visit_module(&mut self, v: &Module) -> Result<(), Self::Error> { - self.default_visit_with( - self.module_depth + 1, - AnnotationTarget::Module(v.canonical()), - v, - ) - } - - fn visit_mem( - &mut self, - v: &Mem, - ) -> Result<(), Self::Error> - where - Element: Visit, - { - self.default_visit_with( - self.module_depth + 1, - AnnotationTarget::Mem(v.canonical()), - v, - ) - } - - fn visit_dont_touch_annotation(&mut self, _v: &DontTouchAnnotation) -> Result<(), Self::Error> { - if let AnnotationTarget::Target(target) = self.annotation_target { - self.dont_touch_targets.insert(target); - } - Ok(()) - } - - fn visit_lattice_annotation(&mut self, v: &LatticeAnnotation) -> Result<(), Self::Error> { - fn todo( - msg: &str, - annotation: &LatticeAnnotation, - source_location: SourceLocation, - ) -> Result { - Err(WriteXdcContentsError(eyre::eyre!( - "{msg}\nannotation: {annotation:?}\nat: {source_location}" - ))) - } - if self.module_depth != 1 { - match todo( - "annotations are not yet supported outside of the top module since the logic to figure out the correct name isn't implemented", - v, - self.annotation_target.source_location(), - )? {} - } - match self.annotation_target { - AnnotationTarget::None => unreachable!(), - AnnotationTarget::Module(module) => match v { - LatticeAnnotation::XdcIOStandard(_) - | LatticeAnnotation::XdcLocation(_) - | LatticeAnnotation::XdcCreateClock(_) => { - return Err(WriteXdcContentsError(eyre::eyre!( - "annotation not allowed on a module: {v:?}\nat: {}", - module.source_location(), - ))); - } - }, - AnnotationTarget::Mem(mem) => match todo( - "lattice annotations are not yet supported on memories since the logic to figure out the correct name isn't implemented", - v, - mem.source_location(), - )? {}, - AnnotationTarget::Target(target) => { - let base = target.base(); - match *base { - TargetBase::ModuleIO(_) => { - // already handled by write_xdc_contents handling the main module's ScalarizedModuleABI - Ok(()) - } - TargetBase::MemPort(mem_port) => { - match todo( - "lattice annotations are not yet supported on memory ports since the logic to figure out the correct name isn't implemented", - v, - mem_port.source_location(), - )? {} - } - TargetBase::Reg(_) - | TargetBase::RegSync(_) - | TargetBase::RegAsync(_) - | TargetBase::Wire(_) => { - match *target { - Target::Base(_) => {} - Target::Child(_) => match todo( - "lattice annotations are not yet supported on parts of registers/wires since the logic to figure out the correct name isn't implemented", - v, - base.source_location(), - )? {}, - } - match base.canonical_ty() { - CanonicalType::UInt(_) - | CanonicalType::SInt(_) - | CanonicalType::Bool(_) - | CanonicalType::AsyncReset(_) - | CanonicalType::SyncReset(_) - | CanonicalType::Reset(_) - | CanonicalType::Clock(_) => {} - CanonicalType::Enum(_) - | CanonicalType::Array(_) - | CanonicalType::Bundle(_) - | CanonicalType::PhantomConst(_) - | CanonicalType::DynSimOnly(_) => match todo( - "lattice annotations are not yet supported on types other than integers, Bool, resets, or Clock since the logic to figure out the correct name isn't implemented", - v, - base.source_location(), - )? {}, - } - self.required_dont_touch_targets.insert(target); - match v { - LatticeAnnotation::XdcIOStandard(_) - | LatticeAnnotation::XdcLocation(_) => { - return Err(WriteXdcContentsError(eyre::eyre!( - "annotation must be on a ModuleIO: {v:?}\nat: {}", - base.source_location(), - ))); - } - LatticeAnnotation::XdcCreateClock(XdcCreateClockAnnotation { - period, - }) => { - let TargetName(ScopedNameId(_, NameId(name, _)), _) = - base.target_name(); - writeln!( - self.output, - "create_clock -period {period} [get_nets {}]", - tcl_escape(name), - )?; - Ok(()) - } - } - } - TargetBase::Instance(instance) => match todo( - "lattice annotations are not yet supported on instances' IO since the logic to figure out the correct name isn't implemented", - v, - instance.source_location(), - )? {}, - } - } - } - } -} - -impl YosysNextpnrTrellisWriteXdcFile { - fn write_xdc_contents_for_port_and_annotations( - &self, - output: &mut impl fmt::Write, - port: &ScalarizedModuleABIPort, - annotations: ScalarizedModuleABIAnnotations<'_>, - ) -> Result<(), WriteXdcContentsError> { - for annotation in annotations { - match annotation.annotation() { - Annotation::DontTouch(_) - | Annotation::SVAttribute(_) - | Annotation::BlackBoxInline(_) - | Annotation::BlackBoxPath(_) - | Annotation::DocString(_) - | Annotation::CustomFirrtl(_) => {} - Annotation::Lattice(LatticeAnnotation::XdcLocation(XdcLocationAnnotation { - location, - })) => writeln!( - output, - "set_property LOC {} [get_ports {}]", - tcl_escape(location), - tcl_escape(port.scalarized_name()), - )?, - Annotation::Lattice(LatticeAnnotation::XdcIOStandard(XdcIOStandardAnnotation { - value, - })) => writeln!( - output, - "set_property IOSTANDARD {} [get_ports {}]", - tcl_escape(value), - tcl_escape(port.scalarized_name()), - )?, - Annotation::Lattice(LatticeAnnotation::XdcCreateClock( - XdcCreateClockAnnotation { period }, - )) => writeln!( - output, - "create_clock -period {period} [get_ports {}]", - tcl_escape(port.scalarized_name()), - )?, - } - } - Ok(()) - } - fn write_xdc_contents( - &self, - output: &mut String, - top_module: &Module, - ) -> eyre::Result<()> { - let scalarized_module_abi = - ScalarizedModuleABI::new(top_module, self.firrtl_export_options) - .map_err(eyre::Report::from)?; - match scalarized_module_abi.for_each_port_and_annotations(|port, annotations| { - match self.write_xdc_contents_for_port_and_annotations(output, port, annotations) { - Ok(()) => ControlFlow::Continue(()), - Err(e) => ControlFlow::Break(e), - } - }) { - ControlFlow::Continue(()) => {} - ControlFlow::Break(e) => return Err(e.0), - } - XdcFileWriter::run(output, *top_module).map_err(|e| e.0) - } -} - -impl JobKind for YosysNextpnrTrellisWriteXdcFileJobKind { - type Args = YosysNextpnrTrellisWriteXdcFileArgs; - type Job = YosysNextpnrTrellisWriteXdcFile; - type Dependencies = JobKindAndDependencies>; - - fn dependencies(self) -> Self::Dependencies { - Default::default() - } - - fn args_to_jobs( - args: JobArgsAndDependencies, - params: &JobParams, - global_params: &GlobalParams, - ) -> eyre::Result> { - let firrtl_export_options = args - .dependencies - .dependencies - .dependencies - .dependencies - .dependencies - .args - .args - .export_options; - args.args_to_jobs_simple(params, global_params, |_kind, args, dependencies| { - let YosysNextpnrTrellisWriteXdcFileArgs {} = args; - let base_job = dependencies.get_job::(); - Ok(YosysNextpnrTrellisWriteXdcFile { - firrtl_export_options, - output_dir: base_job.output_dir(), - xdc_file: base_job.file_with_ext("xdc"), - }) - }) - } - - fn inputs(self, job: &Self::Job) -> Interned<[JobItemName]> { - [JobItemName::Path { - path: job.output_dir, - }] - .intern_slice() - } - - fn outputs(self, job: &Self::Job) -> Interned<[JobItemName]> { - [JobItemName::Path { path: job.xdc_file }].intern_slice() - } - - fn name(self) -> Interned { - "yosys-nextpnr-trellis-write-xdc-file".intern() - } - - fn external_command_params(self, _job: &Self::Job) -> Option { - None - } - - fn run( - self, - job: &Self::Job, - inputs: &[JobItem], - params: &JobParams, - _global_params: &GlobalParams, - _acquired_job: &mut AcquiredJob, - ) -> eyre::Result> { - assert!(inputs.iter().map(JobItem::name).eq(self.inputs(job))); - let mut xdc = String::new(); - job.write_xdc_contents(&mut xdc, params.main_module())?; - std::fs::write(job.xdc_file, xdc)?; - Ok(vec![JobItem::Path { path: job.xdc_file }]) - } - - fn subcommand_hidden(self) -> bool { - true - } -} - -#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Default)] -pub struct NextpnrLattice; - -impl ExternalProgramTrait for NextpnrLattice { - fn default_program_name() -> Interned { - "nextpnr-lattice".intern() - } -} - -#[derive(Clone, PartialEq, Eq, Hash, Debug, clap::Args)] -pub struct YosysNextpnrTrellisRunNextpnrArgs { - #[command(flatten)] - pub common: LatticeArgs, - #[arg(long, env = "CHIPDB_DIR", value_hint = clap::ValueHint::DirPath)] - pub nextpnr_lattice_chipdb_dir: PathBuf, - #[arg(long, default_value_t = 0)] - pub nextpnr_lattice_seed: i32, -} - -impl ToArgs for YosysNextpnrTrellisRunNextpnrArgs { - fn to_args(&self, args: &mut (impl WriteArgs + ?Sized)) { - let Self { - common, - nextpnr_lattice_chipdb_dir, - nextpnr_lattice_seed, - } = self; - common.to_args(args); - args.write_long_option_eq("nextpnr-lattice-chipdb-dir", nextpnr_lattice_chipdb_dir); - args.write_display_arg(format_args!("--nextpnr-lattice-seed={nextpnr_lattice_seed}")); - } -} - -#[derive(Clone, PartialEq, Eq, Hash, Debug, Serialize, Deserialize)] -pub struct YosysNextpnrTrellisRunNextpnr { - nextpnr_lattice_chipdb_dir: Interned, - device: Device, - nextpnr_lattice_seed: i32, - xdc_file: Interned, - xdc_file_name: Interned, - json_file: Interned, - json_file_name: Interned, - routed_json_file: Interned, - routed_json_file_name: Interned, - fasm_file: Interned, - fasm_file_name: Interned, -} - -impl YosysNextpnrTrellisRunNextpnr { - fn chipdb_file(&self) -> Interned { - let mut retval = self - .nextpnr_lattice_chipdb_dir - .join(self.device.trellis_device()); - retval.set_extension("bin"); - retval.intern_deref() - } -} - -impl ExternalCommand for YosysNextpnrTrellisRunNextpnr { - type AdditionalArgs = YosysNextpnrTrellisRunNextpnrArgs; - type AdditionalJobData = Self; - type BaseJobPosition = GetJobPositionDependencies< - GetJobPositionDependencies<::BaseJobPosition>, - >; - type Dependencies = JobKindAndDependencies; - type ExternalProgram = NextpnrLattice; - - fn dependencies() -> Self::Dependencies { - Default::default() - } - - fn args_to_jobs( - args: JobArgsAndDependencies>, - params: &JobParams, - global_params: &GlobalParams, - ) -> eyre::Result<( - Self::AdditionalJobData, - ::JobsAndKinds, - )> { - args.args_to_jobs_external_simple(params, global_params, |args, dependencies| { - let YosysNextpnrTrellisRunNextpnrArgs { - common, - nextpnr_lattice_chipdb_dir, - nextpnr_lattice_seed, - } = args.additional_args; - let base_job = dependencies.get_job::(); - let write_xdc_file = dependencies.get_job::(); - let synth = dependencies.get_job::, _>(); - let routed_json_file = base_job.file_with_ext("routed.json"); - let fasm_file = base_job.file_with_ext("fasm"); - Ok(Self { - nextpnr_lattice_chipdb_dir: nextpnr_lattice_chipdb_dir.intern_deref(), - device: common.require_device(base_job.platform(), global_params)?, - nextpnr_lattice_seed, - xdc_file: write_xdc_file.xdc_file, - xdc_file_name: write_xdc_file - .xdc_file - .interned_file_name() - .expect("known to have file name"), - json_file: synth.additional_job_data().json_file(), - json_file_name: synth.additional_job_data().json_file_name(), - routed_json_file, - routed_json_file_name: routed_json_file - .interned_file_name() - .expect("known to have file name"), - fasm_file, - fasm_file_name: fasm_file - .interned_file_name() - .expect("known to have file name"), - }) - }) - } - - fn inputs(job: &ExternalCommandJob) -> Interned<[JobItemName]> { - [ - JobItemName::Path { - path: job.additional_job_data().json_file, - }, - JobItemName::Path { - path: job.additional_job_data().xdc_file, - }, - ] - .intern_slice() - } - - fn output_paths(job: &ExternalCommandJob) -> Interned<[Interned]> { - [ - job.additional_job_data().routed_json_file, - job.additional_job_data().fasm_file, - ] - .intern_slice() - } - - fn command_line_args(job: &ExternalCommandJob, args: &mut W) { - let job_data @ YosysNextpnrTrellisRunNextpnr { - nextpnr_lattice_seed, - xdc_file_name, - json_file_name, - routed_json_file_name, - fasm_file_name, - .. - } = job.additional_job_data(); - args.write_long_option_eq("chipdb", job_data.chipdb_file()); - args.write_long_option_eq("xdc", xdc_file_name); - args.write_long_option_eq("json", json_file_name); - args.write_long_option_eq("write", routed_json_file_name); - args.write_long_option_eq("fasm", fasm_file_name); - args.write_display_arg(format_args!("--seed={nextpnr_lattice_seed}")); - } - - fn current_dir(job: &ExternalCommandJob) -> Option> { - Some(job.output_dir()) - } - - fn job_kind_name() -> Interned { - "yosys-nextpnr-trellis-run-nextpnr".intern() - } - - fn subcommand_hidden() -> bool { - true - } -} - -#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Default)] -pub struct Xcfasm; - -impl ExternalProgramTrait for Xcfasm { - fn default_program_name() -> Interned { - "xcfasm".intern() - } -} - -#[derive(Clone, PartialEq, Eq, Hash, Debug, clap::Args)] -pub struct YosysNextpnrTrellisArgs { - #[arg(long, env = "DB_DIR", value_hint = clap::ValueHint::DirPath)] - pub prjtrellis_db_dir: PathBuf, -} - -impl ToArgs for YosysNextpnrTrellisArgs { - fn to_args(&self, args: &mut (impl WriteArgs + ?Sized)) { - let Self { prjtrellis_db_dir } = self; - args.write_long_option_eq("prjtrellis-db-dir", prjtrellis_db_dir); - } -} - -#[derive(Clone, PartialEq, Eq, Hash, Debug, Serialize, Deserialize)] -pub struct YosysNextpnrTrellis { - prjtrellis_db_dir: Interned, - device: Device, - fasm_file: Interned, - fasm_file_name: Interned, - frames_file: Interned, - frames_file_name: Interned, - bit_file: Interned, - bit_file_name: Interned, -} - -impl YosysNextpnrTrellis { - fn db_root(&self) -> Interned { - self.prjtrellis_db_dir - .join(self.device.trellis_family()) - .intern_deref() - } - fn part_file(&self) -> Interned { - let mut retval = self.prjtrellis_db_dir.join(self.device.trellis_family()); - retval.push(self.device.trellis_part()); - retval.push("part.yaml"); - retval.intern_deref() - } -} - -impl ExternalCommand for YosysNextpnrTrellis { - type AdditionalArgs = YosysNextpnrTrellisArgs; - type AdditionalJobData = Self; - type BaseJobPosition = GetJobPositionDependencies< - ::BaseJobPosition, - >; - type Dependencies = JobKindAndDependencies>; - type ExternalProgram = Xcfasm; - - fn dependencies() -> Self::Dependencies { - Default::default() - } - - fn args_to_jobs( - args: JobArgsAndDependencies>, - params: &JobParams, - global_params: &GlobalParams, - ) -> eyre::Result<( - Self::AdditionalJobData, - ::JobsAndKinds, - )> { - args.args_to_jobs_external_simple(params, global_params, |args, dependencies| { - let YosysNextpnrTrellisArgs { prjtrellis_db_dir } = args.additional_args; - let base_job = dependencies.get_job::(); - let frames_file = base_job.file_with_ext("frames"); - let bit_file = base_job.file_with_ext("bit"); - Ok(Self { - prjtrellis_db_dir: prjtrellis_db_dir.intern_deref(), - device: dependencies.job.job.additional_job_data().device, - fasm_file: dependencies.job.job.additional_job_data().fasm_file, - fasm_file_name: dependencies.job.job.additional_job_data().fasm_file_name, - frames_file, - frames_file_name: frames_file - .interned_file_name() - .expect("known to have file name"), - bit_file, - bit_file_name: bit_file - .interned_file_name() - .expect("known to have file name"), - }) - }) - } - - fn inputs(job: &ExternalCommandJob) -> Interned<[JobItemName]> { - [JobItemName::Path { - path: job.additional_job_data().fasm_file, - }] - .intern_slice() - } - - fn output_paths(job: &ExternalCommandJob) -> Interned<[Interned]> { - [ - job.additional_job_data().frames_file, - job.additional_job_data().bit_file, - ] - .intern_slice() - } - - fn command_line_args(job: &ExternalCommandJob, args: &mut W) { - let job_data @ YosysNextpnrTrellis { - device, - fasm_file_name, - frames_file_name, - bit_file_name, - .. - } = job.additional_job_data(); - args.write_arg("--sparse"); - args.write_long_option_eq("db-root", job_data.db_root()); - args.write_long_option_eq("part", device.trellis_part()); - args.write_long_option_eq("part_file", job_data.part_file()); - args.write_long_option_eq("fn_in", fasm_file_name); - args.write_long_option_eq("frm_out", frames_file_name); - args.write_long_option_eq("bit_out", bit_file_name); - } - - fn current_dir(job: &ExternalCommandJob) -> Option> { - Some(job.output_dir()) - } - - fn job_kind_name() -> Interned { - "yosys-nextpnr-trellis".intern() - } -} - -pub(crate) fn built_in_job_kinds() -> impl IntoIterator { - [ - DynJobKind::new(YosysNextpnrTrellisWriteYsFileJobKind), - DynJobKind::new(ExternalCommandJobKind::::new()), - DynJobKind::new(YosysNextpnrTrellisWriteXdcFileJobKind), - DynJobKind::new(ExternalCommandJobKind::::new()), - DynJobKind::new(ExternalCommandJobKind::::new()), - ] -} - -pub(crate) fn built_in_platforms() -> impl IntoIterator { - [] -} diff --git a/crates/fayalite/src/vendor/xilinx/yosys_nextpnr_prjxray.rs b/crates/fayalite/src/vendor/xilinx/yosys_nextpnr_prjxray.rs index 3e1ac0c..2d498e7 100644 --- a/crates/fayalite/src/vendor/xilinx/yosys_nextpnr_prjxray.rs +++ b/crates/fayalite/src/vendor/xilinx/yosys_nextpnr_prjxray.rs @@ -546,7 +546,7 @@ impl Visitor for XdcFileWriter { base.source_location(), )? {}, } - match base.canonical_ty() { + match base.canonical_ty().unwrap_transparent_types() { CanonicalType::UInt(_) | CanonicalType::SInt(_) | CanonicalType::Bool(_) @@ -563,6 +563,9 @@ impl Visitor for XdcFileWriter { v, base.source_location(), )? {}, + CanonicalType::TraceAsString(_) => { + unreachable!("handled by unwrap_transparent_types") + } } self.required_dont_touch_targets.insert(target); match v { diff --git a/crates/fayalite/tests/hdl_types.rs b/crates/fayalite/tests/hdl_types.rs index 5030282..cb3510e 100644 --- a/crates/fayalite/tests/hdl_types.rs +++ b/crates/fayalite/tests/hdl_types.rs @@ -244,3 +244,13 @@ pub struct MyTypeWithPrivateMembersWithArg { pub(crate) b: MyPubCrateTypeWithArg, pub c: T, } + +#[hdl(outline_generated)] +pub enum EnumWithOnlyOneVariant { + A, +} + +#[hdl(outline_generated)] +pub enum EnumWithOnlyOneVariant2 { + A(T), +} diff --git a/crates/fayalite/tests/hdl_types_fmt.rs b/crates/fayalite/tests/hdl_types_fmt.rs new file mode 100644 index 0000000..382f64d --- /dev/null +++ b/crates/fayalite/tests/hdl_types_fmt.rs @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: LGPL-3.0-or-later +// See Notices.txt for copyright information +use fayalite::{prelude::*, ty::SimValueDebug}; +use std::fmt; + +#[hdl(outline_generated)] +struct MyStruct0 { + v: T, + a: ArrayType, S>, +} + +#[hdl] +#[test] +fn check_my_struct0() { + let ty = MyStruct0[UInt[8]][3]; + assert_eq!( + format!("{ty:?}"), + "MyStruct0 { v: UInt<8>, a: Array, 3> }", + ); + assert_eq!( + format!("{:?}", ty.mask_type()), + "MaskType { v: Bool, a: Array }", + ); + let v = #[hdl(sim)] + MyStruct0::<_, _> { + v: 0x23u8, + a: [1u8, 2, 3], + }; + assert_eq!( + format!("{v:?}"), + "MyStruct0 { v: 0x23_u8, a: [0x1_u8, 0x2_u8, 0x3_u8] }", + ); +} + +#[hdl(outline_generated, custom_debug())] +struct MyStruct1 { + v: T, + a: ArrayType, S>, +} + +impl fmt::Debug for MyStruct1 { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let Self { v, a } = self; + f.debug_struct("Custom") + .field("v", v) + .field("a", a) + .finish() + } +} + +impl SimValueDebug for MyStruct1 { + #[hdl] + fn sim_value_debug( + value: &::SimValue, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + #[hdl(sim)] + let Self { v, a } = value; + f.debug_struct("Custom") + .field("v", &v) + .field("a", &a) + .finish() + } +} + +#[hdl] +#[test] +fn check_my_struct1() { + let ty = MyStruct1[UInt[8]][3]; + assert_eq!( + format!("{ty:?}"), + "Custom { v: UInt<8>, a: Array, 3> }", + ); + assert_eq!( + format!("{:?}", ty.mask_type()), + "MaskType { v: Bool, a: Array }", + ); + let v = #[hdl(sim)] + MyStruct1::<_, _> { + v: 0x23u8, + a: [1u8, 2, 3], + }; + assert_eq!( + format!("{v:?}"), + "Custom { v: 0x23_u8, a: [0x1_u8, 0x2_u8, 0x3_u8] }", + ); +} + +#[hdl(outline_generated)] +enum MyEnum0 { + Unit, + V(T), + A(ArrayType, S>), +} + +#[hdl] +#[test] +fn check_my_enum0() { + let ty = MyEnum0[UInt[8]][3]; + assert_eq!( + format!("{ty:?}"), + "MyEnum0 { Unit: (), V: UInt<8>, A: Array, 3> }", + ); + let v = #[hdl(sim)] + ty.Unit(); + assert_eq!(format!("{v:?}"), "Unit"); + let v = #[hdl(sim)] + ty.V(0x23u8); + assert_eq!(format!("{v:?}"), "V(0x23_u8)"); + let v = #[hdl(sim)] + ty.A([1u8, 2, 3]); + assert_eq!(format!("{v:?}"), "A([0x1_u8, 0x2_u8, 0x3_u8])"); +} + +#[hdl(outline_generated, custom_debug())] +enum MyEnum1 { + Unit, + V(T), + A(ArrayType, S>), +} + +impl fmt::Debug for MyEnum1 { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let Self { Unit, V, A } = self; + f.debug_struct("Custom") + .field("Unit", Unit) + .field("V", V) + .field("A", A) + .finish() + } +} + +impl SimValueDebug for MyEnum1 { + #[hdl] + fn sim_value_debug( + value: &::SimValue, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + type SimValueT = ::SimValue; + match value { + SimValueT::::Unit(_) => f.write_str("MyEnum1::Unit"), + SimValueT::::V(v, _) => f.debug_tuple("MyEnum1::V").field(v).finish(), + SimValueT::::A(a, _) => f.debug_tuple("MyEnum1::A").field(a).finish(), + SimValueT::::Unknown(_) => f.write_str("MyEnum1::Unknown"), + } + } +} + +#[hdl] +#[test] +fn check_my_enum1() { + let ty = MyEnum1[UInt[8]][3]; + assert_eq!( + format!("{ty:?}"), + "Custom { Unit: (), V: UInt<8>, A: Array, 3> }", + ); + let v = #[hdl(sim)] + ty.Unit(); + assert_eq!(format!("{v:?}"), "MyEnum1::Unit"); + let v = #[hdl(sim)] + ty.V(0x23u8); + assert_eq!(format!("{v:?}"), "MyEnum1::V(0x23_u8)"); + let v = #[hdl(sim)] + ty.A([1u8, 2, 3]); + assert_eq!(format!("{v:?}"), "MyEnum1::A([0x1_u8, 0x2_u8, 0x3_u8])"); +} diff --git a/crates/fayalite/tests/module.rs b/crates/fayalite/tests/module.rs index 2761cba..9dc0107 100644 --- a/crates/fayalite/tests/module.rs +++ b/crates/fayalite/tests/module.rs @@ -13,7 +13,7 @@ use fayalite::{ }; use serde_json::json; -#[hdl(outline_generated)] +#[hdl(outline_generated, cmp_eq)] pub enum TestEnum { A, B(UInt<8>), @@ -679,6 +679,366 @@ circuit check_enum_literals: }; } +#[hdl_module(outline_generated)] +pub fn check_enum_cmp_eq() { + #[hdl] + let lhs: TestEnum = m.input(); + #[hdl] + let rhs: TestEnum = m.input(); + #[hdl] + let eq: Bool = m.output(); + connect(eq, lhs.cmp_eq(rhs)); +} + +#[test] +fn test_enum_cmp_eq() { + let _n = SourceLocation::normalize_files_for_tests(); + let m = check_enum_cmp_eq(); + dbg!(m); + #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161 + assert_export_firrtl! { + m => + options: ExportOptions { + simplify_enums: None, + ..ExportOptions::default() + }, + "/test/check_enum_cmp_eq.fir": r"FIRRTL version 3.2.0 +circuit check_enum_cmp_eq: + type Ty0 = {|A, B: UInt<8>, C: UInt<1>[3]|} + module check_enum_cmp_eq: @[module-XXXXXXXXXX.rs 1:1] + input lhs: Ty0 @[module-XXXXXXXXXX.rs 2:1] + input rhs: Ty0 @[module-XXXXXXXXXX.rs 3:1] + output eq: UInt<1> @[module-XXXXXXXXXX.rs 4:1] + wire TestEnum_cmp_eq: UInt<1> @[module-XXXXXXXXXX.rs 5:1] + connect TestEnum_cmp_eq, UInt<1>(0h0) @[module-XXXXXXXXXX.rs 5:1] + match lhs: @[module-XXXXXXXXXX.rs 5:1] + A: + match rhs: @[module-XXXXXXXXXX.rs 5:1] + A: + connect TestEnum_cmp_eq, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 5:1] + B(_match_arm_value): + skip + C(_match_arm_value_1): + skip + B(_match_arm_value_2): + match rhs: @[module-XXXXXXXXXX.rs 5:1] + A: + skip + B(_match_arm_value_3): + connect TestEnum_cmp_eq, eq(_match_arm_value_2, _match_arm_value_3) @[module-XXXXXXXXXX.rs 5:1] + C(_match_arm_value_4): + skip + C(_match_arm_value_5): + match rhs: @[module-XXXXXXXXXX.rs 5:1] + A: + skip + B(_match_arm_value_6): + skip + C(_match_arm_value_7): + wire _array_literal_expr: UInt<1>[3] + connect _array_literal_expr[0], eq(_match_arm_value_5[0], _match_arm_value_7[0]) + connect _array_literal_expr[1], eq(_match_arm_value_5[1], _match_arm_value_7[1]) + connect _array_literal_expr[2], eq(_match_arm_value_5[2], _match_arm_value_7[2]) + wire _cast_array_to_bits_expr: UInt<1>[3] + connect _cast_array_to_bits_expr[0], _array_literal_expr[0] + connect _cast_array_to_bits_expr[1], _array_literal_expr[1] + connect _cast_array_to_bits_expr[2], _array_literal_expr[2] + wire _cast_to_bits_expr: UInt<3> + connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0])) + connect TestEnum_cmp_eq, andr(_cast_to_bits_expr) @[module-XXXXXXXXXX.rs 5:1] + connect eq, TestEnum_cmp_eq @[module-XXXXXXXXXX.rs 6:1] +", + }; + #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161 + assert_export_firrtl! { + m => + options: ExportOptions { + simplify_enums: Some(SimplifyEnumsKind::SimplifyToEnumsWithNoBody), + ..ExportOptions::default() + }, + "/test/check_enum_cmp_eq.fir": r"FIRRTL version 3.2.0 +circuit check_enum_cmp_eq: + type Ty0 = {|A, B, C|} + type Ty1 = {tag: Ty0, body: UInt<8>} + module check_enum_cmp_eq: @[module-XXXXXXXXXX.rs 1:1] + input lhs: Ty1 @[module-XXXXXXXXXX.rs 2:1] + input rhs: Ty1 @[module-XXXXXXXXXX.rs 3:1] + output eq: UInt<1> @[module-XXXXXXXXXX.rs 4:1] + wire TestEnum_cmp_eq: UInt<1> @[module-XXXXXXXXXX.rs 5:1] + connect TestEnum_cmp_eq, UInt<1>(0h0) @[module-XXXXXXXXXX.rs 5:1] + match lhs.tag: @[module-XXXXXXXXXX.rs 5:1] + A: + match rhs.tag: @[module-XXXXXXXXXX.rs 5:1] + A: + connect TestEnum_cmp_eq, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 5:1] + B: + skip + C: + skip + B: + match rhs.tag: @[module-XXXXXXXXXX.rs 5:1] + A: + skip + B: + connect TestEnum_cmp_eq, eq(bits(lhs.body, 7, 0), bits(rhs.body, 7, 0)) @[module-XXXXXXXXXX.rs 5:1] + C: + skip + C: + match rhs.tag: @[module-XXXXXXXXXX.rs 5:1] + A: + skip + B: + skip + C: + wire _array_literal_expr: UInt<1>[3] + wire _cast_bits_to_array_expr: UInt<1>[3] + wire _cast_bits_to_array_expr_flattened: UInt<1>[3] + connect _cast_bits_to_array_expr_flattened[0], bits(bits(lhs.body, 2, 0), 0, 0) + connect _cast_bits_to_array_expr[0], _cast_bits_to_array_expr_flattened[0] + connect _cast_bits_to_array_expr_flattened[1], bits(bits(lhs.body, 2, 0), 1, 1) + connect _cast_bits_to_array_expr[1], _cast_bits_to_array_expr_flattened[1] + connect _cast_bits_to_array_expr_flattened[2], bits(bits(lhs.body, 2, 0), 2, 2) + connect _cast_bits_to_array_expr[2], _cast_bits_to_array_expr_flattened[2] + wire _cast_bits_to_array_expr_1: UInt<1>[3] + wire _cast_bits_to_array_expr_flattened_1: UInt<1>[3] + connect _cast_bits_to_array_expr_flattened_1[0], bits(bits(rhs.body, 2, 0), 0, 0) + connect _cast_bits_to_array_expr_1[0], _cast_bits_to_array_expr_flattened_1[0] + connect _cast_bits_to_array_expr_flattened_1[1], bits(bits(rhs.body, 2, 0), 1, 1) + connect _cast_bits_to_array_expr_1[1], _cast_bits_to_array_expr_flattened_1[1] + connect _cast_bits_to_array_expr_flattened_1[2], bits(bits(rhs.body, 2, 0), 2, 2) + connect _cast_bits_to_array_expr_1[2], _cast_bits_to_array_expr_flattened_1[2] + connect _array_literal_expr[0], eq(_cast_bits_to_array_expr[0], _cast_bits_to_array_expr_1[0]) + wire _cast_bits_to_array_expr_2: UInt<1>[3] + wire _cast_bits_to_array_expr_flattened_2: UInt<1>[3] + connect _cast_bits_to_array_expr_flattened_2[0], bits(bits(lhs.body, 2, 0), 0, 0) + connect _cast_bits_to_array_expr_2[0], _cast_bits_to_array_expr_flattened_2[0] + connect _cast_bits_to_array_expr_flattened_2[1], bits(bits(lhs.body, 2, 0), 1, 1) + connect _cast_bits_to_array_expr_2[1], _cast_bits_to_array_expr_flattened_2[1] + connect _cast_bits_to_array_expr_flattened_2[2], bits(bits(lhs.body, 2, 0), 2, 2) + connect _cast_bits_to_array_expr_2[2], _cast_bits_to_array_expr_flattened_2[2] + wire _cast_bits_to_array_expr_3: UInt<1>[3] + wire _cast_bits_to_array_expr_flattened_3: UInt<1>[3] + connect _cast_bits_to_array_expr_flattened_3[0], bits(bits(rhs.body, 2, 0), 0, 0) + connect _cast_bits_to_array_expr_3[0], _cast_bits_to_array_expr_flattened_3[0] + connect _cast_bits_to_array_expr_flattened_3[1], bits(bits(rhs.body, 2, 0), 1, 1) + connect _cast_bits_to_array_expr_3[1], _cast_bits_to_array_expr_flattened_3[1] + connect _cast_bits_to_array_expr_flattened_3[2], bits(bits(rhs.body, 2, 0), 2, 2) + connect _cast_bits_to_array_expr_3[2], _cast_bits_to_array_expr_flattened_3[2] + connect _array_literal_expr[1], eq(_cast_bits_to_array_expr_2[1], _cast_bits_to_array_expr_3[1]) + wire _cast_bits_to_array_expr_4: UInt<1>[3] + wire _cast_bits_to_array_expr_flattened_4: UInt<1>[3] + connect _cast_bits_to_array_expr_flattened_4[0], bits(bits(lhs.body, 2, 0), 0, 0) + connect _cast_bits_to_array_expr_4[0], _cast_bits_to_array_expr_flattened_4[0] + connect _cast_bits_to_array_expr_flattened_4[1], bits(bits(lhs.body, 2, 0), 1, 1) + connect _cast_bits_to_array_expr_4[1], _cast_bits_to_array_expr_flattened_4[1] + connect _cast_bits_to_array_expr_flattened_4[2], bits(bits(lhs.body, 2, 0), 2, 2) + connect _cast_bits_to_array_expr_4[2], _cast_bits_to_array_expr_flattened_4[2] + wire _cast_bits_to_array_expr_5: UInt<1>[3] + wire _cast_bits_to_array_expr_flattened_5: UInt<1>[3] + connect _cast_bits_to_array_expr_flattened_5[0], bits(bits(rhs.body, 2, 0), 0, 0) + connect _cast_bits_to_array_expr_5[0], _cast_bits_to_array_expr_flattened_5[0] + connect _cast_bits_to_array_expr_flattened_5[1], bits(bits(rhs.body, 2, 0), 1, 1) + connect _cast_bits_to_array_expr_5[1], _cast_bits_to_array_expr_flattened_5[1] + connect _cast_bits_to_array_expr_flattened_5[2], bits(bits(rhs.body, 2, 0), 2, 2) + connect _cast_bits_to_array_expr_5[2], _cast_bits_to_array_expr_flattened_5[2] + connect _array_literal_expr[2], eq(_cast_bits_to_array_expr_4[2], _cast_bits_to_array_expr_5[2]) + wire _cast_array_to_bits_expr: UInt<1>[3] + connect _cast_array_to_bits_expr[0], _array_literal_expr[0] + connect _cast_array_to_bits_expr[1], _array_literal_expr[1] + connect _cast_array_to_bits_expr[2], _array_literal_expr[2] + wire _cast_to_bits_expr: UInt<3> + connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0])) + connect TestEnum_cmp_eq, andr(_cast_to_bits_expr) @[module-XXXXXXXXXX.rs 5:1] + connect eq, TestEnum_cmp_eq @[module-XXXXXXXXXX.rs 6:1] +", + }; + #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161 + assert_export_firrtl! { + m => + options: ExportOptions { + simplify_enums: Some(SimplifyEnumsKind::ReplaceWithBundleOfUInts), + ..ExportOptions::default() + }, + "/test/check_enum_cmp_eq.fir": r"FIRRTL version 3.2.0 +circuit check_enum_cmp_eq: + type Ty0 = {tag: UInt<2>, body: UInt<8>} + module check_enum_cmp_eq: @[module-XXXXXXXXXX.rs 1:1] + input lhs: Ty0 @[module-XXXXXXXXXX.rs 2:1] + input rhs: Ty0 @[module-XXXXXXXXXX.rs 3:1] + output eq: UInt<1> @[module-XXXXXXXXXX.rs 4:1] + wire TestEnum_cmp_eq: UInt<1> @[module-XXXXXXXXXX.rs 5:1] + connect TestEnum_cmp_eq, UInt<1>(0h0) @[module-XXXXXXXXXX.rs 5:1] + when eq(lhs.tag, UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1] + when eq(rhs.tag, UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1] + connect TestEnum_cmp_eq, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 5:1] + else when eq(rhs.tag, UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1] + skip + else when eq(lhs.tag, UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1] + when eq(rhs.tag, UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1] + skip + else when eq(rhs.tag, UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1] + connect TestEnum_cmp_eq, eq(bits(lhs.body, 7, 0), bits(rhs.body, 7, 0)) @[module-XXXXXXXXXX.rs 5:1] + else when eq(rhs.tag, UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1] + skip + else when eq(rhs.tag, UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1] + skip + else: + wire _array_literal_expr: UInt<1>[3] + wire _cast_bits_to_array_expr: UInt<1>[3] + wire _cast_bits_to_array_expr_flattened: UInt<1>[3] + connect _cast_bits_to_array_expr_flattened[0], bits(bits(lhs.body, 2, 0), 0, 0) + connect _cast_bits_to_array_expr[0], _cast_bits_to_array_expr_flattened[0] + connect _cast_bits_to_array_expr_flattened[1], bits(bits(lhs.body, 2, 0), 1, 1) + connect _cast_bits_to_array_expr[1], _cast_bits_to_array_expr_flattened[1] + connect _cast_bits_to_array_expr_flattened[2], bits(bits(lhs.body, 2, 0), 2, 2) + connect _cast_bits_to_array_expr[2], _cast_bits_to_array_expr_flattened[2] + wire _cast_bits_to_array_expr_1: UInt<1>[3] + wire _cast_bits_to_array_expr_flattened_1: UInt<1>[3] + connect _cast_bits_to_array_expr_flattened_1[0], bits(bits(rhs.body, 2, 0), 0, 0) + connect _cast_bits_to_array_expr_1[0], _cast_bits_to_array_expr_flattened_1[0] + connect _cast_bits_to_array_expr_flattened_1[1], bits(bits(rhs.body, 2, 0), 1, 1) + connect _cast_bits_to_array_expr_1[1], _cast_bits_to_array_expr_flattened_1[1] + connect _cast_bits_to_array_expr_flattened_1[2], bits(bits(rhs.body, 2, 0), 2, 2) + connect _cast_bits_to_array_expr_1[2], _cast_bits_to_array_expr_flattened_1[2] + connect _array_literal_expr[0], eq(_cast_bits_to_array_expr[0], _cast_bits_to_array_expr_1[0]) + wire _cast_bits_to_array_expr_2: UInt<1>[3] + wire _cast_bits_to_array_expr_flattened_2: UInt<1>[3] + connect _cast_bits_to_array_expr_flattened_2[0], bits(bits(lhs.body, 2, 0), 0, 0) + connect _cast_bits_to_array_expr_2[0], _cast_bits_to_array_expr_flattened_2[0] + connect _cast_bits_to_array_expr_flattened_2[1], bits(bits(lhs.body, 2, 0), 1, 1) + connect _cast_bits_to_array_expr_2[1], _cast_bits_to_array_expr_flattened_2[1] + connect _cast_bits_to_array_expr_flattened_2[2], bits(bits(lhs.body, 2, 0), 2, 2) + connect _cast_bits_to_array_expr_2[2], _cast_bits_to_array_expr_flattened_2[2] + wire _cast_bits_to_array_expr_3: UInt<1>[3] + wire _cast_bits_to_array_expr_flattened_3: UInt<1>[3] + connect _cast_bits_to_array_expr_flattened_3[0], bits(bits(rhs.body, 2, 0), 0, 0) + connect _cast_bits_to_array_expr_3[0], _cast_bits_to_array_expr_flattened_3[0] + connect _cast_bits_to_array_expr_flattened_3[1], bits(bits(rhs.body, 2, 0), 1, 1) + connect _cast_bits_to_array_expr_3[1], _cast_bits_to_array_expr_flattened_3[1] + connect _cast_bits_to_array_expr_flattened_3[2], bits(bits(rhs.body, 2, 0), 2, 2) + connect _cast_bits_to_array_expr_3[2], _cast_bits_to_array_expr_flattened_3[2] + connect _array_literal_expr[1], eq(_cast_bits_to_array_expr_2[1], _cast_bits_to_array_expr_3[1]) + wire _cast_bits_to_array_expr_4: UInt<1>[3] + wire _cast_bits_to_array_expr_flattened_4: UInt<1>[3] + connect _cast_bits_to_array_expr_flattened_4[0], bits(bits(lhs.body, 2, 0), 0, 0) + connect _cast_bits_to_array_expr_4[0], _cast_bits_to_array_expr_flattened_4[0] + connect _cast_bits_to_array_expr_flattened_4[1], bits(bits(lhs.body, 2, 0), 1, 1) + connect _cast_bits_to_array_expr_4[1], _cast_bits_to_array_expr_flattened_4[1] + connect _cast_bits_to_array_expr_flattened_4[2], bits(bits(lhs.body, 2, 0), 2, 2) + connect _cast_bits_to_array_expr_4[2], _cast_bits_to_array_expr_flattened_4[2] + wire _cast_bits_to_array_expr_5: UInt<1>[3] + wire _cast_bits_to_array_expr_flattened_5: UInt<1>[3] + connect _cast_bits_to_array_expr_flattened_5[0], bits(bits(rhs.body, 2, 0), 0, 0) + connect _cast_bits_to_array_expr_5[0], _cast_bits_to_array_expr_flattened_5[0] + connect _cast_bits_to_array_expr_flattened_5[1], bits(bits(rhs.body, 2, 0), 1, 1) + connect _cast_bits_to_array_expr_5[1], _cast_bits_to_array_expr_flattened_5[1] + connect _cast_bits_to_array_expr_flattened_5[2], bits(bits(rhs.body, 2, 0), 2, 2) + connect _cast_bits_to_array_expr_5[2], _cast_bits_to_array_expr_flattened_5[2] + connect _array_literal_expr[2], eq(_cast_bits_to_array_expr_4[2], _cast_bits_to_array_expr_5[2]) + wire _cast_array_to_bits_expr: UInt<1>[3] + connect _cast_array_to_bits_expr[0], _array_literal_expr[0] + connect _cast_array_to_bits_expr[1], _array_literal_expr[1] + connect _cast_array_to_bits_expr[2], _array_literal_expr[2] + wire _cast_to_bits_expr: UInt<3> + connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0])) + connect TestEnum_cmp_eq, andr(_cast_to_bits_expr) @[module-XXXXXXXXXX.rs 5:1] + connect eq, TestEnum_cmp_eq @[module-XXXXXXXXXX.rs 6:1] +", + }; + #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161 + assert_export_firrtl! { + m => + options: ExportOptions { + simplify_enums: Some(SimplifyEnumsKind::ReplaceWithUInt), + ..ExportOptions::default() + }, + "/test/check_enum_cmp_eq.fir": r"FIRRTL version 3.2.0 +circuit check_enum_cmp_eq: + module check_enum_cmp_eq: @[module-XXXXXXXXXX.rs 1:1] + input lhs: UInt<10> @[module-XXXXXXXXXX.rs 2:1] + input rhs: UInt<10> @[module-XXXXXXXXXX.rs 3:1] + output eq: UInt<1> @[module-XXXXXXXXXX.rs 4:1] + wire TestEnum_cmp_eq: UInt<1> @[module-XXXXXXXXXX.rs 5:1] + connect TestEnum_cmp_eq, UInt<1>(0h0) @[module-XXXXXXXXXX.rs 5:1] + when eq(bits(lhs, 1, 0), UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1] + when eq(bits(rhs, 1, 0), UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1] + connect TestEnum_cmp_eq, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 5:1] + else when eq(bits(rhs, 1, 0), UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1] + skip + else when eq(bits(lhs, 1, 0), UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1] + when eq(bits(rhs, 1, 0), UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1] + skip + else when eq(bits(rhs, 1, 0), UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1] + connect TestEnum_cmp_eq, eq(bits(bits(lhs, 9, 2), 7, 0), bits(bits(rhs, 9, 2), 7, 0)) @[module-XXXXXXXXXX.rs 5:1] + else when eq(bits(rhs, 1, 0), UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1] + skip + else when eq(bits(rhs, 1, 0), UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1] + skip + else: + wire _array_literal_expr: UInt<1>[3] + wire _cast_bits_to_array_expr: UInt<1>[3] + wire _cast_bits_to_array_expr_flattened: UInt<1>[3] + connect _cast_bits_to_array_expr_flattened[0], bits(bits(bits(lhs, 9, 2), 2, 0), 0, 0) + connect _cast_bits_to_array_expr[0], _cast_bits_to_array_expr_flattened[0] + connect _cast_bits_to_array_expr_flattened[1], bits(bits(bits(lhs, 9, 2), 2, 0), 1, 1) + connect _cast_bits_to_array_expr[1], _cast_bits_to_array_expr_flattened[1] + connect _cast_bits_to_array_expr_flattened[2], bits(bits(bits(lhs, 9, 2), 2, 0), 2, 2) + connect _cast_bits_to_array_expr[2], _cast_bits_to_array_expr_flattened[2] + wire _cast_bits_to_array_expr_1: UInt<1>[3] + wire _cast_bits_to_array_expr_flattened_1: UInt<1>[3] + connect _cast_bits_to_array_expr_flattened_1[0], bits(bits(bits(rhs, 9, 2), 2, 0), 0, 0) + connect _cast_bits_to_array_expr_1[0], _cast_bits_to_array_expr_flattened_1[0] + connect _cast_bits_to_array_expr_flattened_1[1], bits(bits(bits(rhs, 9, 2), 2, 0), 1, 1) + connect _cast_bits_to_array_expr_1[1], _cast_bits_to_array_expr_flattened_1[1] + connect _cast_bits_to_array_expr_flattened_1[2], bits(bits(bits(rhs, 9, 2), 2, 0), 2, 2) + connect _cast_bits_to_array_expr_1[2], _cast_bits_to_array_expr_flattened_1[2] + connect _array_literal_expr[0], eq(_cast_bits_to_array_expr[0], _cast_bits_to_array_expr_1[0]) + wire _cast_bits_to_array_expr_2: UInt<1>[3] + wire _cast_bits_to_array_expr_flattened_2: UInt<1>[3] + connect _cast_bits_to_array_expr_flattened_2[0], bits(bits(bits(lhs, 9, 2), 2, 0), 0, 0) + connect _cast_bits_to_array_expr_2[0], _cast_bits_to_array_expr_flattened_2[0] + connect _cast_bits_to_array_expr_flattened_2[1], bits(bits(bits(lhs, 9, 2), 2, 0), 1, 1) + connect _cast_bits_to_array_expr_2[1], _cast_bits_to_array_expr_flattened_2[1] + connect _cast_bits_to_array_expr_flattened_2[2], bits(bits(bits(lhs, 9, 2), 2, 0), 2, 2) + connect _cast_bits_to_array_expr_2[2], _cast_bits_to_array_expr_flattened_2[2] + wire _cast_bits_to_array_expr_3: UInt<1>[3] + wire _cast_bits_to_array_expr_flattened_3: UInt<1>[3] + connect _cast_bits_to_array_expr_flattened_3[0], bits(bits(bits(rhs, 9, 2), 2, 0), 0, 0) + connect _cast_bits_to_array_expr_3[0], _cast_bits_to_array_expr_flattened_3[0] + connect _cast_bits_to_array_expr_flattened_3[1], bits(bits(bits(rhs, 9, 2), 2, 0), 1, 1) + connect _cast_bits_to_array_expr_3[1], _cast_bits_to_array_expr_flattened_3[1] + connect _cast_bits_to_array_expr_flattened_3[2], bits(bits(bits(rhs, 9, 2), 2, 0), 2, 2) + connect _cast_bits_to_array_expr_3[2], _cast_bits_to_array_expr_flattened_3[2] + connect _array_literal_expr[1], eq(_cast_bits_to_array_expr_2[1], _cast_bits_to_array_expr_3[1]) + wire _cast_bits_to_array_expr_4: UInt<1>[3] + wire _cast_bits_to_array_expr_flattened_4: UInt<1>[3] + connect _cast_bits_to_array_expr_flattened_4[0], bits(bits(bits(lhs, 9, 2), 2, 0), 0, 0) + connect _cast_bits_to_array_expr_4[0], _cast_bits_to_array_expr_flattened_4[0] + connect _cast_bits_to_array_expr_flattened_4[1], bits(bits(bits(lhs, 9, 2), 2, 0), 1, 1) + connect _cast_bits_to_array_expr_4[1], _cast_bits_to_array_expr_flattened_4[1] + connect _cast_bits_to_array_expr_flattened_4[2], bits(bits(bits(lhs, 9, 2), 2, 0), 2, 2) + connect _cast_bits_to_array_expr_4[2], _cast_bits_to_array_expr_flattened_4[2] + wire _cast_bits_to_array_expr_5: UInt<1>[3] + wire _cast_bits_to_array_expr_flattened_5: UInt<1>[3] + connect _cast_bits_to_array_expr_flattened_5[0], bits(bits(bits(rhs, 9, 2), 2, 0), 0, 0) + connect _cast_bits_to_array_expr_5[0], _cast_bits_to_array_expr_flattened_5[0] + connect _cast_bits_to_array_expr_flattened_5[1], bits(bits(bits(rhs, 9, 2), 2, 0), 1, 1) + connect _cast_bits_to_array_expr_5[1], _cast_bits_to_array_expr_flattened_5[1] + connect _cast_bits_to_array_expr_flattened_5[2], bits(bits(bits(rhs, 9, 2), 2, 0), 2, 2) + connect _cast_bits_to_array_expr_5[2], _cast_bits_to_array_expr_flattened_5[2] + connect _array_literal_expr[2], eq(_cast_bits_to_array_expr_4[2], _cast_bits_to_array_expr_5[2]) + wire _cast_array_to_bits_expr: UInt<1>[3] + connect _cast_array_to_bits_expr[0], _array_literal_expr[0] + connect _cast_array_to_bits_expr[1], _array_literal_expr[1] + connect _cast_array_to_bits_expr[2], _array_literal_expr[2] + wire _cast_to_bits_expr: UInt<3> + connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0])) + connect TestEnum_cmp_eq, andr(_cast_to_bits_expr) @[module-XXXXXXXXXX.rs 5:1] + connect eq, TestEnum_cmp_eq @[module-XXXXXXXXXX.rs 6:1] +", + }; +} + #[hdl_module(outline_generated)] pub fn check_struct_enum_match() { #[hdl] diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs index cbe0b58..80ae4c2 100644 --- a/crates/fayalite/tests/sim.rs +++ b/crates/fayalite/tests/sim.rs @@ -1,13 +1,20 @@ // SPDX-License-Identifier: LGPL-3.0-or-later // See Notices.txt for copyright information +use bitvec::{order::Lsb0, view::BitView}; use fayalite::{ - memory::{ReadStruct, ReadWriteStruct, WriteStruct}, - module::{instance_with_loc, memory_with_init_and_loc, reg_builder_with_loc}, + assert_export_firrtl, + firrtl::ExportOptions, + memory::{ReadStruct, ReadWriteStruct, WriteStruct, splat_mask}, + module::{ + instance_with_loc, memory_with_init_and_loc, reg_builder_with_loc, + transform::simplify_enums::SimplifyEnumsKind, + }, prelude::*, reset::ResetType, sim::vcd::VcdWriterDecls, - util::RcWriter, + ty::SimValueDebug, + util::{RcWriter, ready_valid::queue}, }; use std::{collections::BTreeMap, num::NonZeroUsize, rc::Rc}; @@ -550,6 +557,150 @@ fn test_enums() { } } +#[hdl] +pub enum EnumWithSimpleBody { + A(UInt<8>), + B(UInt<8>), + C(UInt<8>), +} + +#[hdl_module(outline_generated)] +pub fn enum_with_simple_body() { + #[hdl] + let which_in: UInt<8> = m.input(); + #[hdl] + let data_in: UInt<8> = m.input(); + #[hdl] + let which_out: UInt<8> = m.output(); + #[hdl] + let data_out: UInt<8> = m.output(); + #[hdl] + let enum_out: EnumWithSimpleBody = m.output(); + + #[hdl] + if which_in.cmp_eq(0u8) { + connect(enum_out, EnumWithSimpleBody.A(data_in)); + } else if which_in.cmp_eq(1u8) { + connect(enum_out, EnumWithSimpleBody.B(data_in)); + } else { + connect(enum_out, EnumWithSimpleBody.C(data_in)); + } + + #[hdl] + match enum_out { + EnumWithSimpleBody::A(v) => { + connect(which_out, 0u8); + connect(data_out, v); + } + EnumWithSimpleBody::B(v) => { + connect(which_out, 1u8); + connect(data_out, v); + } + EnumWithSimpleBody::C(v) => { + connect(which_out, 2u8); + connect(data_out, v); + } + } +} + +#[hdl] +#[test] +fn test_enum_with_simple_body() { + let _n = SourceLocation::normalize_files_for_tests(); + let mut sim = Simulation::new(enum_with_simple_body()); + let mut writer = RcWriter::default(); + sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); + for which in 0u8..=2 { + for data in (0..u8::MAX).step_by(45) { + sim.write(sim.io().which_in, which); + sim.write(sim.io().data_in, data); + sim.advance_time(SimDuration::from_micros(1)); + assert_eq!(sim.read(sim.io().which_out).as_int(), which); + assert_eq!(sim.read(sim.io().data_out).as_int(), data); + } + } + sim.flush_traces().unwrap(); + let vcd = String::from_utf8(writer.take()).unwrap(); + println!("####### VCD:\n{vcd}\n#######"); + #[derive(Debug)] + struct WireState<'a> { + name: &'a str, + space_then_id: Option<&'a str>, + value: Option<&'a str>, + } + impl<'a> WireState<'a> { + fn new(name: &'a str) -> Self { + Self { + name, + space_then_id: None, + value: None, + } + } + } + let mut variant_wires = [ + WireState::new("A"), + WireState::new("B"), + WireState::new("C"), + ]; + // check that output .vcd has the proper values for all variants' wires + for (is_last, line) in vcd.lines().map(|line| (false, line)).chain([(true, "")]) { + if let Some(line) = line.strip_prefix("$var wire 8") + && let Some(line) = line.strip_suffix(" $end") + && let Some((space_then_id, state)) = variant_wires + .iter_mut() + .find_map(|state| Some((line.strip_suffix(state.name)?.strip_suffix(" ")?, state))) + { + assert_eq!(space_then_id.chars().next(), Some(' ')); + assert!( + space_then_id + .chars() + .skip(1) + .all(|ch| matches!(ch, '!'..='~')) + ); + assert_eq!(state.space_then_id.replace(space_then_id), None); + } else if line.starts_with("#") || is_last { + let Some(expected_value) = variant_wires[0].value else { + panic!( + "variant {} hasn't been initialized before a timestamp or EOF: {variant_wires:#?}\n\ + line={line:?}", + variant_wires[0].name, + ); + }; + for state in &variant_wires { + assert_eq!( + state.value, + Some(expected_value), + "at a timestamp or EOF: variant value for {} doesn't match expected value.\n\ + {variant_wires:#?}\nline={line:?}", + state.name, + ); + } + } else if line.starts_with("b") { + for state in &mut variant_wires { + let Some(space_then_id) = state.space_then_id else { + let name = state.name; + panic!( + "variant {name} hasn't had an id assigned yet: {variant_wires:#?}\n\ + line={line:?}", + ); + }; + if let Some(value) = line.strip_suffix(space_then_id) { + state.value = Some(value); + break; + } + } + } + } + if vcd != include_str!("sim/expected/enum_with_simple_body.vcd") { + panic!(); + } + let sim_debug = format!("{sim:#?}"); + println!("#######\n{sim_debug}\n#######"); + if sim_debug != include_str!("sim/expected/enum_with_simple_body.txt") { + panic!(); + } +} + #[hdl_module(outline_generated)] pub fn memories() { #[hdl] @@ -2495,3 +2646,967 @@ fn test_sim_read_past() { panic!(); } } + +#[hdl_module(outline_generated)] +pub fn last_connect() { + #[hdl] + let inp: HdlOption> = m.input(); + #[hdl] + let out: HdlOption> = m.output(); + connect(out, HdlNone()); + #[hdl] + if let HdlSome(v) = inp { + #[hdl] + let w = wire(); + connect(out, HdlSome(w)); + connect(w, v.len() as u8); + for (i, v) in v.into_iter().enumerate() { + #[hdl] + if v { + connect(w, i as u8); + } + } + } +} + +#[hdl] +#[test] +fn test_last_connect() { + let _n = SourceLocation::normalize_files_for_tests(); + let mut sim = Simulation::new(last_connect()); + let mut writer = RcWriter::default(); + sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); + let bools = [false, true]; + sim.write(sim.io().inp, HdlNone()); + sim.advance_time(SimDuration::from_micros(1)); + let expected: SimValue>> = #[hdl(sim)] + HdlNone(); + assert_eq!(sim.read(sim.io().out), expected); + for a in bools { + for b in bools { + for c in bools { + for d in bools { + let inp = [a, b, c, d]; + sim.write(sim.io().inp, HdlSome(inp)); + sim.advance_time(SimDuration::from_micros(1)); + let mut expected = inp.len() as u8; + for (i, v) in inp.into_iter().enumerate() { + if v { + expected = i as u8; + } + } + let expected: SimValue>> = #[hdl(sim)] + HdlSome(expected); + let out = sim.read(sim.io().out); + println!("expected={expected:?} out={out:?} inp={inp:?}"); + assert_eq!(expected, out); + } + } + } + } + sim.flush_traces().unwrap(); + let vcd = String::from_utf8(writer.take()).unwrap(); + println!("####### VCD:\n{vcd}\n#######"); + if vcd != include_str!("sim/expected/last_connect.vcd") { + panic!(); + } + let sim_debug = format!("{sim:#?}"); + println!("#######\n{sim_debug}\n#######"); + if sim_debug != include_str!("sim/expected/last_connect.txt") { + panic!(); + } +} + +#[track_caller] +#[hdl] +fn test_queue_helper( + capacity: usize, + inp_ready_is_comb: bool, + out_valid_is_comb: bool, + expected_vcd: &str, + expected_sim_debug: &str, +) { + let _n = SourceLocation::normalize_files_for_tests(); + let mut sim = Simulation::new(queue( + UInt::<8>::new_static(), + NonZeroUsize::new(capacity).expect("capacity should be non-zero"), + inp_ready_is_comb, + out_valid_is_comb, + )); + let writer = RcWriter::default(); + sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); + struct DumpVcdOnDrop { + writer: Option, + } + impl Drop for DumpVcdOnDrop { + fn drop(&mut self) { + if let Some(mut writer) = self.writer.take() { + let vcd = String::from_utf8(writer.take()).unwrap(); + println!("####### VCD:\n{vcd}\n#######"); + } + } + } + let mut writer = DumpVcdOnDrop { + writer: Some(writer), + }; + sim.write_clock(sim.io().cd.clk, false); + sim.write_reset(sim.io().cd.rst, true); + let mut input_value = 0u8; + let mut expected_output_value = 0u8; + /// deterministic random numbers + fn rand(mut v: u32) -> bool { + // random 32-bit primes + v = v.wrapping_mul(0xF807B7EF).rotate_left(16); + v ^= 0xA1E24BBA; // random 32-bit constant + v = v.wrapping_mul(0xE9D30017).rotate_left(16); + v = v.wrapping_mul(0x3895AFFB).rotate_left(16); + v & 1 != 0 + } + for cycle in 0..100u32 { + println!("cycle: {cycle}"); + sim.write( + sim.io().inp.data, + if rand(cycle) { + #[hdl(sim)] + HdlSome(input_value) + } else { + #[hdl(sim)] + HdlNone() + }, + ); + sim.write_bool(sim.io().out.ready, rand(u32::MAX / 2 + cycle)); + sim.advance_time(SimDuration::from_nanos(500)); + if !sim.read_reset(sim.io().cd.rst) { + let inp_ready = sim.read_bool(sim.io().inp.ready); + if inp_ready { + #[hdl(sim)] + if let HdlSome(v) = sim.read(sim.io().inp.data) { + println!("enqueued {v}, expected {input_value:#x}"); + assert_eq!(v.as_int(), input_value); + input_value = input_value.wrapping_add(1); + } + } + let out_valid = #[hdl(sim)] + if let HdlSome(v) = sim.read(sim.io().out.data) { + if sim.read_bool(sim.io().out.ready) { + println!("dequeued {v}, expected {expected_output_value:#x}"); + assert_eq!(v.as_int(), expected_output_value); + expected_output_value = expected_output_value.wrapping_add(1); + } + true + } else { + false + }; + assert!(inp_ready || out_valid, "queue isn't making progress"); + } + sim.write_clock(sim.io().cd.clk, true); + sim.advance_time(SimDuration::from_nanos(500)); + sim.write_clock(sim.io().cd.clk, false); + sim.write_reset(sim.io().cd.rst, false); + } + sim.flush_traces().unwrap(); + let vcd = String::from_utf8(writer.writer.take().unwrap().take()).unwrap(); + println!("####### VCD:\n{vcd}\n#######"); + if vcd != expected_vcd { + panic!(); + } + let sim_debug = format!("{sim:#?}"); + println!("#######\n{sim_debug}\n#######"); + if sim_debug != expected_sim_debug { + panic!(); + } +} + +#[test] +fn test_queue_1_false_false() { + test_queue_helper( + 1, + false, + false, + include_str!("sim/expected/queue_1_false_false.vcd"), + include_str!("sim/expected/queue_1_false_false.txt"), + ); +} + +#[test] +fn test_queue_1_false_true() { + test_queue_helper( + 1, + false, + true, + include_str!("sim/expected/queue_1_false_true.vcd"), + include_str!("sim/expected/queue_1_false_true.txt"), + ); +} + +#[test] +fn test_queue_1_true_false() { + test_queue_helper( + 1, + true, + false, + include_str!("sim/expected/queue_1_true_false.vcd"), + include_str!("sim/expected/queue_1_true_false.txt"), + ); +} + +#[test] +fn test_queue_1_true_true() { + test_queue_helper( + 1, + true, + true, + include_str!("sim/expected/queue_1_true_true.vcd"), + include_str!("sim/expected/queue_1_true_true.txt"), + ); +} + +#[test] +fn test_queue_2_false_false() { + test_queue_helper( + 2, + false, + false, + include_str!("sim/expected/queue_2_false_false.vcd"), + include_str!("sim/expected/queue_2_false_false.txt"), + ); +} + +#[test] +fn test_queue_2_false_true() { + test_queue_helper( + 2, + false, + true, + include_str!("sim/expected/queue_2_false_true.vcd"), + include_str!("sim/expected/queue_2_false_true.txt"), + ); +} + +#[test] +fn test_queue_2_true_false() { + test_queue_helper( + 2, + true, + false, + include_str!("sim/expected/queue_2_true_false.vcd"), + include_str!("sim/expected/queue_2_true_false.txt"), + ); +} + +#[test] +fn test_queue_2_true_true() { + test_queue_helper( + 2, + true, + true, + include_str!("sim/expected/queue_2_true_true.vcd"), + include_str!("sim/expected/queue_2_true_true.txt"), + ); +} + +#[test] +fn test_queue_3_false_false() { + test_queue_helper( + 3, + false, + false, + include_str!("sim/expected/queue_3_false_false.vcd"), + include_str!("sim/expected/queue_3_false_false.txt"), + ); +} + +#[test] +fn test_queue_3_false_true() { + test_queue_helper( + 3, + false, + true, + include_str!("sim/expected/queue_3_false_true.vcd"), + include_str!("sim/expected/queue_3_false_true.txt"), + ); +} + +#[test] +fn test_queue_3_true_false() { + test_queue_helper( + 3, + true, + false, + include_str!("sim/expected/queue_3_true_false.vcd"), + include_str!("sim/expected/queue_3_true_false.txt"), + ); +} + +#[test] +fn test_queue_3_true_true() { + test_queue_helper( + 3, + true, + true, + include_str!("sim/expected/queue_3_true_true.vcd"), + include_str!("sim/expected/queue_3_true_true.txt"), + ); +} + +#[test] +fn test_queue_4_false_false() { + test_queue_helper( + 4, + false, + false, + include_str!("sim/expected/queue_4_false_false.vcd"), + include_str!("sim/expected/queue_4_false_false.txt"), + ); +} + +#[test] +fn test_queue_4_false_true() { + test_queue_helper( + 4, + false, + true, + include_str!("sim/expected/queue_4_false_true.vcd"), + include_str!("sim/expected/queue_4_false_true.txt"), + ); +} + +#[test] +fn test_queue_4_true_false() { + test_queue_helper( + 4, + true, + false, + include_str!("sim/expected/queue_4_true_false.vcd"), + include_str!("sim/expected/queue_4_true_false.txt"), + ); +} + +#[test] +fn test_queue_4_true_true() { + test_queue_helper( + 4, + true, + true, + include_str!("sim/expected/queue_4_true_true.vcd"), + include_str!("sim/expected/queue_4_true_true.txt"), + ); +} + +#[hdl(outline_generated, custom_debug(sim), cmp_eq)] +pub enum HasCustomDebug { + Text(UInt<512>), + FmtError, +} + +impl HasCustomDebug { + #[hdl] + pub fn new_sim(text: Result<&str, std::fmt::Error>) -> SimValue { + match text { + Ok(text) => { + let mut retval = HasCustomDebug.Text.zero(); + let src = text.as_bytes().view_bits::(); + let dest = retval.bits_mut(); + let len = src.len().min(dest.len()); + dest[..len].clone_from_bitslice(&src[..len]); + #[hdl(sim)] + HasCustomDebug.Text(retval) + } + Err(std::fmt::Error) => + { + #[hdl(sim)] + HasCustomDebug.FmtError() + } + } + } + pub fn new(text: Result<&str, std::fmt::Error>) -> Expr { + Self::new_sim(text).to_expr() + } +} + +impl SimValueDebug for HasCustomDebug { + #[hdl] + fn sim_value_debug( + value: &::SimValue, + f: &mut std::fmt::Formatter<'_>, + ) -> std::fmt::Result { + if f.alternate() { + return #[hdl(sim)] + match value { + Self::FmtError => f.write_str("FmtError"), + Self::Text(text) => f.debug_tuple("Text").field(text).finish(), + }; + } + #[hdl(sim)] + match value { + Self::FmtError => Err(std::fmt::Error), + Self::Text(text) => { + assert_eq!(text.ty().width() % u8::BITS as usize, 0); + let mut bytes = vec![0u8; text.ty().width() / u8::BITS as usize]; + bytes + .view_bits_mut::() + .clone_from_bitslice(text.bits()); + if let Some(len) = bytes.iter().position(|b| *b == 0) { + bytes.truncate(len); + } + f.write_str(&String::from_utf8_lossy(&bytes)) + } + } + } +} + +#[hdl_module(outline_generated)] +pub fn sim_trace_as_string() { + #[hdl] + let clk: Clock = m.input(); + #[hdl] + let read: ReadStruct>, ConstUsize<8>> = m.input(); + #[hdl] + let write: WriteStruct, 2>, ConstUsize<8>> = m.input(); + #[hdl] + let mut mem = memory_with_init([[HasCustomDebug::new(Ok("")).to_trace_as_string(); 2]; 4]); + let read_port = mem.new_read_port(); + connect(read_port.clk, clk); + connect_any(read_port.addr, read.addr); + connect(read_port.en, read.en); + for (l, r) in read.data.iter().zip(read_port.data.iter()) { + connect(l, &**r); + } + let write_port = mem.new_write_port(); + connect(write_port.clk, clk); + connect_any(write_port.addr, write.addr); + connect(write_port.data, write.data); + connect(write_port.en, write.en); + connect(write_port.mask, write.mask); +} + +#[hdl] +#[test] +fn test_sim_trace_as_string() { + let _n = SourceLocation::normalize_files_for_tests(); + let m = sim_trace_as_string(); + let mut sim = Simulation::new(m); + // sim.set_breakpoints_unstable(Default::default(), true); + let mut writer = RcWriter::default(); + sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); + sim.write(sim.io().clk, false); + sim.write(sim.io().read.clk, false); + sim.write(sim.io().write.clk, false); + #[derive(Debug)] + struct TestCase { + read: Option<(u8, [Result<&'static str, std::fmt::Error>; 2])>, + write_addr: Option, + write_data: [Result<&'static str, std::fmt::Error>; 2], + write_mask: [bool; 2], + } + const TEST_CASES: &[TestCase] = &[ + TestCase { + read: None, + write_addr: None, + write_data: [Ok(""); 2], + write_mask: [false; 2], + }, + TestCase { + read: None, + write_addr: Some(0), + write_data: [Ok("mem[0][0]"), Ok("mem[0][1]")], + write_mask: [true; 2], + }, + TestCase { + read: None, + write_addr: Some(1), + write_data: [Ok("mem[1][0]"), Ok("mem[1][1]")], + write_mask: [true; 2], + }, + TestCase { + read: None, + write_addr: Some(2), + write_data: [Ok("mem[2][0]"), Ok("mem[2][1]")], + write_mask: [true; 2], + }, + TestCase { + read: None, + write_addr: Some(3), + write_data: [Ok("mem[3][0]"), Ok("mem[3][1]")], + write_mask: [true; 2], + }, + TestCase { + read: Some((1, [Ok("mem[1][0]"), Ok("mem[1][1]")])), + write_addr: None, + write_data: [Err(std::fmt::Error), Err(std::fmt::Error)], + write_mask: [true; 2], + }, + TestCase { + read: Some((1, [Err(std::fmt::Error), Err(std::fmt::Error)])), + write_addr: Some(1), + write_data: [Err(std::fmt::Error), Err(std::fmt::Error)], + write_mask: [true; 2], + }, + ]; + for test_case in TEST_CASES { + let TestCase { + read, + write_addr, + write_data, + write_mask, + } = test_case; + sim.write(sim.io().read.addr, read.map(|v| v.0).unwrap_or(0)); + sim.write(sim.io().read.en, read.is_some()); + sim.write(sim.io().write.addr, write_addr.unwrap_or(0)); + sim.write(sim.io().write.en, write_addr.is_some()); + sim.write( + sim.io().write.data, + write_data.map(|v| HasCustomDebug::new_sim(v).to_trace_as_string()), + ); + sim.write( + sim.io().write.mask, + write_mask.map(|v| splat_mask(TraceAsString[HasCustomDebug], v.to_expr())), + ); + sim.write(sim.io().clk, false); + sim.advance_time(SimDuration::from_nanos(500)); + sim.write(sim.io().clk, true); + sim.advance_time(SimDuration::from_nanos(500)); + if let Some((_, expected_read_data)) = read { + let read_data = sim.read(sim.io().read.data); + let expected_read_data = expected_read_data + .map(HasCustomDebug::new_sim) + .into_sim_value(); + assert!( + *read_data.inner() == expected_read_data, + "{read_data:#?}\n!= {expected_read_data:#?}", + ); + } + } + sim.flush_traces().unwrap(); + let vcd = String::from_utf8(writer.take()).unwrap(); + println!("####### VCD:\n{vcd}\n#######"); + if vcd != include_str!("sim/expected/sim_trace_as_string.vcd") { + panic!(); + } + let sim_debug = format!("{sim:#?}"); + println!("#######\n{sim_debug}\n#######"); + if sim_debug != include_str!("sim/expected/sim_trace_as_string.txt") { + panic!(); + } +} + +#[test] +fn test_firrtl_trace_as_string() { + let _n = SourceLocation::normalize_files_for_tests(); + let m = sim_trace_as_string(); + #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161 + assert_export_firrtl! { + m => + options: ExportOptions { + simplify_memories: false, + simplify_enums: None, + ..ExportOptions::default() + }, + "/test/sim_trace_as_string.fir": r#"FIRRTL version 3.2.0 +circuit sim_trace_as_string: %[[ + { + "class": "firrtl.annotations.MemoryFileInlineAnnotation", + "filename": "/test/sim_trace_as_string/mem.mem", + "hexOrBinary": "b", + "target": "~sim_trace_as_string|sim_trace_as_string>mem" + } +]] + type Ty0 = {|Text: UInt<512>, FmtError|} + type Ty1 = {addr: UInt<8>, en: UInt<1>, clk: Clock, flip data: Ty0[2]} + type Ty2 = {addr: UInt<8>, en: UInt<1>, clk: Clock, data: Ty0[2], mask: UInt<1>[2]} + type Ty3 = {addr: UInt<2>, en: UInt<1>, clk: Clock, flip data: Ty0[2]} + type Ty4 = {addr: UInt<2>, en: UInt<1>, clk: Clock, data: Ty0[2], mask: UInt<1>[2]} + module sim_trace_as_string: @[module-XXXXXXXXXX.rs 1:1] + input clk: Clock @[module-XXXXXXXXXX.rs 2:1] + input `read`: Ty1 @[module-XXXXXXXXXX.rs 3:1] + input `write`: Ty2 @[module-XXXXXXXXXX.rs 4:1] + mem `mem`: @[module-XXXXXXXXXX.rs 5:1] + data-type => Ty0[2] + depth => 4 + read-latency => 0 + write-latency => 1 + read-under-write => old + reader => r0 + writer => w1 + connect `mem`.r0.clk, clk @[module-XXXXXXXXXX.rs 7:1] + ; connect different types: + ; lhs: UInt<2> + ; rhs: UInt<8> + connect `mem`.r0.addr, `read`.addr @[module-XXXXXXXXXX.rs 8:1] + connect `mem`.r0.en, `read`.en @[module-XXXXXXXXXX.rs 9:1] + connect `read`.data[0], `mem`.r0.data[0] @[module-XXXXXXXXXX.rs 10:1] + connect `read`.data[1], `mem`.r0.data[1] @[module-XXXXXXXXXX.rs 10:1] + connect `mem`.w1.clk, clk @[module-XXXXXXXXXX.rs 12:1] + ; connect different types: + ; lhs: UInt<2> + ; rhs: UInt<8> + connect `mem`.w1.addr, `write`.addr @[module-XXXXXXXXXX.rs 13:1] + connect `mem`.w1.data, `write`.data @[module-XXXXXXXXXX.rs 14:1] + connect `mem`.w1.en, `write`.en @[module-XXXXXXXXXX.rs 15:1] + connect `mem`.w1.mask, `write`.mask @[module-XXXXXXXXXX.rs 16:1] +"#, + "/test/sim_trace_as_string/mem.mem": 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+", + }; + #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161 + assert_export_firrtl! { + m => + options: ExportOptions { + simplify_memories: true, + simplify_enums: None, + ..ExportOptions::default() + }, + "/test/sim_trace_as_string.fir": r#"FIRRTL version 3.2.0 +circuit sim_trace_as_string: %[[ + { + "class": "firrtl.annotations.MemoryFileInlineAnnotation", + "filename": "/test/sim_trace_as_string/mem.mem", + "hexOrBinary": "b", + "target": "~sim_trace_as_string|sim_trace_as_string>mem" + } +]] + type Ty0 = {|Text: UInt<512>, FmtError|} + type Ty1 = {addr: UInt<8>, en: UInt<1>, clk: Clock, flip data: Ty0[2]} + type Ty2 = {addr: UInt<8>, en: UInt<1>, clk: Clock, data: Ty0[2], mask: UInt<1>[2]} + type Ty3 = {addr: UInt<2>, en: UInt<1>, clk: Clock, flip data: Ty0[2]} + type Ty4 = {addr: UInt<2>, en: UInt<1>, clk: Clock, data: Ty0[2], mask: UInt<1>[2]} + type Ty5 = {addr: UInt<2>, en: UInt<1>, clk: Clock, flip data: UInt<513>[2]} + type Ty6 = {addr: UInt<2>, en: UInt<1>, clk: Clock, data: UInt<513>[2], mask: UInt<1>[2]} + module sim_trace_as_string: @[module-XXXXXXXXXX.rs 1:1] + input clk: Clock @[module-XXXXXXXXXX.rs 2:1] + input `read`: Ty1 @[module-XXXXXXXXXX.rs 3:1] + input `write`: Ty2 @[module-XXXXXXXXXX.rs 4:1] + mem `mem`: @[module-XXXXXXXXXX.rs 5:1] + data-type => UInt<513>[2] + depth => 4 + read-latency => 0 + write-latency => 1 + read-under-write => old + reader => r0 + writer => w1 + wire mem_r0: Ty3 @[module-XXXXXXXXXX.rs 6:1] + wire mem_w1: Ty4 @[module-XXXXXXXXXX.rs 11:1] + wire _cast_bits_to_enum_expr: Ty0 + wire _cast_bits_to_enum_expr_body: UInt<512> + connect _cast_bits_to_enum_expr_body, head(`mem`.r0.data[0], 512) + when eq(UInt<1>(0), tail(`mem`.r0.data[0], 512)): + connect _cast_bits_to_enum_expr, {|Text: UInt<512>, FmtError|}(Text, _cast_bits_to_enum_expr_body) + else: + connect _cast_bits_to_enum_expr, {|Text: UInt<512>, FmtError|}(FmtError) + connect mem_r0.data[0], _cast_bits_to_enum_expr @[module-XXXXXXXXXX.rs 6:1] + wire _cast_bits_to_enum_expr_1: Ty0 + wire _cast_bits_to_enum_expr_body_1: UInt<512> + connect _cast_bits_to_enum_expr_body_1, head(`mem`.r0.data[1], 512) + when eq(UInt<1>(0), tail(`mem`.r0.data[1], 512)): + connect _cast_bits_to_enum_expr_1, {|Text: UInt<512>, FmtError|}(Text, _cast_bits_to_enum_expr_body_1) + else: + connect _cast_bits_to_enum_expr_1, {|Text: UInt<512>, FmtError|}(FmtError) + connect mem_r0.data[1], _cast_bits_to_enum_expr_1 @[module-XXXXXXXXXX.rs 6:1] + wire _cast_enum_to_bits_expr: UInt<513> + match mem_w1.data[0]: + Text(_cast_enum_to_bits_expr_Text): + connect _cast_enum_to_bits_expr, pad(cat(_cast_enum_to_bits_expr_Text, UInt<1>(0)), 513) + FmtError: + connect _cast_enum_to_bits_expr, UInt<513>(1) + connect `mem`.w1.data[0], _cast_enum_to_bits_expr @[module-XXXXXXXXXX.rs 11:1] + connect `mem`.w1.mask[0], mem_w1.mask[0] @[module-XXXXXXXXXX.rs 11:1] + wire _cast_enum_to_bits_expr_1: UInt<513> + match mem_w1.data[1]: + Text(_cast_enum_to_bits_expr_Text_1): + connect _cast_enum_to_bits_expr_1, pad(cat(_cast_enum_to_bits_expr_Text_1, UInt<1>(0)), 513) + FmtError: + connect _cast_enum_to_bits_expr_1, UInt<513>(1) + connect `mem`.w1.data[1], _cast_enum_to_bits_expr_1 @[module-XXXXXXXXXX.rs 11:1] + connect `mem`.w1.mask[1], mem_w1.mask[1] @[module-XXXXXXXXXX.rs 11:1] + connect `mem`.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 6:1] + connect `mem`.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 6:1] + connect `mem`.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 6:1] + connect `mem`.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 11:1] + connect `mem`.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 11:1] + connect `mem`.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 11:1] + connect mem_r0.clk, clk @[module-XXXXXXXXXX.rs 7:1] + ; connect different types: + ; lhs: UInt<2> + ; rhs: UInt<8> + connect mem_r0.addr, `read`.addr @[module-XXXXXXXXXX.rs 8:1] + connect mem_r0.en, `read`.en @[module-XXXXXXXXXX.rs 9:1] + connect `read`.data[0], mem_r0.data[0] @[module-XXXXXXXXXX.rs 10:1] + connect `read`.data[1], mem_r0.data[1] @[module-XXXXXXXXXX.rs 10:1] + connect mem_w1.clk, clk @[module-XXXXXXXXXX.rs 12:1] + ; connect different types: + ; lhs: UInt<2> + ; rhs: UInt<8> + connect mem_w1.addr, `write`.addr @[module-XXXXXXXXXX.rs 13:1] + connect mem_w1.data, `write`.data @[module-XXXXXXXXXX.rs 14:1] + connect mem_w1.en, `write`.en @[module-XXXXXXXXXX.rs 15:1] + connect mem_w1.mask, `write`.mask @[module-XXXXXXXXXX.rs 16:1] +"#, + "/test/sim_trace_as_string/mem.mem": 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+", + }; + #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161 + assert_export_firrtl! { + m => + options: ExportOptions { + simplify_memories: false, + simplify_enums: Some(SimplifyEnumsKind::SimplifyToEnumsWithNoBody), + ..ExportOptions::default() + }, + "/test/sim_trace_as_string.fir": r#"FIRRTL version 3.2.0 +circuit sim_trace_as_string: %[[ + { + "class": "firrtl.annotations.MemoryFileInlineAnnotation", + "filename": "/test/sim_trace_as_string/mem.mem", + "hexOrBinary": "b", + "target": "~sim_trace_as_string|sim_trace_as_string>mem" + } +]] + type Ty0 = {|Text, FmtError|} + type Ty1 = {tag: Ty0, body: UInt<512>} + type Ty2 = {addr: UInt<8>, en: UInt<1>, clk: Clock, flip data: Ty1[2]} + type Ty3 = {addr: UInt<8>, en: UInt<1>, clk: Clock, data: Ty1[2], mask: UInt<1>[2]} + type Ty4 = {addr: UInt<2>, en: UInt<1>, clk: Clock, data: Ty1[2], mask: UInt<1>[2]} + type Ty5 = {tag: UInt<1>, body: UInt<1>} + type Ty6 = {addr: UInt<2>, en: UInt<1>, clk: Clock, data: Ty1[2], mask: Ty5[2]} + type Ty7 = {addr: UInt<2>, en: UInt<1>, clk: Clock, flip data: Ty1[2]} + module sim_trace_as_string: @[module-XXXXXXXXXX.rs 1:1] + input clk: Clock @[module-XXXXXXXXXX.rs 2:1] + input `read`: Ty2 @[module-XXXXXXXXXX.rs 3:1] + input `write`: Ty3 @[module-XXXXXXXXXX.rs 4:1] + mem `mem`: @[module-XXXXXXXXXX.rs 5:1] + data-type => Ty1[2] + depth => 4 + read-latency => 0 + write-latency => 1 + read-under-write => old + reader => r0 + writer => w1 + wire mem_w1: Ty4 @[module-XXXXXXXXXX.rs 11:1] + connect `mem`.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 11:1] + connect `mem`.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 11:1] + connect `mem`.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 11:1] + connect `mem`.w1.data, mem_w1.data @[module-XXXXXXXXXX.rs 11:1] + connect `mem`.w1.mask[0].tag, mem_w1.mask[0] @[module-XXXXXXXXXX.rs 11:1] + connect `mem`.w1.mask[0].body, mem_w1.mask[0] @[module-XXXXXXXXXX.rs 11:1] + connect `mem`.w1.mask[1].tag, mem_w1.mask[1] @[module-XXXXXXXXXX.rs 11:1] + connect `mem`.w1.mask[1].body, mem_w1.mask[1] @[module-XXXXXXXXXX.rs 11:1] + connect `mem`.r0.clk, clk @[module-XXXXXXXXXX.rs 7:1] + ; connect different types: + ; lhs: UInt<2> + ; rhs: UInt<8> + connect `mem`.r0.addr, `read`.addr @[module-XXXXXXXXXX.rs 8:1] + connect `mem`.r0.en, `read`.en @[module-XXXXXXXXXX.rs 9:1] + connect `read`.data[0], `mem`.r0.data[0] @[module-XXXXXXXXXX.rs 10:1] + connect `read`.data[1], `mem`.r0.data[1] @[module-XXXXXXXXXX.rs 10:1] + connect mem_w1.clk, clk @[module-XXXXXXXXXX.rs 12:1] + ; connect different types: + ; lhs: UInt<2> + ; rhs: UInt<8> + connect mem_w1.addr, `write`.addr @[module-XXXXXXXXXX.rs 13:1] + connect mem_w1.data, `write`.data @[module-XXXXXXXXXX.rs 14:1] + connect mem_w1.en, `write`.en @[module-XXXXXXXXXX.rs 15:1] + connect mem_w1.mask, `write`.mask @[module-XXXXXXXXXX.rs 16:1] +"#, + "/test/sim_trace_as_string/mem.mem": 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+", + }; + #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161 + assert_export_firrtl! { + m => + options: ExportOptions { + simplify_memories: true, + simplify_enums: Some(SimplifyEnumsKind::SimplifyToEnumsWithNoBody), + ..ExportOptions::default() + }, + "/test/sim_trace_as_string.fir": r#"FIRRTL version 3.2.0 +circuit sim_trace_as_string: %[[ + { + "class": "firrtl.annotations.MemoryFileInlineAnnotation", + "filename": "/test/sim_trace_as_string/mem_0_tag.mem", + "hexOrBinary": "b", + "target": "~sim_trace_as_string|sim_trace_as_string>mem_0_tag" + }, + { + "class": "firrtl.annotations.MemoryFileInlineAnnotation", + "filename": "/test/sim_trace_as_string/mem_0_body.mem", + "hexOrBinary": "h", + "target": "~sim_trace_as_string|sim_trace_as_string>mem_0_body" + }, + { + "class": "firrtl.annotations.MemoryFileInlineAnnotation", + "filename": "/test/sim_trace_as_string/mem_1_tag.mem", + "hexOrBinary": "b", + "target": "~sim_trace_as_string|sim_trace_as_string>mem_1_tag" + }, + { + "class": "firrtl.annotations.MemoryFileInlineAnnotation", + "filename": "/test/sim_trace_as_string/mem_1_body.mem", + "hexOrBinary": "h", + "target": "~sim_trace_as_string|sim_trace_as_string>mem_1_body" + } +]] + type Ty0 = {|Text, FmtError|} + type Ty1 = {tag: Ty0, body: UInt<512>} + type Ty2 = {addr: UInt<8>, en: UInt<1>, clk: Clock, flip data: Ty1[2]} + type Ty3 = {addr: UInt<8>, en: UInt<1>, clk: Clock, data: Ty1[2], mask: UInt<1>[2]} + type Ty4 = {addr: UInt<2>, en: UInt<1>, clk: Clock, flip data: Ty1[2]} + type Ty5 = {tag: UInt<1>, body: UInt<1>} + type Ty6 = {addr: UInt<2>, en: UInt<1>, clk: Clock, data: Ty1[2], mask: Ty5[2]} + type Ty7 = {addr: UInt<2>, en: UInt<1>, clk: Clock, flip data: UInt<1>} + type Ty8 = {addr: UInt<2>, en: UInt<1>, clk: Clock, data: UInt<1>, mask: UInt<1>} + type Ty9 = {addr: UInt<2>, en: UInt<1>, clk: Clock, flip data: UInt<512>} + type Ty10 = {addr: UInt<2>, en: UInt<1>, clk: Clock, data: UInt<512>, mask: UInt<1>} + type Ty11 = {addr: UInt<2>, en: UInt<1>, clk: Clock, data: Ty1[2], mask: UInt<1>[2]} + module sim_trace_as_string: @[module-XXXXXXXXXX.rs 1:1] + input clk: Clock @[module-XXXXXXXXXX.rs 2:1] + input `read`: Ty2 @[module-XXXXXXXXXX.rs 3:1] + input `write`: Ty3 @[module-XXXXXXXXXX.rs 4:1] + mem mem_0_tag: @[module-XXXXXXXXXX.rs 5:1] + data-type => UInt<1> + depth => 4 + read-latency => 0 + write-latency => 1 + read-under-write => old + reader => r0 + writer => w1 + mem mem_0_body: @[module-XXXXXXXXXX.rs 5:1] + data-type => UInt<512> + depth => 4 + read-latency => 0 + write-latency => 1 + read-under-write => old + reader => r0 + writer => w1 + mem mem_1_tag: @[module-XXXXXXXXXX.rs 5:1] + data-type => UInt<1> + depth => 4 + read-latency => 0 + write-latency => 1 + read-under-write => old + reader => r0 + writer => w1 + mem mem_1_body: @[module-XXXXXXXXXX.rs 5:1] + data-type => UInt<512> + depth => 4 + read-latency => 0 + write-latency => 1 + read-under-write => old + reader => r0 + writer => w1 + wire mem_r0: Ty4 @[module-XXXXXXXXXX.rs 6:1] + wire mem_w1: Ty6 @[module-XXXXXXXXXX.rs 11:1] + wire _cast_bits_to_enum_expr: Ty0 + when eq(UInt<1>(0), tail(mem_0_tag.r0.data, 0)): + connect _cast_bits_to_enum_expr, {|Text, FmtError|}(Text) + else: + connect _cast_bits_to_enum_expr, {|Text, FmtError|}(FmtError) + connect mem_r0.data[0].tag, _cast_bits_to_enum_expr @[module-XXXXXXXXXX.rs 6:1] + wire _cast_enum_to_bits_expr: UInt<1> + match mem_w1.data[0].tag: + Text: + connect _cast_enum_to_bits_expr, UInt<1>(0) + FmtError: + connect _cast_enum_to_bits_expr, UInt<1>(1) + connect mem_0_tag.w1.data, _cast_enum_to_bits_expr @[module-XXXXXXXXXX.rs 11:1] + connect mem_0_tag.w1.mask, mem_w1.mask[0].tag @[module-XXXXXXXXXX.rs 11:1] + connect mem_0_tag.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 6:1] + connect mem_0_tag.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 6:1] + connect mem_0_tag.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 6:1] + connect mem_0_tag.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 11:1] + connect mem_0_tag.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 11:1] + connect mem_0_tag.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 11:1] + connect mem_r0.data[0].body, mem_0_body.r0.data @[module-XXXXXXXXXX.rs 6:1] + connect mem_0_body.w1.data, mem_w1.data[0].body @[module-XXXXXXXXXX.rs 11:1] + connect mem_0_body.w1.mask, mem_w1.mask[0].body @[module-XXXXXXXXXX.rs 11:1] + connect mem_0_body.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 6:1] + connect mem_0_body.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 6:1] + connect mem_0_body.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 6:1] + connect mem_0_body.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 11:1] + connect mem_0_body.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 11:1] + connect mem_0_body.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 11:1] + wire _cast_bits_to_enum_expr_1: Ty0 + when eq(UInt<1>(0), tail(mem_1_tag.r0.data, 0)): + connect _cast_bits_to_enum_expr_1, {|Text, FmtError|}(Text) + else: + connect _cast_bits_to_enum_expr_1, {|Text, FmtError|}(FmtError) + connect mem_r0.data[1].tag, _cast_bits_to_enum_expr_1 @[module-XXXXXXXXXX.rs 6:1] + wire _cast_enum_to_bits_expr_1: UInt<1> + match mem_w1.data[1].tag: + Text: + connect _cast_enum_to_bits_expr_1, UInt<1>(0) + FmtError: + connect _cast_enum_to_bits_expr_1, UInt<1>(1) + connect mem_1_tag.w1.data, _cast_enum_to_bits_expr_1 @[module-XXXXXXXXXX.rs 11:1] + connect mem_1_tag.w1.mask, mem_w1.mask[1].tag @[module-XXXXXXXXXX.rs 11:1] + connect mem_1_tag.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 6:1] + connect mem_1_tag.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 6:1] + connect mem_1_tag.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 6:1] + connect mem_1_tag.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 11:1] + connect mem_1_tag.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 11:1] + connect mem_1_tag.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 11:1] + connect mem_r0.data[1].body, mem_1_body.r0.data @[module-XXXXXXXXXX.rs 6:1] + connect mem_1_body.w1.data, mem_w1.data[1].body @[module-XXXXXXXXXX.rs 11:1] + connect mem_1_body.w1.mask, mem_w1.mask[1].body @[module-XXXXXXXXXX.rs 11:1] + connect mem_1_body.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 6:1] + connect mem_1_body.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 6:1] + connect mem_1_body.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 6:1] + connect mem_1_body.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 11:1] + connect mem_1_body.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 11:1] + connect mem_1_body.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 11:1] + wire mem_w1_1: Ty11 @[module-XXXXXXXXXX.rs 11:1] + connect mem_w1.addr, mem_w1_1.addr @[module-XXXXXXXXXX.rs 11:1] + connect mem_w1.en, mem_w1_1.en @[module-XXXXXXXXXX.rs 11:1] + connect mem_w1.clk, mem_w1_1.clk @[module-XXXXXXXXXX.rs 11:1] + connect mem_w1.data, mem_w1_1.data @[module-XXXXXXXXXX.rs 11:1] + connect mem_w1.mask[0].tag, mem_w1_1.mask[0] @[module-XXXXXXXXXX.rs 11:1] + connect mem_w1.mask[0].body, mem_w1_1.mask[0] @[module-XXXXXXXXXX.rs 11:1] + connect mem_w1.mask[1].tag, mem_w1_1.mask[1] @[module-XXXXXXXXXX.rs 11:1] + connect mem_w1.mask[1].body, mem_w1_1.mask[1] @[module-XXXXXXXXXX.rs 11:1] + connect mem_r0.clk, clk @[module-XXXXXXXXXX.rs 7:1] + ; connect different types: + ; lhs: UInt<2> + ; rhs: UInt<8> + connect mem_r0.addr, `read`.addr @[module-XXXXXXXXXX.rs 8:1] + connect mem_r0.en, `read`.en @[module-XXXXXXXXXX.rs 9:1] + connect `read`.data[0], mem_r0.data[0] @[module-XXXXXXXXXX.rs 10:1] + connect `read`.data[1], mem_r0.data[1] @[module-XXXXXXXXXX.rs 10:1] + connect mem_w1_1.clk, clk @[module-XXXXXXXXXX.rs 12:1] + ; connect different types: + ; lhs: UInt<2> + ; rhs: UInt<8> + connect mem_w1_1.addr, `write`.addr @[module-XXXXXXXXXX.rs 13:1] + connect mem_w1_1.data, `write`.data @[module-XXXXXXXXXX.rs 14:1] + connect mem_w1_1.en, `write`.en @[module-XXXXXXXXXX.rs 15:1] + connect mem_w1_1.mask, `write`.mask @[module-XXXXXXXXXX.rs 16:1] +"#, + "/test/sim_trace_as_string/mem_0_body.mem": r"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +", + "/test/sim_trace_as_string/mem_0_tag.mem": r"0 +0 +0 +0 +", + "/test/sim_trace_as_string/mem_1_body.mem": r"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +", + "/test/sim_trace_as_string/mem_1_tag.mem": r"0 +0 +0 +0 +", + }; +} diff --git a/crates/fayalite/tests/sim/expected/array_rw.txt b/crates/fayalite/tests/sim/expected/array_rw.txt index 27b040d..271ec3c 100644 --- a/crates/fayalite/tests/sim/expected/array_rw.txt +++ b/crates/fayalite/tests/sim/expected/array_rw.txt @@ -1218,6 +1218,7 @@ Simulation { index: StatePartIndex(0), ty: UInt<8>, }, + maybe_changed: true, state: 0xff, last_state: 0xff, }, @@ -1227,6 +1228,7 @@ Simulation { index: StatePartIndex(1), ty: UInt<8>, }, + maybe_changed: true, state: 0x7f, last_state: 0x7f, }, @@ -1236,6 +1238,7 @@ Simulation { index: StatePartIndex(2), ty: UInt<8>, }, + maybe_changed: true, state: 0x3f, last_state: 0x3f, }, @@ -1245,6 +1248,7 @@ Simulation { index: StatePartIndex(3), ty: UInt<8>, }, + maybe_changed: true, state: 0x1f, last_state: 0x1f, }, @@ -1254,6 +1258,7 @@ Simulation { index: StatePartIndex(4), ty: UInt<8>, }, + maybe_changed: true, state: 0x0f, last_state: 0x0f, }, @@ -1263,6 +1268,7 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, + maybe_changed: true, state: 0x07, last_state: 0x07, }, @@ -1272,6 +1278,7 @@ Simulation { index: StatePartIndex(6), ty: UInt<8>, }, + maybe_changed: true, state: 0x03, last_state: 0x03, }, @@ -1281,6 +1288,7 @@ Simulation { index: StatePartIndex(7), ty: UInt<8>, }, + maybe_changed: true, state: 0x01, last_state: 0x01, }, @@ -1290,6 +1298,7 @@ Simulation { index: StatePartIndex(8), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -1299,6 +1308,7 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, + maybe_changed: true, state: 0x80, last_state: 0x80, }, @@ -1308,6 +1318,7 @@ Simulation { index: StatePartIndex(10), ty: UInt<8>, }, + maybe_changed: true, state: 0xc0, last_state: 0xc0, }, @@ -1317,6 +1328,7 @@ Simulation { index: StatePartIndex(11), ty: UInt<8>, }, + maybe_changed: true, state: 0xe0, last_state: 0xe0, }, @@ -1326,6 +1338,7 @@ Simulation { index: StatePartIndex(12), ty: UInt<8>, }, + maybe_changed: true, state: 0xf0, last_state: 0xf0, }, @@ -1335,6 +1348,7 @@ Simulation { index: StatePartIndex(13), ty: UInt<8>, }, + maybe_changed: true, state: 0xf8, last_state: 0xf8, }, @@ -1344,6 +1358,7 @@ Simulation { index: StatePartIndex(14), ty: UInt<8>, }, + maybe_changed: true, state: 0xfc, last_state: 0xfc, }, @@ -1353,6 +1368,7 @@ Simulation { index: StatePartIndex(15), ty: UInt<8>, }, + maybe_changed: true, state: 0xfe, last_state: 0xfe, }, @@ -1362,6 +1378,7 @@ Simulation { index: StatePartIndex(16), ty: UInt<8>, }, + maybe_changed: true, state: 0xff, last_state: 0xff, }, @@ -1371,6 +1388,7 @@ Simulation { index: StatePartIndex(17), ty: UInt<8>, }, + maybe_changed: true, state: 0x7f, last_state: 0x7f, }, @@ -1380,6 +1398,7 @@ Simulation { index: StatePartIndex(18), ty: UInt<8>, }, + maybe_changed: true, state: 0x3f, last_state: 0x3f, }, @@ -1389,6 +1408,7 @@ Simulation { index: StatePartIndex(19), ty: UInt<8>, }, + maybe_changed: true, state: 0x1f, last_state: 0x1f, }, @@ -1398,6 +1418,7 @@ Simulation { index: StatePartIndex(20), ty: UInt<8>, }, + maybe_changed: true, state: 0x0f, last_state: 0x0f, }, @@ -1407,6 +1428,7 @@ Simulation { index: StatePartIndex(21), ty: UInt<8>, }, + maybe_changed: true, state: 0x07, last_state: 0x07, }, @@ -1416,6 +1438,7 @@ Simulation { index: StatePartIndex(22), ty: UInt<8>, }, + maybe_changed: true, state: 0x03, last_state: 0x03, }, @@ -1425,6 +1448,7 @@ Simulation { index: StatePartIndex(23), ty: UInt<8>, }, + maybe_changed: true, state: 0x01, last_state: 0x01, }, @@ -1434,6 +1458,7 @@ Simulation { index: StatePartIndex(24), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -1443,6 +1468,7 @@ Simulation { index: StatePartIndex(25), ty: UInt<8>, }, + maybe_changed: true, state: 0x80, last_state: 0x80, }, @@ -1452,6 +1478,7 @@ Simulation { index: StatePartIndex(26), ty: UInt<8>, }, + maybe_changed: true, state: 0xc0, last_state: 0xc0, }, @@ -1461,6 +1488,7 @@ Simulation { index: StatePartIndex(27), ty: UInt<8>, }, + maybe_changed: true, state: 0xe0, last_state: 0xe0, }, @@ -1470,6 +1498,7 @@ Simulation { index: StatePartIndex(28), ty: UInt<8>, }, + maybe_changed: true, state: 0xf0, last_state: 0xf0, }, @@ -1479,6 +1508,7 @@ Simulation { index: StatePartIndex(29), ty: UInt<8>, }, + maybe_changed: true, state: 0xf8, last_state: 0xf8, }, @@ -1488,6 +1518,7 @@ Simulation { index: StatePartIndex(30), ty: UInt<8>, }, + maybe_changed: true, state: 0xfc, last_state: 0xfc, }, @@ -1497,6 +1528,7 @@ Simulation { index: StatePartIndex(31), ty: UInt<8>, }, + maybe_changed: true, state: 0xfe, last_state: 0xe1, }, @@ -1506,6 +1538,7 @@ Simulation { index: StatePartIndex(32), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -1515,6 +1548,7 @@ Simulation { index: StatePartIndex(33), ty: UInt<8>, }, + maybe_changed: true, state: 0xff, last_state: 0xff, }, @@ -1524,6 +1558,7 @@ Simulation { index: StatePartIndex(34), ty: UInt<8>, }, + maybe_changed: true, state: 0x10, last_state: 0x0f, }, @@ -1533,6 +1568,7 @@ Simulation { index: StatePartIndex(35), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0xe1, }, @@ -1541,6 +1577,7 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1550,6 +1587,7 @@ Simulation { index: StatePartIndex(37), ty: UInt<8>, }, + maybe_changed: true, state: 0xff, last_state: 0xff, }, @@ -1559,6 +1597,7 @@ Simulation { index: StatePartIndex(38), ty: UInt<8>, }, + maybe_changed: true, state: 0x7f, last_state: 0x7f, }, @@ -1568,6 +1607,7 @@ Simulation { index: StatePartIndex(39), ty: UInt<8>, }, + maybe_changed: true, state: 0x3f, last_state: 0x3f, }, @@ -1577,6 +1617,7 @@ Simulation { index: StatePartIndex(40), ty: UInt<8>, }, + maybe_changed: true, state: 0x1f, last_state: 0x1f, }, @@ -1586,6 +1627,7 @@ Simulation { index: StatePartIndex(41), ty: UInt<8>, }, + maybe_changed: true, state: 0x0f, last_state: 0x0f, }, @@ -1595,6 +1637,7 @@ Simulation { index: StatePartIndex(42), ty: UInt<8>, }, + maybe_changed: true, state: 0x07, last_state: 0x07, }, @@ -1604,6 +1647,7 @@ Simulation { index: StatePartIndex(43), ty: UInt<8>, }, + maybe_changed: true, state: 0x03, last_state: 0x03, }, @@ -1613,6 +1657,7 @@ Simulation { index: StatePartIndex(44), ty: UInt<8>, }, + maybe_changed: true, state: 0x01, last_state: 0x01, }, @@ -1622,6 +1667,7 @@ Simulation { index: StatePartIndex(45), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -1631,6 +1677,7 @@ Simulation { index: StatePartIndex(46), ty: UInt<8>, }, + maybe_changed: true, state: 0x80, last_state: 0x80, }, @@ -1640,6 +1687,7 @@ Simulation { index: StatePartIndex(47), ty: UInt<8>, }, + maybe_changed: true, state: 0xc0, last_state: 0xc0, }, @@ -1649,6 +1697,7 @@ Simulation { index: StatePartIndex(48), ty: UInt<8>, }, + maybe_changed: true, state: 0xe0, last_state: 0xe0, }, @@ -1658,6 +1707,7 @@ Simulation { index: StatePartIndex(49), ty: UInt<8>, }, + maybe_changed: true, state: 0xf0, last_state: 0xf0, }, @@ -1667,6 +1717,7 @@ Simulation { index: StatePartIndex(50), ty: UInt<8>, }, + maybe_changed: true, state: 0xf8, last_state: 0xf8, }, @@ -1676,6 +1727,7 @@ Simulation { index: StatePartIndex(51), ty: UInt<8>, }, + maybe_changed: true, state: 0xfc, last_state: 0xfc, }, @@ -1685,6 +1737,7 @@ Simulation { index: StatePartIndex(52), ty: UInt<8>, }, + maybe_changed: true, state: 0xfe, last_state: 0xe1, }, diff --git a/crates/fayalite/tests/sim/expected/array_rw.vcd b/crates/fayalite/tests/sim/expected/array_rw.vcd index 8ede394..fefce5f 100644 --- a/crates/fayalite/tests/sim/expected/array_rw.vcd +++ b/crates/fayalite/tests/sim/expected/array_rw.vcd @@ -1,283 +1,283 @@ $timescale 1 ps $end $scope module array_rw $end $scope struct array_in $end -$var wire 8 ! \[0] $end -$var wire 8 " \[1] $end -$var wire 8 # \[2] $end -$var wire 8 $ \[3] $end -$var wire 8 % \[4] $end -$var wire 8 & \[5] $end -$var wire 8 ' \[6] $end -$var wire 8 ( \[7] $end -$var wire 8 ) \[8] $end -$var wire 8 * \[9] $end -$var wire 8 + \[10] $end -$var wire 8 , \[11] $end -$var wire 8 - \[12] $end -$var wire 8 . \[13] $end -$var wire 8 / \[14] $end -$var wire 8 0 \[15] $end +$var wire 8 Yvfu^ \[0] $end +$var wire 8 |Cs`W \[1] $end +$var wire 8 M!nsb \[2] $end +$var wire 8 59L{w \[3] $end +$var wire 8 o2+|F \[4] $end +$var wire 8 ikzV5 \[5] $end +$var wire 8 [E$Z* \[6] $end +$var wire 8 ?"~01 \[7] $end +$var wire 8 /kghT \[8] $end +$var wire 8 +}(9) \[9] $end +$var wire 8 iMP}= \[10] $end +$var wire 8 2M0tL \[11] $end +$var wire 8 :AjkA \[12] $end +$var wire 8 VM_:8 \[13] $end +$var wire 8 UveL2 \[14] $end +$var wire 8 A)9Z6 \[15] $end $upscope $end $scope struct array_out $end -$var wire 8 1 \[0] $end -$var wire 8 2 \[1] $end -$var wire 8 3 \[2] $end -$var wire 8 4 \[3] $end -$var wire 8 5 \[4] $end -$var wire 8 6 \[5] $end -$var wire 8 7 \[6] $end -$var wire 8 8 \[7] $end -$var wire 8 9 \[8] $end -$var wire 8 : \[9] $end -$var wire 8 ; \[10] $end -$var wire 8 < \[11] $end -$var wire 8 = \[12] $end -$var wire 8 > \[13] $end -$var wire 8 ? \[14] $end -$var wire 8 @ \[15] $end +$var wire 8 2zdj1 \[0] $end +$var wire 8 =;m_[ \[1] $end +$var wire 8 @9Hd \[2] $end +$var wire 8 C:="| \[3] $end +$var wire 8 IDk7# \[4] $end +$var wire 8 i]E1i \[5] $end +$var wire 8 tK,M] \[6] $end +$var wire 8 tGp!\ \[7] $end +$var wire 8 ."qjK \[8] $end +$var wire 8 AUO:R \[9] $end +$var wire 8 'kx`n \[10] $end +$var wire 8 U&(K\ \[11] $end +$var wire 8 q0H<( \[14] $end +$var wire 8 ARhXJ \[15] $end $upscope $end -$var wire 8 A read_index $end -$var wire 8 B read_data $end -$var wire 8 C write_index $end -$var wire 8 D write_data $end -$var wire 1 E write_en $end +$var wire 8 -n:7@ read_index $end +$var wire 8 >h<=Z read_data $end +$var wire 8 [xld3 write_index $end +$var wire 8 J+DYh write_data $end +$var wire 1 z,@WW write_en $end $scope struct array_wire $end -$var wire 8 F \[0] $end -$var wire 8 G \[1] $end -$var wire 8 H \[2] $end -$var wire 8 I \[3] $end -$var wire 8 J \[4] $end -$var wire 8 K \[5] $end -$var wire 8 L \[6] $end -$var wire 8 M \[7] $end -$var wire 8 N \[8] $end -$var wire 8 O \[9] $end -$var wire 8 P \[10] $end -$var wire 8 Q \[11] $end -$var wire 8 R \[12] $end -$var wire 8 S \[13] $end -$var wire 8 T \[14] $end -$var wire 8 U \[15] $end +$var wire 8 B{KJS \[0] $end +$var wire 8 V'K*& \[1] $end +$var wire 8 4zI$O \[2] $end +$var wire 8 %TTk[ \[3] $end +$var wire 8 IgSeY \[4] $end +$var wire 8 &&1T" \[5] $end +$var wire 8 5)-l\ \[6] $end +$var wire 8 0RsLb \[7] $end +$var wire 8 T>:}D \[8] $end +$var wire 8 DPpZ* \[9] $end +$var wire 8 %E(nf \[10] $end +$var wire 8 2'pba \[11] $end +$var wire 8 e/c1: \[12] $end +$var wire 8 ;w.C7 \[13] $end +$var wire 8 fwdfu \[14] $end +$var wire 8 *R\vx \[15] $end $upscope $end $upscope $end $enddefinitions $end $dumpvars -b11111111 ! -b1111111 " -b111111 # -b11111 $ -b1111 % -b111 & -b11 ' -b1 ( -b0 ) -b10000000 * -b11000000 + -b11100000 , -b11110000 - -b11111000 . -b11111100 / -b11111110 0 -b11111111 1 -b1111111 2 -b111111 3 -b11111 4 -b1111 5 -b111 6 -b11 7 -b1 8 -b0 9 -b10000000 : -b11000000 ; -b11100000 < -b11110000 = -b11111000 > -b11111100 ? -b11111110 @ -b0 A -b11111111 B -b0 C -b0 D -0E -b11111111 F -b1111111 G -b111111 H -b11111 I -b1111 J -b111 K -b11 L -b1 M -b0 N -b10000000 O -b11000000 P -b11100000 Q -b11110000 R -b11111000 S -b11111100 T -b11111110 U +b11111111 Yvfu^ +b1111111 |Cs`W +b111111 M!nsb +b11111 59L{w +b1111 o2+|F +b111 ikzV5 +b11 [E$Z* +b1 ?"~01 +b0 /kghT +b10000000 +}(9) +b11000000 iMP}= +b11100000 2M0tL +b11110000 :AjkA +b11111000 VM_:8 +b11111100 UveL2 +b11111110 A)9Z6 +b11111111 2zdj1 +b1111111 =;m_[ +b111111 @9Hd +b11111 C:="| +b1111 IDk7# +b111 i]E1i +b11 tK,M] +b1 tGp!\ +b0 ."qjK +b10000000 AUO:R +b11000000 'kx`n +b11100000 U&(K\ +b11110000 q0H<( +b11111110 ARhXJ +b0 -n:7@ +b11111111 >h<=Z +b0 [xld3 +b0 J+DYh +0z,@WW +b11111111 B{KJS +b1111111 V'K*& +b111111 4zI$O +b11111 %TTk[ +b1111 IgSeY +b111 &&1T" +b11 5)-l\ +b1 0RsLb +b0 T>:}D +b10000000 DPpZ* +b11000000 %E(nf +b11100000 2'pba +b11110000 e/c1: +b11111000 ;w.C7 +b11111100 fwdfu +b11111110 *R\vx $end #1000000 -b1 A -b1111111 B +b1 -n:7@ +b1111111 >h<=Z #2000000 -b10 A -b111111 B +b10 -n:7@ +b111111 >h<=Z #3000000 -b11 A -b11111 B +b11 -n:7@ +b11111 >h<=Z #4000000 -b100 A -b1111 B +b100 -n:7@ +b1111 >h<=Z #5000000 -b101 A -b111 B +b101 -n:7@ +b111 >h<=Z #6000000 -b110 A -b11 B +b110 -n:7@ +b11 >h<=Z #7000000 -b111 A -b1 B +b111 -n:7@ +b1 >h<=Z #8000000 -b1000 A -b0 B +b1000 -n:7@ +b0 >h<=Z #9000000 -b1001 A -b10000000 B +b1001 -n:7@ +b10000000 >h<=Z #10000000 -b1010 A -b11000000 B +b1010 -n:7@ +b11000000 >h<=Z #11000000 -b1011 A -b11100000 B +b1011 -n:7@ +b11100000 >h<=Z #12000000 -b1100 A -b11110000 B +b1100 -n:7@ +b11110000 >h<=Z #13000000 -b1101 A -b11111000 B +b1101 -n:7@ +b11111000 >h<=Z #14000000 -b1110 A -b11111100 B +b1110 -n:7@ +b11111100 >h<=Z #15000000 -b1111 A -b11111110 B +b1111 -n:7@ +b11111110 >h<=Z #16000000 -b10000 A -b0 B +b10000 -n:7@ +b0 >h<=Z #17000000 -b0 1 -b0 A -1E -b0 F +b0 2zdj1 +b0 -n:7@ +1z,@WW +b0 B{KJS #18000000 -b11111111 1 -b1 2 -b11111111 B -b1 C -b1 D -b11111111 F -b1 G +b11111111 2zdj1 +b1 =;m_[ +b11111111 >h<=Z +b1 [xld3 +b1 J+DYh +b11111111 B{KJS +b1 V'K*& #19000000 -b1111111 2 -b100 3 -b10 C -b100 D -b1111111 G -b100 H +b1111111 =;m_[ +b100 @9Hd +b10 [xld3 +b100 J+DYh +b1111111 V'K*& +b100 4zI$O #20000000 -b111111 3 -b1001 4 -b11 C -b1001 D -b111111 H -b1001 I +b111111 @9Hd +b1001 C:="| +b11 [xld3 +b1001 J+DYh +b111111 4zI$O +b1001 %TTk[ #21000000 -b11111 4 -b10000 5 -b100 C -b10000 D -b11111 I -b10000 J +b11111 C:="| +b10000 IDk7# +b100 [xld3 +b10000 J+DYh +b11111 %TTk[ +b10000 IgSeY #22000000 -b1111 5 -b11001 6 -b101 C -b11001 D -b1111 J -b11001 K +b1111 IDk7# +b11001 i]E1i +b101 [xld3 +b11001 J+DYh +b1111 IgSeY +b11001 &&1T" #23000000 -b111 6 -b100100 7 -b110 C -b100100 D -b111 K -b100100 L +b111 i]E1i +b100100 tK,M] +b110 [xld3 +b100100 J+DYh +b111 &&1T" +b100100 5)-l\ #24000000 -b11 7 -b110001 8 -b111 C -b110001 D -b11 L -b110001 M +b11 tK,M] +b110001 tGp!\ +b111 [xld3 +b110001 J+DYh +b11 5)-l\ +b110001 0RsLb #25000000 -b1 8 -b1000000 9 -b1000 C -b1000000 D -b1 M -b1000000 N +b1 tGp!\ +b1000000 ."qjK +b1000 [xld3 +b1000000 J+DYh +b1 0RsLb +b1000000 T>:}D #26000000 -b0 9 -b1010001 : -b1001 C -b1010001 D -b0 N -b1010001 O +b0 ."qjK +b1010001 AUO:R +b1001 [xld3 +b1010001 J+DYh +b0 T>:}D +b1010001 DPpZ* #27000000 -b10000000 : -b1100100 ; -b1010 C -b1100100 D -b10000000 O -b1100100 P +b10000000 AUO:R +b1100100 'kx`n +b1010 [xld3 +b1100100 J+DYh +b10000000 DPpZ* +b1100100 %E(nf #28000000 -b11000000 ; -b1111001 < -b1011 C -b1111001 D -b11000000 P -b1111001 Q +b11000000 'kx`n +b1111001 U&(K\ +b1011 [xld3 +b1111001 J+DYh +b11000000 %E(nf +b1111001 2'pba #29000000 -b11100000 < -b10010000 = -b1100 C -b10010000 D -b11100000 Q -b10010000 R +b11100000 U&(K\ +b10010000 q -b1101 C -b10101001 D -b11110000 R -b10101001 S +b11110000 q -b11000100 ? -b1110 C -b11000100 D -b11111000 S -b11000100 T +b11111000 zvj)] +b11000100 >0H<( +b1110 [xld3 +b11000100 J+DYh +b11111000 ;w.C7 +b11000100 fwdfu #32000000 -b11111100 ? -b11100001 @ -b1111 C -b11100001 D -b11111100 T -b11100001 U +b11111100 >0H<( +b11100001 ARhXJ +b1111 [xld3 +b11100001 J+DYh +b11111100 fwdfu +b11100001 *R\vx #33000000 -b11111110 @ -b10000 C -b0 D -b11111110 U +b11111110 ARhXJ +b10000 [xld3 +b0 J+DYh +b11111110 *R\vx #34000000 diff --git a/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt b/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt index d470792..74c03a4 100644 --- a/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt +++ b/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt @@ -155,6 +155,7 @@ Simulation { kind: BigBool { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x1, last_state: 0x0, }, @@ -163,6 +164,7 @@ Simulation { kind: BigBool { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, diff --git a/crates/fayalite/tests/sim/expected/conditional_assignment_last.vcd b/crates/fayalite/tests/sim/expected/conditional_assignment_last.vcd index dd9a85a..96a9fba 100644 --- a/crates/fayalite/tests/sim/expected/conditional_assignment_last.vcd +++ b/crates/fayalite/tests/sim/expected/conditional_assignment_last.vcd @@ -1,14 +1,14 @@ $timescale 1 ps $end $scope module conditional_assignment_last $end -$var wire 1 ! i $end -$var wire 1 " w $end +$var wire 1 xt~(W i $end +$var wire 1 6:7im w $end $upscope $end $enddefinitions $end $dumpvars -0! -1" +0xt~(W +16:7im $end #1000000 -1! -0" +1xt~(W +06:7im #2000000 diff --git a/crates/fayalite/tests/sim/expected/connect_const.txt b/crates/fayalite/tests/sim/expected/connect_const.txt index 56ea4ad..8193fc5 100644 --- a/crates/fayalite/tests/sim/expected/connect_const.txt +++ b/crates/fayalite/tests/sim/expected/connect_const.txt @@ -124,6 +124,7 @@ Simulation { index: StatePartIndex(0), ty: UInt<8>, }, + maybe_changed: true, state: 0x05, last_state: 0x05, }, diff --git a/crates/fayalite/tests/sim/expected/connect_const_reset.txt b/crates/fayalite/tests/sim/expected/connect_const_reset.txt index 6b5814a..5a64923 100644 --- a/crates/fayalite/tests/sim/expected/connect_const_reset.txt +++ b/crates/fayalite/tests/sim/expected/connect_const_reset.txt @@ -175,6 +175,7 @@ Simulation { kind: BigAsyncReset { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -183,6 +184,7 @@ Simulation { kind: BigBool { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, diff --git a/crates/fayalite/tests/sim/expected/connect_const_reset.vcd b/crates/fayalite/tests/sim/expected/connect_const_reset.vcd index 50b427c..f6e228a 100644 --- a/crates/fayalite/tests/sim/expected/connect_const_reset.vcd +++ b/crates/fayalite/tests/sim/expected/connect_const_reset.vcd @@ -1,11 +1,11 @@ $timescale 1 ps $end $scope module connect_const_reset $end -$var wire 1 ! reset_out $end -$var wire 1 " bit_out $end +$var wire 1 8ke|= reset_out $end +$var wire 1 {"c@= bit_out $end $upscope $end $enddefinitions $end $dumpvars -1! -1" +18ke|= +1{"c@= $end #1000000 diff --git a/crates/fayalite/tests/sim/expected/counter_async.txt b/crates/fayalite/tests/sim/expected/counter_async.txt index 86bde88..20d27ac 100644 --- a/crates/fayalite/tests/sim/expected/counter_async.txt +++ b/crates/fayalite/tests/sim/expected/counter_async.txt @@ -123,58 +123,62 @@ Simulation { dest: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, src: StatePartIndex(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> }, }, + 8: Copy { + dest: StatePartIndex(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, + src: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, + }, // at: module-XXXXXXXXXX.rs:1:1 - 8: Add { + 9: Add { dest: StatePartIndex(8), // (0x4) SlotDebugData { name: "", ty: UInt<5> }, lhs: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, rhs: StatePartIndex(7), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, }, - 9: CastToUInt { + 10: CastToUInt { dest: StatePartIndex(9), // (0x4) SlotDebugData { name: "", ty: UInt<4> }, src: StatePartIndex(8), // (0x4) SlotDebugData { name: "", ty: UInt<5> }, dest_width: 4, }, // at: module-XXXXXXXXXX.rs:4:1 - 10: Copy { + 11: Copy { dest: StatePartIndex(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, src: StatePartIndex(9), // (0x4) SlotDebugData { name: "", ty: UInt<4> }, }, // at: module-XXXXXXXXXX.rs:6:1 - 11: Copy { + 12: Copy { dest: StatePartIndex(2), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> }, src: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, }, // at: module-XXXXXXXXXX.rs:3:1 - 12: BranchIfSmallNonZero { - target: 16, + 13: BranchIfSmallNonZero { + target: 17, value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 13: BranchIfSmallZero { - target: 17, + 14: BranchIfSmallZero { + target: 18, value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 14: Copy { + 15: Copy { dest: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, src: StatePartIndex(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, }, - 15: Branch { - target: 17, + 16: Branch { + target: 18, }, - 16: Copy { + 17: Copy { dest: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, src: StatePartIndex(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> }, }, - 17: XorSmallImmediate { + 18: XorSmallImmediate { dest: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, rhs: 0x1, }, // at: module-XXXXXXXXXX.rs:1:1 - 18: Return, + 19: Return, ], .. }, - pc: 18, + pc: 19, memory_write_log: [], memories: StatePart { value: [], @@ -328,6 +332,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x1, last_state: 0x0, }, @@ -336,6 +341,7 @@ Simulation { kind: BigAsyncReset { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -345,6 +351,7 @@ Simulation { index: StatePartIndex(2), ty: UInt<4>, }, + maybe_changed: true, state: 0x3, last_state: 0x2, }, @@ -354,6 +361,7 @@ Simulation { index: StatePartIndex(3), ty: UInt<4>, }, + maybe_changed: true, state: 0x3, last_state: 0x2, }, diff --git a/crates/fayalite/tests/sim/expected/counter_async.vcd b/crates/fayalite/tests/sim/expected/counter_async.vcd index dab690f..d40f10f 100644 --- a/crates/fayalite/tests/sim/expected/counter_async.vcd +++ b/crates/fayalite/tests/sim/expected/counter_async.vcd @@ -1,217 +1,217 @@ $timescale 1 ps $end $scope module counter $end $scope struct cd $end -$var wire 1 ! clk $end -$var wire 1 " rst $end +$var wire 1 `[J;" clk $end +$var wire 1 4pZx7 rst $end $upscope $end -$var wire 4 # count $end -$var reg 4 $ count_reg $end +$var wire 4 rPs;{ count $end +$var reg 4 6_+(g count_reg $end $upscope $end $enddefinitions $end $dumpvars -0! -0" -b0 # -b0 $ +0`[J;" +04pZx7 +b0 rPs;{ +b0 6_+(g $end #500000 -1" -b11 # -b11 $ +14pZx7 +b11 rPs;{ +b11 6_+(g #1000000 -1! +1`[J;" #1500000 -0" +04pZx7 #2000000 -0! +0`[J;" #3000000 -1! -b100 # -b100 $ +1`[J;" +b100 rPs;{ +b100 6_+(g #4000000 -0! +0`[J;" #5000000 -1! -b101 # -b101 $ +1`[J;" +b101 rPs;{ +b101 6_+(g #6000000 -0! +0`[J;" #7000000 -1! -b110 # -b110 $ +1`[J;" +b110 rPs;{ +b110 6_+(g #8000000 -0! +0`[J;" #9000000 -1! -b111 # -b111 $ +1`[J;" +b111 rPs;{ +b111 6_+(g #10000000 -0! +0`[J;" #11000000 -1! -b1000 # -b1000 $ +1`[J;" +b1000 rPs;{ +b1000 6_+(g #12000000 -0! +0`[J;" #13000000 -1! -b1001 # -b1001 $ +1`[J;" +b1001 rPs;{ +b1001 6_+(g #14000000 -0! +0`[J;" #15000000 -1! -b1010 # -b1010 $ +1`[J;" +b1010 rPs;{ +b1010 6_+(g #16000000 -0! +0`[J;" #17000000 -1! -b1011 # -b1011 $ +1`[J;" +b1011 rPs;{ +b1011 6_+(g #18000000 -0! +0`[J;" #19000000 -1! -b1100 # -b1100 $ +1`[J;" +b1100 rPs;{ +b1100 6_+(g #20000000 -0! +0`[J;" #21000000 -1! -b1101 # -b1101 $ +1`[J;" +b1101 rPs;{ +b1101 6_+(g #22000000 -0! +0`[J;" #23000000 -1! -b1110 # -b1110 $ +1`[J;" +b1110 rPs;{ +b1110 6_+(g #24000000 -0! +0`[J;" #25000000 -1! -b1111 # -b1111 $ +1`[J;" +b1111 rPs;{ +b1111 6_+(g #26000000 -0! +0`[J;" #27000000 -1! -b0 # -b0 $ +1`[J;" +b0 rPs;{ +b0 6_+(g #28000000 -0! +0`[J;" #29000000 -1! -b1 # -b1 $ +1`[J;" +b1 rPs;{ +b1 6_+(g #30000000 -0! +0`[J;" #31000000 -1! -b10 # -b10 $ +1`[J;" +b10 rPs;{ +b10 6_+(g #32000000 -0! +0`[J;" #33000000 -1! -b11 # -b11 $ +1`[J;" +b11 rPs;{ +b11 6_+(g #34000000 -0! +0`[J;" #35000000 -1! -b100 # -b100 $ +1`[J;" +b100 rPs;{ +b100 6_+(g #36000000 -0! +0`[J;" #37000000 -1! -b101 # -b101 $ +1`[J;" +b101 rPs;{ +b101 6_+(g #38000000 -0! +0`[J;" #39000000 -1! -b110 # -b110 $ +1`[J;" +b110 rPs;{ +b110 6_+(g #40000000 -0! +0`[J;" #41000000 -1! -b111 # -b111 $ +1`[J;" +b111 rPs;{ +b111 6_+(g #42000000 -0! +0`[J;" #43000000 -1! -b1000 # -b1000 $ +1`[J;" +b1000 rPs;{ +b1000 6_+(g #44000000 -0! +0`[J;" #45000000 -1! -b1001 # -b1001 $ +1`[J;" +b1001 rPs;{ +b1001 6_+(g #46000000 -0! +0`[J;" #47000000 -1! -b1010 # -b1010 $ +1`[J;" +b1010 rPs;{ +b1010 6_+(g #48000000 -0! +0`[J;" #49000000 -1! -b1011 # -b1011 $ +1`[J;" +b1011 rPs;{ +b1011 6_+(g #50000000 -0! +0`[J;" #51000000 -1! -b1100 # -b1100 $ +1`[J;" +b1100 rPs;{ +b1100 6_+(g #52000000 -0! +0`[J;" #53000000 -1! -b1101 # -b1101 $ +1`[J;" +b1101 rPs;{ +b1101 6_+(g #54000000 -0! +0`[J;" #55000000 -1! -b1110 # -b1110 $ +1`[J;" +b1110 rPs;{ +b1110 6_+(g #56000000 -0! +0`[J;" #57000000 -1! -b1111 # -b1111 $ +1`[J;" +b1111 rPs;{ +b1111 6_+(g #58000000 -0! +0`[J;" #59000000 -1! -b0 # -b0 $ +1`[J;" +b0 rPs;{ +b0 6_+(g #60000000 -0! +0`[J;" #61000000 -1! -b1 # -b1 $ +1`[J;" +b1 rPs;{ +b1 6_+(g #62000000 -0! +0`[J;" #63000000 -1! -b10 # -b10 $ +1`[J;" +b10 rPs;{ +b10 6_+(g #64000000 -0! +0`[J;" #65000000 -1! -b11 # -b11 $ +1`[J;" +b11 rPs;{ +b11 6_+(g #66000000 diff --git a/crates/fayalite/tests/sim/expected/counter_sync.txt b/crates/fayalite/tests/sim/expected/counter_sync.txt index 0a7517e..baa08e7 100644 --- a/crates/fayalite/tests/sim/expected/counter_sync.txt +++ b/crates/fayalite/tests/sim/expected/counter_sync.txt @@ -102,61 +102,65 @@ Simulation { src: StatePartIndex(7), // (0x4) SlotDebugData { name: "", ty: UInt<5> }, dest_width: 4, }, - // at: module-XXXXXXXXXX.rs:4:1 - 4: Copy { - dest: StatePartIndex(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, - src: StatePartIndex(8), // (0x4) SlotDebugData { name: "", ty: UInt<4> }, - }, // at: module-XXXXXXXXXX.rs:3:1 - 5: IsNonZeroDestIsSmall { + 4: IsNonZeroDestIsSmall { dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: SyncReset }, }, - 6: IsNonZeroDestIsSmall { + 5: IsNonZeroDestIsSmall { dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock }, }, - 7: AndSmall { + 6: AndSmall { dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, rhs: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, + 7: Copy { + dest: StatePartIndex(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, + src: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, + }, + // at: module-XXXXXXXXXX.rs:4:1 + 8: Copy { + dest: StatePartIndex(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, + src: StatePartIndex(8), // (0x4) SlotDebugData { name: "", ty: UInt<4> }, + }, // at: module-XXXXXXXXXX.rs:1:1 - 8: Const { + 9: Const { dest: StatePartIndex(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> }, value: 0x3, }, // at: module-XXXXXXXXXX.rs:3:1 - 9: BranchIfSmallZero { - target: 14, + 10: BranchIfSmallZero { + target: 15, value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 10: BranchIfSmallNonZero { - target: 13, + 11: BranchIfSmallNonZero { + target: 14, value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 11: Copy { + 12: Copy { dest: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, src: StatePartIndex(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, }, - 12: Branch { - target: 14, + 13: Branch { + target: 15, }, - 13: Copy { + 14: Copy { dest: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, src: StatePartIndex(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> }, }, - 14: XorSmallImmediate { + 15: XorSmallImmediate { dest: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, rhs: 0x1, }, // at: module-XXXXXXXXXX.rs:1:1 - 15: Return, + 16: Return, ], .. }, - pc: 15, + pc: 16, memory_write_log: [], memories: StatePart { value: [], @@ -309,6 +313,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x1, last_state: 0x0, }, @@ -317,6 +322,7 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -326,6 +332,7 @@ Simulation { index: StatePartIndex(2), ty: UInt<4>, }, + maybe_changed: true, state: 0x3, last_state: 0x2, }, @@ -335,6 +342,7 @@ Simulation { index: StatePartIndex(3), ty: UInt<4>, }, + maybe_changed: true, state: 0x3, last_state: 0x2, }, diff --git a/crates/fayalite/tests/sim/expected/counter_sync.vcd b/crates/fayalite/tests/sim/expected/counter_sync.vcd index 9504a30..f6a8177 100644 --- a/crates/fayalite/tests/sim/expected/counter_sync.vcd +++ b/crates/fayalite/tests/sim/expected/counter_sync.vcd @@ -1,214 +1,214 @@ $timescale 1 ps $end $scope module counter $end $scope struct cd $end -$var wire 1 ! clk $end -$var wire 1 " rst $end +$var wire 1 `[J;" clk $end +$var wire 1 4pZx7 rst $end $upscope $end -$var wire 4 # count $end -$var reg 4 $ count_reg $end +$var wire 4 rPs;{ count $end +$var reg 4 6_+(g count_reg $end $upscope $end $enddefinitions $end $dumpvars -0! -1" -b0 # -b0 $ +0`[J;" +14pZx7 +b0 rPs;{ +b0 6_+(g $end #1000000 -1! -b11 # -b11 $ -0" +1`[J;" +b11 rPs;{ +b11 6_+(g +04pZx7 #2000000 -0! +0`[J;" #3000000 -1! -b100 # -b100 $ +1`[J;" +b100 rPs;{ +b100 6_+(g #4000000 -0! +0`[J;" #5000000 -1! -b101 # -b101 $ +1`[J;" +b101 rPs;{ +b101 6_+(g #6000000 -0! +0`[J;" #7000000 -1! -b110 # -b110 $ +1`[J;" +b110 rPs;{ +b110 6_+(g #8000000 -0! +0`[J;" #9000000 -1! -b111 # -b111 $ +1`[J;" +b111 rPs;{ +b111 6_+(g #10000000 -0! +0`[J;" #11000000 -1! -b1000 # -b1000 $ +1`[J;" +b1000 rPs;{ +b1000 6_+(g #12000000 -0! +0`[J;" #13000000 -1! -b1001 # -b1001 $ +1`[J;" +b1001 rPs;{ +b1001 6_+(g #14000000 -0! +0`[J;" #15000000 -1! -b1010 # -b1010 $ +1`[J;" +b1010 rPs;{ +b1010 6_+(g #16000000 -0! +0`[J;" #17000000 -1! -b1011 # -b1011 $ +1`[J;" +b1011 rPs;{ +b1011 6_+(g #18000000 -0! +0`[J;" #19000000 -1! -b1100 # -b1100 $ +1`[J;" +b1100 rPs;{ +b1100 6_+(g #20000000 -0! +0`[J;" #21000000 -1! -b1101 # -b1101 $ +1`[J;" +b1101 rPs;{ +b1101 6_+(g #22000000 -0! +0`[J;" #23000000 -1! -b1110 # -b1110 $ +1`[J;" +b1110 rPs;{ +b1110 6_+(g #24000000 -0! +0`[J;" #25000000 -1! -b1111 # -b1111 $ +1`[J;" +b1111 rPs;{ +b1111 6_+(g #26000000 -0! +0`[J;" #27000000 -1! -b0 # -b0 $ +1`[J;" +b0 rPs;{ +b0 6_+(g #28000000 -0! +0`[J;" #29000000 -1! -b1 # -b1 $ +1`[J;" +b1 rPs;{ +b1 6_+(g #30000000 -0! +0`[J;" #31000000 -1! -b10 # -b10 $ +1`[J;" +b10 rPs;{ +b10 6_+(g #32000000 -0! +0`[J;" #33000000 -1! -b11 # -b11 $ +1`[J;" +b11 rPs;{ +b11 6_+(g #34000000 -0! +0`[J;" #35000000 -1! -b100 # -b100 $ +1`[J;" +b100 rPs;{ +b100 6_+(g #36000000 -0! +0`[J;" #37000000 -1! -b101 # -b101 $ +1`[J;" +b101 rPs;{ +b101 6_+(g #38000000 -0! +0`[J;" #39000000 -1! -b110 # -b110 $ +1`[J;" +b110 rPs;{ +b110 6_+(g #40000000 -0! +0`[J;" #41000000 -1! -b111 # -b111 $ +1`[J;" +b111 rPs;{ +b111 6_+(g #42000000 -0! +0`[J;" #43000000 -1! -b1000 # -b1000 $ +1`[J;" +b1000 rPs;{ +b1000 6_+(g #44000000 -0! +0`[J;" #45000000 -1! -b1001 # -b1001 $ +1`[J;" +b1001 rPs;{ +b1001 6_+(g #46000000 -0! +0`[J;" #47000000 -1! -b1010 # -b1010 $ +1`[J;" +b1010 rPs;{ +b1010 6_+(g #48000000 -0! +0`[J;" #49000000 -1! -b1011 # -b1011 $ +1`[J;" +b1011 rPs;{ +b1011 6_+(g #50000000 -0! +0`[J;" #51000000 -1! -b1100 # -b1100 $ +1`[J;" +b1100 rPs;{ +b1100 6_+(g #52000000 -0! +0`[J;" #53000000 -1! -b1101 # -b1101 $ +1`[J;" +b1101 rPs;{ +b1101 6_+(g #54000000 -0! +0`[J;" #55000000 -1! -b1110 # -b1110 $ +1`[J;" +b1110 rPs;{ +b1110 6_+(g #56000000 -0! +0`[J;" #57000000 -1! -b1111 # -b1111 $ +1`[J;" +b1111 rPs;{ +b1111 6_+(g #58000000 -0! +0`[J;" #59000000 -1! -b0 # -b0 $ +1`[J;" +b0 rPs;{ +b0 6_+(g #60000000 -0! +0`[J;" #61000000 -1! -b1 # -b1 $ +1`[J;" +b1 rPs;{ +b1 6_+(g #62000000 -0! +0`[J;" #63000000 -1! -b10 # -b10 $ +1`[J;" +b10 rPs;{ +b10 6_+(g #64000000 -0! +0`[J;" #65000000 -1! -b11 # -b11 $ +1`[J;" +b11 rPs;{ +b11 6_+(g #66000000 diff --git a/crates/fayalite/tests/sim/expected/duplicate_names.txt b/crates/fayalite/tests/sim/expected/duplicate_names.txt index 64bbbe6..76338e8 100644 --- a/crates/fayalite/tests/sim/expected/duplicate_names.txt +++ b/crates/fayalite/tests/sim/expected/duplicate_names.txt @@ -137,6 +137,7 @@ Simulation { index: StatePartIndex(0), ty: UInt<8>, }, + maybe_changed: true, state: 0x05, last_state: 0x05, }, @@ -146,6 +147,7 @@ Simulation { index: StatePartIndex(2), ty: UInt<8>, }, + maybe_changed: true, state: 0x06, last_state: 0x06, }, diff --git a/crates/fayalite/tests/sim/expected/duplicate_names.vcd b/crates/fayalite/tests/sim/expected/duplicate_names.vcd index 1e9f6c6..238c074 100644 --- a/crates/fayalite/tests/sim/expected/duplicate_names.vcd +++ b/crates/fayalite/tests/sim/expected/duplicate_names.vcd @@ -1,11 +1,11 @@ $timescale 1 ps $end $scope module duplicate_names $end -$var wire 8 ! w $end -$var wire 8 " w_2 $end +$var wire 8 7[_7. w $end +$var wire 8 7[_7." w_2 $end $upscope $end $enddefinitions $end $dumpvars -b101 ! -b110 " +b101 7[_7. +b110 7[_7." $end #1000000 diff --git a/crates/fayalite/tests/sim/expected/enum_with_simple_body.txt b/crates/fayalite/tests/sim/expected/enum_with_simple_body.txt new file mode 100644 index 0000000..6b5af1c --- /dev/null +++ b/crates/fayalite/tests/sim/expected/enum_with_simple_body.txt @@ -0,0 +1,749 @@ +Simulation { + state: State { + insns: Insns { + state_layout: StateLayout { + ty: TypeLayout { + small_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + A, + B, + C, + }, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 33, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::which_in", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::data_in", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::which_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::data_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::enum_out", + ty: Enum { + A(UInt<8>), + B(UInt<8>), + C(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<10>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<2>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<10>, + }, + SlotDebugData { + name: "", + ty: UInt<10>, + }, + SlotDebugData { + name: "", + ty: UInt<10>, + }, + SlotDebugData { + name: "", + ty: Enum { + A(UInt<8>), + B(UInt<8>), + C(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<2>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<10>, + }, + SlotDebugData { + name: "", + ty: UInt<10>, + }, + SlotDebugData { + name: "", + ty: UInt<10>, + }, + SlotDebugData { + name: "", + ty: Enum { + A(UInt<8>), + B(UInt<8>), + C(UInt<8>), + }, + }, + SlotDebugData { + name: ".0", + ty: UInt<2>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<10>, + }, + SlotDebugData { + name: "", + ty: UInt<10>, + }, + SlotDebugData { + name: "", + ty: UInt<10>, + }, + SlotDebugData { + name: "", + ty: Enum { + A(UInt<8>), + B(UInt<8>), + C(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + insns: [ + // at: module-XXXXXXXXXX.rs:1:1 + 0: Const { + dest: StatePartIndex(32), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x2, + }, + 1: Const { + dest: StatePartIndex(27), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + value: 0x2, + }, + 2: Copy { + dest: StatePartIndex(25), // (0x2) SlotDebugData { name: ".0", ty: UInt<2> }, + src: StatePartIndex(27), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + 3: Copy { + dest: StatePartIndex(26), // (0xe1) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(1), // (0xe1) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::data_in", ty: UInt<8> }, + }, + 4: Shl { + dest: StatePartIndex(28), // (0x384) SlotDebugData { name: "", ty: UInt<10> }, + lhs: StatePartIndex(26), // (0xe1) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 2, + }, + 5: Or { + dest: StatePartIndex(29), // (0x386) SlotDebugData { name: "", ty: UInt<10> }, + lhs: StatePartIndex(25), // (0x2) SlotDebugData { name: ".0", ty: UInt<2> }, + rhs: StatePartIndex(28), // (0x384) SlotDebugData { name: "", ty: UInt<10> }, + }, + 6: CastToUInt { + dest: StatePartIndex(30), // (0x386) SlotDebugData { name: "", ty: UInt<10> }, + src: StatePartIndex(29), // (0x386) SlotDebugData { name: "", ty: UInt<10> }, + dest_width: 10, + }, + 7: Copy { + dest: StatePartIndex(31), // (0x386) SlotDebugData { name: "", ty: Enum {A(UInt<8>), B(UInt<8>), C(UInt<8>)} }, + src: StatePartIndex(30), // (0x386) SlotDebugData { name: "", ty: UInt<10> }, + }, + 8: Const { + dest: StatePartIndex(20), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + value: 0x1, + }, + 9: Copy { + dest: StatePartIndex(18), // (0x1) SlotDebugData { name: ".0", ty: UInt<2> }, + src: StatePartIndex(20), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + }, + 10: Copy { + dest: StatePartIndex(19), // (0xe1) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(1), // (0xe1) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::data_in", ty: UInt<8> }, + }, + 11: Shl { + dest: StatePartIndex(21), // (0x384) SlotDebugData { name: "", ty: UInt<10> }, + lhs: StatePartIndex(19), // (0xe1) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 2, + }, + 12: Or { + dest: StatePartIndex(22), // (0x385) SlotDebugData { name: "", ty: UInt<10> }, + lhs: StatePartIndex(18), // (0x1) SlotDebugData { name: ".0", ty: UInt<2> }, + rhs: StatePartIndex(21), // (0x384) SlotDebugData { name: "", ty: UInt<10> }, + }, + 13: CastToUInt { + dest: StatePartIndex(23), // (0x385) SlotDebugData { name: "", ty: UInt<10> }, + src: StatePartIndex(22), // (0x385) SlotDebugData { name: "", ty: UInt<10> }, + dest_width: 10, + }, + 14: Copy { + dest: StatePartIndex(24), // (0x385) SlotDebugData { name: "", ty: Enum {A(UInt<8>), B(UInt<8>), C(UInt<8>)} }, + src: StatePartIndex(23), // (0x385) SlotDebugData { name: "", ty: UInt<10> }, + }, + 15: Const { + dest: StatePartIndex(16), // (0x1) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x1, + }, + 16: CmpEq { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(0), // (0x2) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::which_in", ty: UInt<8> }, + rhs: StatePartIndex(16), // (0x1) SlotDebugData { name: "", ty: UInt<8> }, + }, + 17: Const { + dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + value: 0x0, + }, + 18: Copy { + dest: StatePartIndex(9), // (0x0) SlotDebugData { name: ".0", ty: UInt<2> }, + src: StatePartIndex(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + 19: Copy { + dest: StatePartIndex(10), // (0xe1) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(1), // (0xe1) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::data_in", ty: UInt<8> }, + }, + 20: Shl { + dest: StatePartIndex(12), // (0x384) SlotDebugData { name: "", ty: UInt<10> }, + lhs: StatePartIndex(10), // (0xe1) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 2, + }, + 21: Or { + dest: StatePartIndex(13), // (0x384) SlotDebugData { name: "", ty: UInt<10> }, + lhs: StatePartIndex(9), // (0x0) SlotDebugData { name: ".0", ty: UInt<2> }, + rhs: StatePartIndex(12), // (0x384) SlotDebugData { name: "", ty: UInt<10> }, + }, + 22: CastToUInt { + dest: StatePartIndex(14), // (0x384) SlotDebugData { name: "", ty: UInt<10> }, + src: StatePartIndex(13), // (0x384) SlotDebugData { name: "", ty: UInt<10> }, + dest_width: 10, + }, + 23: Copy { + dest: StatePartIndex(15), // (0x384) SlotDebugData { name: "", ty: Enum {A(UInt<8>), B(UInt<8>), C(UInt<8>)} }, + src: StatePartIndex(14), // (0x384) SlotDebugData { name: "", ty: UInt<10> }, + }, + 24: Const { + dest: StatePartIndex(7), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + 25: CmpEq { + dest: StatePartIndex(8), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(0), // (0x2) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::which_in", ty: UInt<8> }, + rhs: StatePartIndex(7), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: module-XXXXXXXXXX.rs:7:1 + 26: BranchIfZero { + target: 28, + value: StatePartIndex(8), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:8:1 + 27: Copy { + dest: StatePartIndex(4), // (0x386) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::enum_out", ty: Enum {A(UInt<8>), B(UInt<8>), C(UInt<8>)} }, + src: StatePartIndex(15), // (0x384) SlotDebugData { name: "", ty: Enum {A(UInt<8>), B(UInt<8>), C(UInt<8>)} }, + }, + // at: module-XXXXXXXXXX.rs:7:1 + 28: BranchIfNonZero { + target: 33, + value: StatePartIndex(8), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:9:1 + 29: BranchIfZero { + target: 31, + value: StatePartIndex(17), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:10:1 + 30: Copy { + dest: StatePartIndex(4), // (0x386) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::enum_out", ty: Enum {A(UInt<8>), B(UInt<8>), C(UInt<8>)} }, + src: StatePartIndex(24), // (0x385) SlotDebugData { name: "", ty: Enum {A(UInt<8>), B(UInt<8>), C(UInt<8>)} }, + }, + // at: module-XXXXXXXXXX.rs:9:1 + 31: BranchIfNonZero { + target: 33, + value: StatePartIndex(17), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:11:1 + 32: Copy { + dest: StatePartIndex(4), // (0x386) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::enum_out", ty: Enum {A(UInt<8>), B(UInt<8>), C(UInt<8>)} }, + src: StatePartIndex(31), // (0x386) SlotDebugData { name: "", ty: Enum {A(UInt<8>), B(UInt<8>), C(UInt<8>)} }, + }, + // at: module-XXXXXXXXXX.rs:1:1 + 33: Copy { + dest: StatePartIndex(5), // (0x386) SlotDebugData { name: "", ty: UInt<10> }, + src: StatePartIndex(4), // (0x386) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::enum_out", ty: Enum {A(UInt<8>), B(UInt<8>), C(UInt<8>)} }, + }, + 34: SliceInt { + dest: StatePartIndex(6), // (0xe1) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(5), // (0x386) SlotDebugData { name: "", ty: UInt<10> }, + start: 2, + len: 8, + }, + // at: module-XXXXXXXXXX.rs:6:1 + 35: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} }, + lhs: StatePartIndex(4), // (0x386) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::enum_out", ty: Enum {A(UInt<8>), B(UInt<8>), C(UInt<8>)} }, + rhs: 0x3, + }, + // at: module-XXXXXXXXXX.rs:12:1 + 36: BranchIfSmallNeImmediate { + target: 39, + lhs: StatePartIndex(0), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} }, + rhs: 0x0, + }, + // at: module-XXXXXXXXXX.rs:13:1 + 37: Copy { + dest: StatePartIndex(2), // (0x2) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::which_out", ty: UInt<8> }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: module-XXXXXXXXXX.rs:14:1 + 38: Copy { + dest: StatePartIndex(3), // (0xe1) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::data_out", ty: UInt<8> }, + src: StatePartIndex(6), // (0xe1) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: module-XXXXXXXXXX.rs:12:1 + 39: BranchIfSmallNeImmediate { + target: 42, + lhs: StatePartIndex(0), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} }, + rhs: 0x1, + }, + // at: module-XXXXXXXXXX.rs:15:1 + 40: Copy { + dest: StatePartIndex(2), // (0x2) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::which_out", ty: UInt<8> }, + src: StatePartIndex(16), // (0x1) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: module-XXXXXXXXXX.rs:16:1 + 41: Copy { + dest: StatePartIndex(3), // (0xe1) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::data_out", ty: UInt<8> }, + src: StatePartIndex(6), // (0xe1) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: module-XXXXXXXXXX.rs:12:1 + 42: BranchIfSmallNeImmediate { + target: 45, + lhs: StatePartIndex(0), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} }, + rhs: 0x2, + }, + // at: module-XXXXXXXXXX.rs:17:1 + 43: Copy { + dest: StatePartIndex(2), // (0x2) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::which_out", ty: UInt<8> }, + src: StatePartIndex(32), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: module-XXXXXXXXXX.rs:18:1 + 44: Copy { + dest: StatePartIndex(3), // (0xe1) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::data_out", ty: UInt<8> }, + src: StatePartIndex(6), // (0xe1) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: module-XXXXXXXXXX.rs:1:1 + 45: Return, + ], + .. + }, + pc: 45, + memory_write_log: [], + memories: StatePart { + value: [], + }, + small_slots: StatePart { + value: [ + 2, + ], + }, + big_slots: StatePart { + value: [ + 2, + 225, + 2 (modified), + 225 (modified), + 902, + 902, + 225, + 0, + 0, + 0, + 225, + 0, + 900, + 900, + 900, + 900, + 1, + 0, + 1, + 225, + 1, + 900, + 901, + 901, + 901, + 2, + 225, + 2, + 900, + 902, + 902, + 902, + 2, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::enum_with_simple_body, + instantiated: Module { + name: enum_with_simple_body, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::enum_with_simple_body, + instantiated: Module { + name: enum_with_simple_body, + .. + }, + }.which_in, + Instance { + name: ::enum_with_simple_body, + instantiated: Module { + name: enum_with_simple_body, + .. + }, + }.data_in, + Instance { + name: ::enum_with_simple_body, + instantiated: Module { + name: enum_with_simple_body, + .. + }, + }.which_out, + Instance { + name: ::enum_with_simple_body, + instantiated: Module { + name: enum_with_simple_body, + .. + }, + }.data_out, + Instance { + name: ::enum_with_simple_body, + instantiated: Module { + name: enum_with_simple_body, + .. + }, + }.enum_out, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::enum_with_simple_body, + instantiated: Module { + name: enum_with_simple_body, + .. + }, + }.data_in, + Instance { + name: ::enum_with_simple_body, + instantiated: Module { + name: enum_with_simple_body, + .. + }, + }.data_out, + Instance { + name: ::enum_with_simple_body, + instantiated: Module { + name: enum_with_simple_body, + .. + }, + }.enum_out, + Instance { + name: ::enum_with_simple_body, + instantiated: Module { + name: enum_with_simple_body, + .. + }, + }.which_in, + Instance { + name: ::enum_with_simple_body, + instantiated: Module { + name: enum_with_simple_body, + .. + }, + }.which_out, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "enum_with_simple_body", + children: [ + TraceModuleIO { + name: "which_in", + child: TraceUInt { + location: TraceScalarId(0), + name: "which_in", + ty: UInt<8>, + flow: Source, + }, + ty: UInt<8>, + flow: Source, + }, + TraceModuleIO { + name: "data_in", + child: TraceUInt { + location: TraceScalarId(1), + name: "data_in", + ty: UInt<8>, + flow: Source, + }, + ty: UInt<8>, + flow: Source, + }, + TraceModuleIO { + name: "which_out", + child: TraceUInt { + location: TraceScalarId(2), + name: "which_out", + ty: UInt<8>, + flow: Sink, + }, + ty: UInt<8>, + flow: Sink, + }, + TraceModuleIO { + name: "data_out", + child: TraceUInt { + location: TraceScalarId(3), + name: "data_out", + ty: UInt<8>, + flow: Sink, + }, + ty: UInt<8>, + flow: Sink, + }, + TraceModuleIO { + name: "enum_out", + child: TraceEnumWithFields { + name: "enum_out", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(4), + name: "$tag", + ty: Enum { + A(UInt<8>), + B(UInt<8>), + C(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(5), + name: "A", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(6), + name: "B", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(7), + name: "C", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + A(UInt<8>), + B(UInt<8>), + C(UInt<8>), + }, + flow: Sink, + }, + ty: Enum { + A(UInt<8>), + B(UInt<8>), + C(UInt<8>), + }, + flow: Sink, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigUInt { + index: StatePartIndex(0), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x02, + last_state: 0x02, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigUInt { + index: StatePartIndex(1), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0xe1, + last_state: 0xb4, + }, + SimTrace { + id: TraceScalarId(2), + kind: BigUInt { + index: StatePartIndex(2), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x02, + last_state: 0x02, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(3), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0xe1, + last_state: 0xb4, + }, + SimTrace { + id: TraceScalarId(4), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + A(UInt<8>), + B(UInt<8>), + C(UInt<8>), + }, + }, + maybe_changed: true, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(5), + kind: BigUInt { + index: StatePartIndex(6), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0xe1, + last_state: 0xb4, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(6), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0xe1, + last_state: 0xb4, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigUInt { + index: StatePartIndex(6), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0xe1, + last_state: 0xb4, + }, + ], + trace_memories: {}, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [], + event_queue: EventQueue(EventQueueData { + instant: 18 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/enum_with_simple_body.vcd b/crates/fayalite/tests/sim/expected/enum_with_simple_body.vcd new file mode 100644 index 0000000..dfe0dc1 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/enum_with_simple_body.vcd @@ -0,0 +1,133 @@ +$timescale 1 ps $end +$scope module enum_with_simple_body $end +$var wire 8 J&-ne which_in $end +$var wire 8 \7mo/ data_in $end +$var wire 8 ,`>ir which_out $end +$var wire 8 0_gMP data_out $end +$scope struct enum_out $end +$var string 1 kFH/w \$tag $end +$var wire 8 |EI_= A $end +$var wire 8 !pRd4 B $end +$var wire 8 &RAbd C $end +$upscope $end +$upscope $end +$enddefinitions $end +$dumpvars +b0 J&-ne +b0 \7mo/ +b0 ,`>ir +b0 0_gMP +sA\x20(0) kFH/w +b0 |EI_= +b0 !pRd4 +b0 &RAbd +$end +#1000000 +b101101 \7mo/ +b101101 0_gMP +b101101 |EI_= +b101101 !pRd4 +b101101 &RAbd +#2000000 +b1011010 \7mo/ +b1011010 0_gMP +b1011010 |EI_= +b1011010 !pRd4 +b1011010 &RAbd +#3000000 +b10000111 \7mo/ +b10000111 0_gMP +b10000111 |EI_= +b10000111 !pRd4 +b10000111 &RAbd +#4000000 +b10110100 \7mo/ +b10110100 0_gMP +b10110100 |EI_= +b10110100 !pRd4 +b10110100 &RAbd +#5000000 +b11100001 \7mo/ +b11100001 0_gMP +b11100001 |EI_= +b11100001 !pRd4 +b11100001 &RAbd +#6000000 +b1 J&-ne +b0 \7mo/ +b1 ,`>ir +b0 0_gMP +sB\x20(1) kFH/w +b0 |EI_= +b0 !pRd4 +b0 &RAbd +#7000000 +b101101 \7mo/ +b101101 0_gMP +b101101 |EI_= +b101101 !pRd4 +b101101 &RAbd +#8000000 +b1011010 \7mo/ +b1011010 0_gMP +b1011010 |EI_= +b1011010 !pRd4 +b1011010 &RAbd +#9000000 +b10000111 \7mo/ +b10000111 0_gMP +b10000111 |EI_= +b10000111 !pRd4 +b10000111 &RAbd +#10000000 +b10110100 \7mo/ +b10110100 0_gMP +b10110100 |EI_= +b10110100 !pRd4 +b10110100 &RAbd +#11000000 +b11100001 \7mo/ +b11100001 0_gMP +b11100001 |EI_= +b11100001 !pRd4 +b11100001 &RAbd +#12000000 +b10 J&-ne +b0 \7mo/ +b10 ,`>ir +b0 0_gMP +sC\x20(2) kFH/w +b0 |EI_= +b0 !pRd4 +b0 &RAbd +#13000000 +b101101 \7mo/ +b101101 0_gMP +b101101 |EI_= +b101101 !pRd4 +b101101 &RAbd +#14000000 +b1011010 \7mo/ +b1011010 0_gMP +b1011010 |EI_= +b1011010 !pRd4 +b1011010 &RAbd +#15000000 +b10000111 \7mo/ +b10000111 0_gMP +b10000111 |EI_= +b10000111 !pRd4 +b10000111 &RAbd +#16000000 +b10110100 \7mo/ +b10110100 0_gMP +b10110100 |EI_= +b10110100 !pRd4 +b10110100 &RAbd +#17000000 +b11100001 \7mo/ +b11100001 0_gMP +b11100001 |EI_= +b11100001 !pRd4 +b11100001 &RAbd +#18000000 diff --git a/crates/fayalite/tests/sim/expected/enums.txt b/crates/fayalite/tests/sim/expected/enums.txt index a193e92..d2da2d9 100644 --- a/crates/fayalite/tests/sim/expected/enums.txt +++ b/crates/fayalite/tests/sim/expected/enums.txt @@ -1012,173 +1012,177 @@ Simulation { lhs: StatePartIndex(4), // (0x1 1) SlotDebugData { name: "", ty: Bool }, rhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, + 99: Copy { + dest: StatePartIndex(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, + src: StatePartIndex(23), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, + }, // at: module-XXXXXXXXXX.rs:1:1 - 99: Const { + 100: Const { dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, value: 0x0, }, - 100: Copy { + 101: Copy { dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, src: StatePartIndex(25), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, }, // at: module-XXXXXXXXXX.rs:12:1 - 101: BranchIfZero { - target: 109, + 102: BranchIfZero { + target: 110, value: StatePartIndex(2), // (0x1) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::en", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:13:1 - 102: BranchIfZero { - target: 104, + 103: BranchIfZero { + target: 105, value: StatePartIndex(46), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:14:1 - 103: Copy { + 104: Copy { dest: StatePartIndex(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, src: StatePartIndex(26), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, }, // at: module-XXXXXXXXXX.rs:13:1 - 104: BranchIfNonZero { - target: 109, + 105: BranchIfNonZero { + target: 110, value: StatePartIndex(46), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:15:1 - 105: BranchIfZero { - target: 107, + 106: BranchIfZero { + target: 108, value: StatePartIndex(48), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:16:1 - 106: Copy { + 107: Copy { dest: StatePartIndex(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, src: StatePartIndex(65), // (0xd) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, }, // at: module-XXXXXXXXXX.rs:15:1 - 107: BranchIfNonZero { - target: 109, + 108: BranchIfNonZero { + target: 110, value: StatePartIndex(48), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:17:1 - 108: Copy { + 109: Copy { dest: StatePartIndex(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, src: StatePartIndex(87), // (0x3e) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, }, // at: module-XXXXXXXXXX.rs:10:1 - 109: Copy { + 110: Copy { dest: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b2_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} }, src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} }, }, // at: module-XXXXXXXXXX.rs:1:1 - 110: Copy { + 111: Copy { dest: StatePartIndex(18), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, src: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b2_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} }, }, - 111: SliceInt { + 112: SliceInt { dest: StatePartIndex(19), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, src: StatePartIndex(18), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, start: 1, len: 2, }, - 112: SliceInt { + 113: SliceInt { dest: StatePartIndex(20), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, src: StatePartIndex(19), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, start: 0, len: 1, }, - 113: SliceInt { + 114: SliceInt { dest: StatePartIndex(21), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, src: StatePartIndex(19), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, start: 1, len: 1, }, - 114: Copy { + 115: Copy { dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(21), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, - 115: Copy { + 116: Copy { dest: StatePartIndex(16), // (0x0) SlotDebugData { name: ".0", ty: UInt<1> }, src: StatePartIndex(20), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, - 116: Copy { + 117: Copy { dest: StatePartIndex(17), // (0x0) SlotDebugData { name: ".1", ty: Bool }, src: StatePartIndex(22), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:9:1 - 117: AndBigWithSmallImmediate { + 118: AndBigWithSmallImmediate { dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, lhs: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b2_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} }, rhs: 0x1, }, // at: module-XXXXXXXXXX.rs:1:1 - 118: Copy { + 119: Copy { dest: StatePartIndex(10), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} }, }, - 119: SliceInt { + 120: SliceInt { dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, src: StatePartIndex(10), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, start: 1, len: 2, }, - 120: SliceInt { + 121: SliceInt { dest: StatePartIndex(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, src: StatePartIndex(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, start: 0, len: 1, }, - 121: SliceInt { + 122: SliceInt { dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, src: StatePartIndex(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, start: 1, len: 1, }, - 122: Copy { + 123: Copy { dest: StatePartIndex(14), // (0x0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(13), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, - 123: Copy { + 124: Copy { dest: StatePartIndex(8), // (0x0) SlotDebugData { name: ".0", ty: UInt<1> }, src: StatePartIndex(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, - 124: Copy { + 125: Copy { dest: StatePartIndex(9), // (0x0) SlotDebugData { name: ".1", ty: Bool }, src: StatePartIndex(14), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:8:1 - 125: AndBigWithSmallImmediate { + 126: AndBigWithSmallImmediate { dest: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, lhs: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} }, rhs: 0x1, }, // at: module-XXXXXXXXXX.rs:11:1 - 126: BranchIfSmallZero { - target: 131, + 127: BranchIfSmallZero { + target: 132, value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 127: BranchIfSmallNonZero { - target: 130, + 128: BranchIfSmallNonZero { + target: 131, value: StatePartIndex(5), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 128: Copy { + 129: Copy { dest: StatePartIndex(23), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, src: StatePartIndex(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, }, - 129: Branch { - target: 131, + 130: Branch { + target: 132, }, - 130: Copy { + 131: Copy { dest: StatePartIndex(23), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, src: StatePartIndex(26), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, }, - 131: XorSmallImmediate { + 132: XorSmallImmediate { dest: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(4), // (0x1 1) SlotDebugData { name: "", ty: Bool }, rhs: 0x1, }, // at: module-XXXXXXXXXX.rs:1:1 - 132: Return, + 133: Return, ], .. }, - pc: 132, + pc: 133, memory_write_log: [], memories: StatePart { value: [], @@ -1742,6 +1746,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x1, last_state: 0x0, }, @@ -1750,6 +1755,7 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1758,6 +1764,7 @@ Simulation { kind: BigBool { index: StatePartIndex(2), }, + maybe_changed: false, state: 0x1, last_state: 0x1, }, @@ -1767,6 +1774,7 @@ Simulation { index: StatePartIndex(3), ty: UInt<2>, }, + maybe_changed: false, state: 0x2, last_state: 0x2, }, @@ -1776,6 +1784,7 @@ Simulation { index: StatePartIndex(4), ty: UInt<4>, }, + maybe_changed: false, state: 0xf, last_state: 0xf, }, @@ -1785,6 +1794,7 @@ Simulation { index: StatePartIndex(5), ty: UInt<2>, }, + maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1794,6 +1804,7 @@ Simulation { index: StatePartIndex(6), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -1806,6 +1817,7 @@ Simulation { HdlSome(Bundle {0: UInt<1>, 1: Bool}), }, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1815,6 +1827,7 @@ Simulation { index: StatePartIndex(8), ty: UInt<1>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1823,6 +1836,7 @@ Simulation { kind: BigBool { index: StatePartIndex(9), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1835,6 +1849,7 @@ Simulation { HdlSome(Bundle {0: UInt<1>, 1: Bool}), }, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1844,6 +1859,7 @@ Simulation { index: StatePartIndex(16), ty: UInt<1>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1852,6 +1868,7 @@ Simulation { kind: BigBool { index: StatePartIndex(17), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1865,6 +1882,7 @@ Simulation { C(Bundle {a: Array, 2>, b: SInt<2>}), }, }, + maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1874,6 +1892,7 @@ Simulation { index: StatePartIndex(27), ty: UInt<1>, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1882,6 +1901,7 @@ Simulation { kind: BigBool { index: StatePartIndex(28), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1891,6 +1911,7 @@ Simulation { index: StatePartIndex(34), ty: UInt<1>, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1900,6 +1921,7 @@ Simulation { index: StatePartIndex(35), ty: UInt<1>, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1909,6 +1931,7 @@ Simulation { index: StatePartIndex(36), ty: SInt<2>, }, + maybe_changed: true, state: 0x3, last_state: 0x3, }, diff --git a/crates/fayalite/tests/sim/expected/enums.vcd b/crates/fayalite/tests/sim/expected/enums.vcd index aff867b..03682b1 100644 --- a/crates/fayalite/tests/sim/expected/enums.vcd +++ b/crates/fayalite/tests/sim/expected/enums.vcd @@ -1,126 +1,126 @@ $timescale 1 ps $end $scope module enums $end $scope struct cd $end -$var wire 1 ! clk $end -$var wire 1 " rst $end +$var wire 1 0n\U< clk $end +$var wire 1 a?A!) rst $end $upscope $end -$var wire 1 # en $end -$var wire 2 $ which_in $end -$var wire 4 % data_in $end -$var wire 2 & which_out $end -$var wire 4 ' data_out $end +$var wire 1 #ZQY# en $end +$var wire 2 8?II+ which_in $end +$var wire 4 OO,N+ data_in $end +$var wire 2 yr2gr which_out $end +$var wire 4 q_O;Y data_out $end $scope struct b_out $end -$var string 1 ( \$tag $end +$var string 1 7L1gf \$tag $end $scope struct HdlSome $end -$var wire 1 ) \0 $end -$var wire 1 * \1 $end +$var wire 1 EO?Ju \0 $end +$var wire 1 cGtNN \1 $end $upscope $end $upscope $end $scope struct b2_out $end -$var string 1 + \$tag $end +$var string 1 dqd@B \$tag $end $scope struct HdlSome $end -$var wire 1 , \0 $end -$var wire 1 - \1 $end +$var wire 1 (FG:I \0 $end +$var wire 1 dzy-= \1 $end $upscope $end $upscope $end $scope struct the_reg $end -$var string 1 . \$tag $end +$var string 1 J#9uO \$tag $end $scope struct B $end -$var reg 1 / \0 $end -$var reg 1 0 \1 $end +$var reg 1 ca2Gh \0 $end +$var reg 1 f)r)? \1 $end $upscope $end $scope struct C $end $scope struct a $end -$var reg 1 1 \[0] $end -$var reg 1 2 \[1] $end +$var reg 1 ;BepJ \[0] $end +$var reg 1 J~2;e \[1] $end $upscope $end -$var reg 2 3 b $end +$var reg 2 w\b)K b $end $upscope $end $upscope $end $upscope $end $enddefinitions $end $dumpvars -0! -1" -0# -b0 $ -b0 % -b0 & -b0 ' -sHdlNone\x20(0) ( -0) -0* -sHdlNone\x20(0) + -0, -0- -sA\x20(0) . -0/ -00 -01 -02 -b0 3 +00n\U< +1a?A!) +0#ZQY# +b0 8?II+ +b0 OO,N+ +b0 yr2gr +b0 q_O;Y +sHdlNone\x20(0) 7L1gf +0EO?Ju +0cGtNN +sHdlNone\x20(0) dqd@B +0(FG:I +0dzy-= +sA\x20(0) J#9uO +0ca2Gh +0f)r)? +0;BepJ +0J~2;e +b0 w\b)K $end #1000000 -1! +10n\U< #1100000 -0" +0a?A!) #2000000 -0! +00n\U< #3000000 -1! +10n\U< #4000000 -1# -b1 $ -0! +1#ZQY# +b1 8?II+ +00n\U< #5000000 -1! -b1 & -sHdlSome\x20(1) ( -sHdlSome\x20(1) + -sB\x20(1) . +10n\U< +b1 yr2gr +sHdlSome\x20(1) 7L1gf +sHdlSome\x20(1) dqd@B +sB\x20(1) J#9uO #6000000 -0# -b0 $ -0! +0#ZQY# +b0 8?II+ +00n\U< #7000000 -1! +10n\U< #8000000 -1# -b1 $ -b1111 % -0! +1#ZQY# +b1 8?II+ +b1111 OO,N+ +00n\U< #9000000 -1! -b11 ' -1) -1* -1, -1- -1/ -10 -11 -12 +10n\U< +b11 q_O;Y +1EO?Ju +1cGtNN +1(FG:I +1dzy-= +1ca2Gh +1f)r)? +1;BepJ +1J~2;e #10000000 -0! +00n\U< #11000000 -1! +10n\U< #12000000 -b10 $ -0! +b10 8?II+ +00n\U< #13000000 -1! -b10 & -b1111 ' -sHdlNone\x20(0) ( -0) -0* -sHdlNone\x20(0) + -0, -0- -sC\x20(2) . -b11 3 +10n\U< +b10 yr2gr +b1111 q_O;Y +sHdlNone\x20(0) 7L1gf +0EO?Ju +0cGtNN +sHdlNone\x20(0) dqd@B +0(FG:I +0dzy-= +sC\x20(2) J#9uO +b11 w\b)K #14000000 -0! +00n\U< #15000000 -1! +10n\U< #16000000 diff --git a/crates/fayalite/tests/sim/expected/extern_module.txt b/crates/fayalite/tests/sim/expected/extern_module.txt index f49106f..48a3af5 100644 --- a/crates/fayalite/tests/sim/expected/extern_module.txt +++ b/crates/fayalite/tests/sim/expected/extern_module.txt @@ -221,6 +221,7 @@ Simulation { kind: BigBool { index: StatePartIndex(0), }, + maybe_changed: false, state: 0x1, last_state: 0x1, }, @@ -229,6 +230,7 @@ Simulation { kind: BigBool { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x1, last_state: 0x0, }, diff --git a/crates/fayalite/tests/sim/expected/extern_module.vcd b/crates/fayalite/tests/sim/expected/extern_module.vcd index 5d6a0bc..21ec5b9 100644 --- a/crates/fayalite/tests/sim/expected/extern_module.vcd +++ b/crates/fayalite/tests/sim/expected/extern_module.vcd @@ -1,52 +1,52 @@ $timescale 1 ps $end $scope module extern_module $end -$var wire 1 ! i $end -$var wire 1 " o $end +$var wire 1 `MLd_ i $end +$var wire 1 ^;OnJ o $end $upscope $end $enddefinitions $end $dumpvars -0! -0" +0`MLd_ +0^;OnJ $end -1" +1^;OnJ #500000 #1500000 -0" +0^;OnJ #2500000 -1" +1^;OnJ #3500000 -0" +0^;OnJ #4500000 -1" +1^;OnJ #5500000 -0" +0^;OnJ #6500000 -1" +1^;OnJ #7500000 -0" +0^;OnJ #8500000 -1" +1^;OnJ #9500000 -0" +0^;OnJ #10000000 -1! +1`MLd_ #10500000 #11500000 -1" +1^;OnJ #12500000 -0" +0^;OnJ #13500000 -1" +1^;OnJ #14500000 -0" +0^;OnJ #15500000 -1" +1^;OnJ #16500000 -0" +0^;OnJ #17500000 -1" +1^;OnJ #18500000 -0" +0^;OnJ #19500000 -1" +1^;OnJ #20000000 diff --git a/crates/fayalite/tests/sim/expected/extern_module2.txt b/crates/fayalite/tests/sim/expected/extern_module2.txt index 365830f..d488666 100644 --- a/crates/fayalite/tests/sim/expected/extern_module2.txt +++ b/crates/fayalite/tests/sim/expected/extern_module2.txt @@ -57,7 +57,7 @@ Simulation { big_slots: StatePart { value: [ 0, - 1, + 1 (modified), 101, ], }, @@ -280,6 +280,7 @@ Simulation { kind: BigBool { index: StatePartIndex(0), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -288,6 +289,7 @@ Simulation { kind: BigClock { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -297,6 +299,7 @@ Simulation { index: StatePartIndex(2), ty: UInt<8>, }, + maybe_changed: false, state: 0x65, last_state: 0x65, }, diff --git a/crates/fayalite/tests/sim/expected/extern_module2.vcd b/crates/fayalite/tests/sim/expected/extern_module2.vcd index 4204567..bf0885a 100644 --- a/crates/fayalite/tests/sim/expected/extern_module2.vcd +++ b/crates/fayalite/tests/sim/expected/extern_module2.vcd @@ -1,151 +1,151 @@ $timescale 1 ps $end $scope module extern_module2 $end -$var wire 1 ! en $end -$var wire 1 " clk $end -$var wire 8 # o $end +$var wire 1 oHT(x en $end +$var wire 1 nHT-: clk $end +$var wire 8 0:wF& o $end $upscope $end $enddefinitions $end $dumpvars -1! -0" -b0 # +1oHT(x +0nHT-: +b0 0:wF& $end -b1001000 # +b1001000 0:wF& #1000000 -1" -b1100101 # +1nHT-: +b1100101 0:wF& #2000000 -0" +0nHT-: #3000000 -1" -b1101100 # +1nHT-: +b1101100 0:wF& #4000000 -0" +0nHT-: #5000000 -1" +1nHT-: #6000000 -0" +0nHT-: #7000000 -1" -b1101111 # +1nHT-: +b1101111 0:wF& #8000000 -0" +0nHT-: #9000000 -1" -b101100 # +1nHT-: +b101100 0:wF& #10000000 -0! -0" +0oHT(x +0nHT-: #11000000 -1" +1nHT-: #12000000 -0" +0nHT-: #13000000 -1" +1nHT-: #14000000 -0" +0nHT-: #15000000 -1" +1nHT-: #16000000 -0" +0nHT-: #17000000 -1" +1nHT-: #18000000 -0" +0nHT-: #19000000 -1" +1nHT-: #20000000 -1! -0" +1oHT(x +0nHT-: #21000000 -1" -b100000 # +1nHT-: +b100000 0:wF& #22000000 -0" +0nHT-: #23000000 -1" -b1010111 # +1nHT-: +b1010111 0:wF& #24000000 -0" +0nHT-: #25000000 -1" -b1101111 # +1nHT-: +b1101111 0:wF& #26000000 -0" +0nHT-: #27000000 -1" -b1110010 # +1nHT-: +b1110010 0:wF& #28000000 -0" +0nHT-: #29000000 -1" -b1101100 # +1nHT-: +b1101100 0:wF& #30000000 -0! -0" +0oHT(x +0nHT-: #31000000 -1" +1nHT-: #32000000 -0" +0nHT-: #33000000 -1" +1nHT-: #34000000 -0" +0nHT-: #35000000 -1" +1nHT-: #36000000 -0" +0nHT-: #37000000 -1" +1nHT-: #38000000 -0" +0nHT-: #39000000 -1" +1nHT-: #40000000 -1! -0" +1oHT(x +0nHT-: #41000000 -1" -b1100100 # +1nHT-: +b1100100 0:wF& #42000000 -0" +0nHT-: #43000000 -1" -b100001 # +1nHT-: +b100001 0:wF& #44000000 -0" +0nHT-: #45000000 -1" -b1010 # +1nHT-: +b1010 0:wF& #46000000 -0" +0nHT-: #47000000 -1" -b1001000 # +1nHT-: +b1001000 0:wF& #48000000 -0" +0nHT-: #49000000 -1" -b1100101 # +1nHT-: +b1100101 0:wF& #50000000 -0! -0" +0oHT(x +0nHT-: #51000000 -1" +1nHT-: #52000000 -0" +0nHT-: #53000000 -1" +1nHT-: #54000000 -0" +0nHT-: #55000000 -1" +1nHT-: #56000000 -0" +0nHT-: #57000000 -1" +1nHT-: #58000000 -0" +0nHT-: #59000000 -1" +1nHT-: #60000000 diff --git a/crates/fayalite/tests/sim/expected/last_connect.txt b/crates/fayalite/tests/sim/expected/last_connect.txt new file mode 100644 index 0000000..c5d1341 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/last_connect.txt @@ -0,0 +1,709 @@ +Simulation { + state: State { + insns: Insns { + state_layout: StateLayout { + ty: TypeLayout { + small_slots: StatePartLayout { + len: 2, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 33, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(last_connect: last_connect).last_connect::inp", + ty: Enum { + HdlNone, + HdlSome(Array), + }, + }, + SlotDebugData { + name: "[0]", + ty: Bool, + }, + SlotDebugData { + name: "[1]", + ty: Bool, + }, + SlotDebugData { + name: "[2]", + ty: Bool, + }, + SlotDebugData { + name: "[3]", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(last_connect: last_connect).last_connect::out", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(last_connect: last_connect).last_connect::w", + ty: UInt<8>, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + insns: [ + // at: module-XXXXXXXXXX.rs:1:1 + 0: Const { + dest: StatePartIndex(32), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x3, + }, + 1: Const { + dest: StatePartIndex(31), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x2, + }, + 2: Const { + dest: StatePartIndex(30), // (0x1) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x1, + }, + 3: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + 4: Const { + dest: StatePartIndex(28), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x4, + }, + // at: module-XXXXXXXXXX.rs:8:1 + 5: Copy { + dest: StatePartIndex(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> }, + src: StatePartIndex(28), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: module-XXXXXXXXXX.rs:1:1 + 6: Const { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 7: Const { + dest: StatePartIndex(18), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + value: 0x0, + }, + 8: Copy { + dest: StatePartIndex(19), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(18), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: module-XXXXXXXXXX.rs:4:1 + 9: Copy { + dest: StatePartIndex(15), // (0x7) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::out", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(19), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: module-XXXXXXXXXX.rs:1:1 + 10: Copy { + dest: StatePartIndex(5), // (0x1f) SlotDebugData { name: "", ty: UInt<5> }, + src: StatePartIndex(0), // (0x1f) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::inp", ty: Enum {HdlNone, HdlSome(Array)} }, + }, + 11: SliceInt { + dest: StatePartIndex(6), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(5), // (0x1f) SlotDebugData { name: "", ty: UInt<5> }, + start: 1, + len: 4, + }, + 12: SliceInt { + dest: StatePartIndex(7), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(6), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 1, + }, + 13: Copy { + dest: StatePartIndex(8), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(7), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 14: SliceInt { + dest: StatePartIndex(9), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(6), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, + start: 1, + len: 1, + }, + 15: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(9), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 16: SliceInt { + dest: StatePartIndex(11), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(6), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, + start: 2, + len: 1, + }, + 17: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(11), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 18: SliceInt { + dest: StatePartIndex(13), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(6), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, + start: 3, + len: 1, + }, + 19: Copy { + dest: StatePartIndex(14), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 20: Copy { + dest: StatePartIndex(1), // (0x1) SlotDebugData { name: "[0]", ty: Bool }, + src: StatePartIndex(8), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 21: Copy { + dest: StatePartIndex(2), // (0x1) SlotDebugData { name: "[1]", ty: Bool }, + src: StatePartIndex(10), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 22: Copy { + dest: StatePartIndex(3), // (0x1) SlotDebugData { name: "[2]", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 23: Copy { + dest: StatePartIndex(4), // (0x1) SlotDebugData { name: "[3]", ty: Bool }, + src: StatePartIndex(14), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:9:1 + 24: BranchIfZero { + target: 26, + value: StatePartIndex(1), // (0x1) SlotDebugData { name: "[0]", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:10:1 + 25: Copy { + dest: StatePartIndex(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: module-XXXXXXXXXX.rs:9:1 + 26: BranchIfZero { + target: 28, + value: StatePartIndex(2), // (0x1) SlotDebugData { name: "[1]", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:10:1 + 27: Copy { + dest: StatePartIndex(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: module-XXXXXXXXXX.rs:9:1 + 28: BranchIfZero { + target: 30, + value: StatePartIndex(3), // (0x1) SlotDebugData { name: "[2]", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:10:1 + 29: Copy { + dest: StatePartIndex(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> }, + src: StatePartIndex(31), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: module-XXXXXXXXXX.rs:9:1 + 30: BranchIfZero { + target: 32, + value: StatePartIndex(4), // (0x1) SlotDebugData { name: "[3]", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:10:1 + 31: Copy { + dest: StatePartIndex(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> }, + src: StatePartIndex(32), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: module-XXXXXXXXXX.rs:1:1 + 32: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(23), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 33: Copy { + dest: StatePartIndex(22), // (0x3) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> }, + }, + 34: Shl { + dest: StatePartIndex(24), // (0x6) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(22), // (0x3) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 35: Or { + dest: StatePartIndex(25), // (0x7) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(21), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(24), // (0x6) SlotDebugData { name: "", ty: UInt<9> }, + }, + 36: CastToUInt { + dest: StatePartIndex(26), // (0x7) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(25), // (0x7) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 37: Copy { + dest: StatePartIndex(27), // (0x7) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(26), // (0x7) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: module-XXXXXXXXXX.rs:2:1 + 38: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(0), // (0x1f) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::inp", ty: Enum {HdlNone, HdlSome(Array)} }, + rhs: 0x1, + }, + // at: module-XXXXXXXXXX.rs:5:1 + 39: BranchIfSmallNeImmediate { + target: 41, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: module-XXXXXXXXXX.rs:7:1 + 40: Copy { + dest: StatePartIndex(15), // (0x7) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::out", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(27), // (0x7) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: module-XXXXXXXXXX.rs:3:1 + 41: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(15), // (0x7) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::out", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: module-XXXXXXXXXX.rs:1:1 + 42: Copy { + dest: StatePartIndex(16), // (0x7) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(15), // (0x7) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::out", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 43: SliceInt { + dest: StatePartIndex(17), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(16), // (0x7) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + 44: Return, + ], + .. + }, + pc: 44, + memory_write_log: [], + memories: StatePart { + value: [], + }, + small_slots: StatePart { + value: [ + 1, + 1, + ], + }, + big_slots: StatePart { + value: [ + 31, + 1, + 1, + 1, + 1, + 31, + 15, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 7 (modified), + 7, + 3, + 0, + 0, + 3, + 1, + 3, + 1, + 6, + 7, + 7, + 7, + 4, + 0, + 1, + 2, + 3, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::last_connect, + instantiated: Module { + name: last_connect, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::last_connect, + instantiated: Module { + name: last_connect, + .. + }, + }.inp, + Instance { + name: ::last_connect, + instantiated: Module { + name: last_connect, + .. + }, + }.out, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::last_connect, + instantiated: Module { + name: last_connect, + .. + }, + }.inp, + Instance { + name: ::last_connect, + instantiated: Module { + name: last_connect, + .. + }, + }.out, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "last_connect", + children: [ + TraceModuleIO { + name: "inp", + child: TraceEnumWithFields { + name: "inp", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(0), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Array), + }, + flow: Source, + }, + non_empty_fields: [ + TraceArray { + name: "HdlSome", + elements: [ + TraceBool { + location: TraceScalarId(1), + name: "[0]", + flow: Source, + }, + TraceBool { + location: TraceScalarId(2), + name: "[1]", + flow: Source, + }, + TraceBool { + location: TraceScalarId(3), + name: "[2]", + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "[3]", + flow: Source, + }, + ], + ty: Array, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Array), + }, + flow: Source, + }, + ty: Enum { + HdlNone, + HdlSome(Array), + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceEnumWithFields { + name: "out", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceWire { + name: "w", + child: TraceUInt { + location: TraceScalarId(7), + name: "w", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(Array), + }, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigBool { + index: StatePartIndex(1), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(2), + kind: BigBool { + index: StatePartIndex(2), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigBool { + index: StatePartIndex(3), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(4), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(17), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x03, + last_state: 0x02, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigUInt { + index: StatePartIndex(20), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x03, + last_state: 0x02, + }, + ], + trace_memories: {}, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [], + event_queue: EventQueue(EventQueueData { + instant: 17 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/last_connect.vcd b/crates/fayalite/tests/sim/expected/last_connect.vcd new file mode 100644 index 0000000..b8b2f56 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/last_connect.vcd @@ -0,0 +1,104 @@ +$timescale 1 ps $end +$scope module last_connect $end +$scope struct inp $end +$var string 1 !C&}* \$tag $end +$scope struct HdlSome $end +$var wire 1 D_viZ \[0] $end +$var wire 1 b5gFK \[1] $end +$var wire 1 xUBRH \[2] $end +$var wire 1 Gp7Xm \[3] $end +$upscope $end +$upscope $end +$scope struct out $end +$var string 1 ^Z_p3 \$tag $end +$var wire 8 rz~), HdlSome $end +$upscope $end +$var wire 8 dlea> w $end +$upscope $end +$enddefinitions $end +$dumpvars +sHdlNone\x20(0) !C&}* +0D_viZ +0b5gFK +0xUBRH +0Gp7Xm +sHdlNone\x20(0) ^Z_p3 +b0 rz~), +b100 dlea> +$end +#1000000 +sHdlSome\x20(1) !C&}* +sHdlSome\x20(1) ^Z_p3 +b100 rz~), +#2000000 +1Gp7Xm +b11 rz~), +b11 dlea> +#3000000 +1xUBRH +0Gp7Xm +b10 rz~), +b10 dlea> +#4000000 +1Gp7Xm +b11 rz~), +b11 dlea> +#5000000 +1b5gFK +0xUBRH +0Gp7Xm +b1 rz~), +b1 dlea> +#6000000 +1Gp7Xm +b11 rz~), +b11 dlea> +#7000000 +1xUBRH +0Gp7Xm +b10 rz~), +b10 dlea> +#8000000 +1Gp7Xm +b11 rz~), +b11 dlea> +#9000000 +1D_viZ +0b5gFK +0xUBRH +0Gp7Xm +b0 rz~), +b0 dlea> +#10000000 +1Gp7Xm +b11 rz~), +b11 dlea> +#11000000 +1xUBRH +0Gp7Xm +b10 rz~), +b10 dlea> +#12000000 +1Gp7Xm +b11 rz~), +b11 dlea> +#13000000 +1b5gFK +0xUBRH +0Gp7Xm +b1 rz~), +b1 dlea> +#14000000 +1Gp7Xm +b11 rz~), +b11 dlea> +#15000000 +1xUBRH +0Gp7Xm +b10 rz~), +b10 dlea> +#16000000 +1Gp7Xm +b11 rz~), +b11 dlea> +#17000000 diff --git a/crates/fayalite/tests/sim/expected/many_memories.txt b/crates/fayalite/tests/sim/expected/many_memories.txt index c521d72..0d1a6db 100644 --- a/crates/fayalite/tests/sim/expected/many_memories.txt +++ b/crates/fayalite/tests/sim/expected/many_memories.txt @@ -5545,6 +5545,7 @@ Simulation { index: StatePartIndex(0), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -5553,6 +5554,7 @@ Simulation { kind: BigBool { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -5561,6 +5563,7 @@ Simulation { kind: BigClock { index: StatePartIndex(2), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -5569,6 +5572,7 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5578,6 +5582,7 @@ Simulation { index: StatePartIndex(4), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -5586,6 +5591,7 @@ Simulation { kind: BigBool { index: StatePartIndex(5), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -5594,6 +5600,7 @@ Simulation { kind: BigClock { index: StatePartIndex(6), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -5602,6 +5609,7 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5611,6 +5619,7 @@ Simulation { index: StatePartIndex(8), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -5619,6 +5628,7 @@ Simulation { kind: BigBool { index: StatePartIndex(9), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -5627,6 +5637,7 @@ Simulation { kind: BigClock { index: StatePartIndex(10), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -5635,6 +5646,7 @@ Simulation { kind: BigBool { index: StatePartIndex(11), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5644,6 +5656,7 @@ Simulation { index: StatePartIndex(12), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -5652,6 +5665,7 @@ Simulation { kind: BigBool { index: StatePartIndex(13), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -5660,6 +5674,7 @@ Simulation { kind: BigClock { index: StatePartIndex(14), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -5668,6 +5683,7 @@ Simulation { kind: BigBool { index: StatePartIndex(15), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5677,6 +5693,7 @@ Simulation { index: StatePartIndex(16), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -5685,6 +5702,7 @@ Simulation { kind: BigBool { index: StatePartIndex(17), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -5693,6 +5711,7 @@ Simulation { kind: BigClock { index: StatePartIndex(18), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -5701,6 +5720,7 @@ Simulation { kind: BigBool { index: StatePartIndex(19), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5710,6 +5730,7 @@ Simulation { index: StatePartIndex(20), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -5718,6 +5739,7 @@ Simulation { kind: BigBool { index: StatePartIndex(21), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -5726,6 +5748,7 @@ Simulation { kind: BigClock { index: StatePartIndex(22), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -5734,6 +5757,7 @@ Simulation { kind: BigBool { index: StatePartIndex(23), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5743,6 +5767,7 @@ Simulation { index: StatePartIndex(24), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -5751,6 +5776,7 @@ Simulation { kind: BigBool { index: StatePartIndex(25), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -5759,6 +5785,7 @@ Simulation { kind: BigClock { index: StatePartIndex(26), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -5767,6 +5794,7 @@ Simulation { kind: BigBool { index: StatePartIndex(27), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5776,6 +5804,7 @@ Simulation { index: StatePartIndex(28), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -5784,6 +5813,7 @@ Simulation { kind: BigBool { index: StatePartIndex(29), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -5792,6 +5822,7 @@ Simulation { kind: BigClock { index: StatePartIndex(30), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -5800,6 +5831,7 @@ Simulation { kind: BigBool { index: StatePartIndex(31), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5809,6 +5841,7 @@ Simulation { index: StatePartIndex(32), ty: UInt<4>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5817,6 +5850,7 @@ Simulation { kind: BigBool { index: StatePartIndex(33), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5825,6 +5859,7 @@ Simulation { kind: BigClock { index: StatePartIndex(34), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -5833,6 +5868,7 @@ Simulation { kind: BigBool { index: StatePartIndex(35), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5841,6 +5877,7 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -5850,6 +5887,7 @@ Simulation { index: StatePartIndex(37), ty: UInt<4>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5858,6 +5896,7 @@ Simulation { kind: BigBool { index: StatePartIndex(38), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5866,6 +5905,7 @@ Simulation { kind: BigClock { index: StatePartIndex(39), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -5874,6 +5914,7 @@ Simulation { kind: BigBool { index: StatePartIndex(40), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5882,6 +5923,7 @@ Simulation { kind: BigBool { index: StatePartIndex(41), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -5891,6 +5933,7 @@ Simulation { index: StatePartIndex(42), ty: UInt<4>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5899,6 +5942,7 @@ Simulation { kind: BigBool { index: StatePartIndex(43), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5907,6 +5951,7 @@ Simulation { kind: BigClock { index: StatePartIndex(44), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -5915,6 +5960,7 @@ Simulation { kind: BigBool { index: StatePartIndex(45), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5923,6 +5969,7 @@ Simulation { kind: BigBool { index: StatePartIndex(46), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -5932,6 +5979,7 @@ Simulation { index: StatePartIndex(47), ty: UInt<4>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5940,6 +5988,7 @@ Simulation { kind: BigBool { index: StatePartIndex(48), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5948,6 +5997,7 @@ Simulation { kind: BigClock { index: StatePartIndex(49), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -5956,6 +6006,7 @@ Simulation { kind: BigBool { index: StatePartIndex(50), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5964,6 +6015,7 @@ Simulation { kind: BigBool { index: StatePartIndex(51), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -5973,6 +6025,7 @@ Simulation { index: StatePartIndex(52), ty: UInt<4>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5981,6 +6034,7 @@ Simulation { kind: BigBool { index: StatePartIndex(53), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5989,6 +6043,7 @@ Simulation { kind: BigClock { index: StatePartIndex(54), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -5997,6 +6052,7 @@ Simulation { kind: BigBool { index: StatePartIndex(55), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6005,6 +6061,7 @@ Simulation { kind: BigBool { index: StatePartIndex(56), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6014,6 +6071,7 @@ Simulation { index: StatePartIndex(57), ty: UInt<4>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6022,6 +6080,7 @@ Simulation { kind: BigBool { index: StatePartIndex(58), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6030,6 +6089,7 @@ Simulation { kind: BigClock { index: StatePartIndex(59), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6038,6 +6098,7 @@ Simulation { kind: BigBool { index: StatePartIndex(60), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6046,6 +6107,7 @@ Simulation { kind: BigBool { index: StatePartIndex(61), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6055,6 +6117,7 @@ Simulation { index: StatePartIndex(62), ty: UInt<4>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6063,6 +6126,7 @@ Simulation { kind: BigBool { index: StatePartIndex(63), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6071,6 +6135,7 @@ Simulation { kind: BigClock { index: StatePartIndex(64), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6079,6 +6144,7 @@ Simulation { kind: BigBool { index: StatePartIndex(65), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6087,6 +6153,7 @@ Simulation { kind: BigBool { index: StatePartIndex(66), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6096,6 +6163,7 @@ Simulation { index: StatePartIndex(67), ty: UInt<4>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6104,6 +6172,7 @@ Simulation { kind: BigBool { index: StatePartIndex(68), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6112,6 +6181,7 @@ Simulation { kind: BigClock { index: StatePartIndex(69), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6120,6 +6190,7 @@ Simulation { kind: BigBool { index: StatePartIndex(70), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6128,6 +6199,7 @@ Simulation { kind: BigBool { index: StatePartIndex(71), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6137,6 +6209,7 @@ Simulation { index: StatePartIndex(72), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -6145,6 +6218,7 @@ Simulation { kind: BigBool { index: StatePartIndex(73), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6153,6 +6227,7 @@ Simulation { kind: BigClock { index: StatePartIndex(74), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6161,6 +6236,7 @@ Simulation { kind: BigBool { index: StatePartIndex(75), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6170,6 +6246,7 @@ Simulation { index: StatePartIndex(76), ty: UInt<4>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6178,6 +6255,7 @@ Simulation { kind: BigBool { index: StatePartIndex(77), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6186,6 +6264,7 @@ Simulation { kind: BigClock { index: StatePartIndex(78), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6194,6 +6273,7 @@ Simulation { kind: BigBool { index: StatePartIndex(79), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6202,6 +6282,7 @@ Simulation { kind: BigBool { index: StatePartIndex(80), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6211,6 +6292,7 @@ Simulation { index: StatePartIndex(83), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -6219,6 +6301,7 @@ Simulation { kind: BigBool { index: StatePartIndex(84), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6227,6 +6310,7 @@ Simulation { kind: BigClock { index: StatePartIndex(85), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6235,6 +6319,7 @@ Simulation { kind: BigBool { index: StatePartIndex(86), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6244,6 +6329,7 @@ Simulation { index: StatePartIndex(87), ty: UInt<4>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6252,6 +6338,7 @@ Simulation { kind: BigBool { index: StatePartIndex(88), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6260,6 +6347,7 @@ Simulation { kind: BigClock { index: StatePartIndex(89), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6268,6 +6356,7 @@ Simulation { kind: BigBool { index: StatePartIndex(90), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6276,6 +6365,7 @@ Simulation { kind: BigBool { index: StatePartIndex(91), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6285,6 +6375,7 @@ Simulation { index: StatePartIndex(94), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -6293,6 +6384,7 @@ Simulation { kind: BigBool { index: StatePartIndex(95), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6301,6 +6393,7 @@ Simulation { kind: BigClock { index: StatePartIndex(96), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6309,6 +6402,7 @@ Simulation { kind: BigBool { index: StatePartIndex(97), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6318,6 +6412,7 @@ Simulation { index: StatePartIndex(98), ty: UInt<4>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6326,6 +6421,7 @@ Simulation { kind: BigBool { index: StatePartIndex(99), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6334,6 +6430,7 @@ Simulation { kind: BigClock { index: StatePartIndex(100), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6342,6 +6439,7 @@ Simulation { kind: BigBool { index: StatePartIndex(101), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6350,6 +6448,7 @@ Simulation { kind: BigBool { index: StatePartIndex(102), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6359,6 +6458,7 @@ Simulation { index: StatePartIndex(105), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -6367,6 +6467,7 @@ Simulation { kind: BigBool { index: StatePartIndex(106), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6375,6 +6476,7 @@ Simulation { kind: BigClock { index: StatePartIndex(107), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6383,6 +6485,7 @@ Simulation { kind: BigBool { index: StatePartIndex(108), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6392,6 +6495,7 @@ Simulation { index: StatePartIndex(109), ty: UInt<4>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6400,6 +6504,7 @@ Simulation { kind: BigBool { index: StatePartIndex(110), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6408,6 +6513,7 @@ Simulation { kind: BigClock { index: StatePartIndex(111), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6416,6 +6522,7 @@ Simulation { kind: BigBool { index: StatePartIndex(112), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6424,6 +6531,7 @@ Simulation { kind: BigBool { index: StatePartIndex(113), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6433,6 +6541,7 @@ Simulation { index: StatePartIndex(116), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -6441,6 +6550,7 @@ Simulation { kind: BigBool { index: StatePartIndex(117), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6449,6 +6559,7 @@ Simulation { kind: BigClock { index: StatePartIndex(118), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6457,6 +6568,7 @@ Simulation { kind: BigBool { index: StatePartIndex(119), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6466,6 +6578,7 @@ Simulation { index: StatePartIndex(120), ty: UInt<4>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6474,6 +6587,7 @@ Simulation { kind: BigBool { index: StatePartIndex(121), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6482,6 +6596,7 @@ Simulation { kind: BigClock { index: StatePartIndex(122), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6490,6 +6605,7 @@ Simulation { kind: BigBool { index: StatePartIndex(123), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6498,6 +6614,7 @@ Simulation { kind: BigBool { index: StatePartIndex(124), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6507,6 +6624,7 @@ Simulation { index: StatePartIndex(127), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -6515,6 +6633,7 @@ Simulation { kind: BigBool { index: StatePartIndex(128), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6523,6 +6642,7 @@ Simulation { kind: BigClock { index: StatePartIndex(129), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6531,6 +6651,7 @@ Simulation { kind: BigBool { index: StatePartIndex(130), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6540,6 +6661,7 @@ Simulation { index: StatePartIndex(131), ty: UInt<4>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6548,6 +6670,7 @@ Simulation { kind: BigBool { index: StatePartIndex(132), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6556,6 +6679,7 @@ Simulation { kind: BigClock { index: StatePartIndex(133), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6564,6 +6688,7 @@ Simulation { kind: BigBool { index: StatePartIndex(134), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6572,6 +6697,7 @@ Simulation { kind: BigBool { index: StatePartIndex(135), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6581,6 +6707,7 @@ Simulation { index: StatePartIndex(138), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -6589,6 +6716,7 @@ Simulation { kind: BigBool { index: StatePartIndex(139), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6597,6 +6725,7 @@ Simulation { kind: BigClock { index: StatePartIndex(140), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6605,6 +6734,7 @@ Simulation { kind: BigBool { index: StatePartIndex(141), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6614,6 +6744,7 @@ Simulation { index: StatePartIndex(142), ty: UInt<4>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6622,6 +6753,7 @@ Simulation { kind: BigBool { index: StatePartIndex(143), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6630,6 +6762,7 @@ Simulation { kind: BigClock { index: StatePartIndex(144), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6638,6 +6771,7 @@ Simulation { kind: BigBool { index: StatePartIndex(145), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6646,6 +6780,7 @@ Simulation { kind: BigBool { index: StatePartIndex(146), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6655,6 +6790,7 @@ Simulation { index: StatePartIndex(149), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -6663,6 +6799,7 @@ Simulation { kind: BigBool { index: StatePartIndex(150), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6671,6 +6808,7 @@ Simulation { kind: BigClock { index: StatePartIndex(151), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6679,6 +6817,7 @@ Simulation { kind: BigBool { index: StatePartIndex(152), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6688,6 +6827,7 @@ Simulation { index: StatePartIndex(153), ty: UInt<4>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6696,6 +6836,7 @@ Simulation { kind: BigBool { index: StatePartIndex(154), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6704,6 +6845,7 @@ Simulation { kind: BigClock { index: StatePartIndex(155), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6712,6 +6854,7 @@ Simulation { kind: BigBool { index: StatePartIndex(156), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6720,6 +6863,7 @@ Simulation { kind: BigBool { index: StatePartIndex(157), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, diff --git a/crates/fayalite/tests/sim/expected/many_memories.vcd b/crates/fayalite/tests/sim/expected/many_memories.vcd index 77d1447..db41ca3 100644 --- a/crates/fayalite/tests/sim/expected/many_memories.vcd +++ b/crates/fayalite/tests/sim/expected/many_memories.vcd @@ -2,2595 +2,2595 @@ $timescale 1 ps $end $scope module many_memories $end $scope struct r $end $scope struct \[0] $end -$var wire 4 ! addr $end -$var wire 1 " en $end -$var wire 1 # clk $end -$var wire 1 $ data $end +$var wire 4 d|7Sd addr $end +$var wire 1 bl7[X en $end +$var wire 1 17/]f clk $end +$var wire 1 0*lF; data $end $upscope $end $scope struct \[1] $end -$var wire 4 % addr $end -$var wire 1 & en $end -$var wire 1 ' clk $end -$var wire 1 ( data $end +$var wire 4 0?lo9 addr $end +$var wire 1 iP},z en $end +$var wire 1 5Gki< clk $end +$var wire 1 5MnH3 data $end $upscope $end $scope struct \[2] $end -$var wire 4 ) addr $end -$var wire 1 * en $end -$var wire 1 + clk $end -$var wire 1 , data $end +$var wire 4 AvJcz addr $end +$var wire 1 mSys{ en $end +$var wire 1 jJ+ac clk $end +$var wire 1 4C05W data $end $upscope $end $scope struct \[3] $end -$var wire 4 - addr $end -$var wire 1 . en $end -$var wire 1 / clk $end -$var wire 1 0 data $end +$var wire 4 sC0ee addr $end +$var wire 1 tG`f% en $end +$var wire 1 V1=.M clk $end +$var wire 1 6!E3h data $end $upscope $end $scope struct \[4] $end -$var wire 4 1 addr $end -$var wire 1 2 en $end -$var wire 1 3 clk $end -$var wire 1 4 data $end +$var wire 4 j,j"< addr $end +$var wire 1 >[_ax en $end +$var wire 1 (v:Ix clk $end +$var wire 1 J[r\_ data $end $upscope $end $scope struct \[5] $end -$var wire 4 5 addr $end -$var wire 1 6 en $end -$var wire 1 7 clk $end -$var wire 1 8 data $end +$var wire 4 OXs&> addr $end +$var wire 1 lu%y\ en $end +$var wire 1 l=z|A clk $end +$var wire 1 +UTFi data $end $upscope $end $scope struct \[6] $end -$var wire 4 9 addr $end -$var wire 1 : en $end -$var wire 1 ; clk $end -$var wire 1 < data $end +$var wire 4 iC]Q& addr $end +$var wire 1 h:kXG en $end +$var wire 1 hP6aI clk $end +$var wire 1 72ujb data $end $upscope $end $scope struct \[7] $end -$var wire 4 = addr $end -$var wire 1 > en $end -$var wire 1 ? clk $end -$var wire 1 @ data $end +$var wire 4 "I):@ addr $end +$var wire 1 rw'Lc en $end +$var wire 1 Vvn/E clk $end +$var wire 1 .[P*8 data $end $upscope $end $upscope $end $scope struct w $end $scope struct \[0] $end -$var wire 4 A addr $end -$var wire 1 B en $end -$var wire 1 C clk $end -$var wire 1 D data $end -$var wire 1 E mask $end +$var wire 4 W9?X. addr $end +$var wire 1 4Dh3Z en $end +$var wire 1 $\W(J clk $end +$var wire 1 cH{Ze data $end +$var wire 1 _OA4l mask $end $upscope $end $scope struct \[1] $end -$var wire 4 F addr $end -$var wire 1 G en $end -$var wire 1 H clk $end -$var wire 1 I data $end -$var wire 1 J mask $end +$var wire 4 6,|K% addr $end +$var wire 1 #'qYA en $end +$var wire 1 QI!iU clk $end +$var wire 1 |di=b data $end +$var wire 1 BCB!} mask $end $upscope $end $scope struct \[2] $end -$var wire 4 K addr $end -$var wire 1 L en $end -$var wire 1 M clk $end -$var wire 1 N data $end -$var wire 1 O mask $end +$var wire 4 $i,h9 addr $end +$var wire 1 =4Sky en $end +$var wire 1 EC,z> clk $end +$var wire 1 y;\Pv data $end +$var wire 1 1XcmV mask $end $upscope $end $scope struct \[3] $end -$var wire 4 P addr $end -$var wire 1 Q en $end -$var wire 1 R clk $end -$var wire 1 S data $end -$var wire 1 T mask $end +$var wire 4 IC,mz addr $end +$var wire 1 LM^hS en $end +$var wire 1 mm5\_ clk $end +$var wire 1 KYJ1[ data $end +$var wire 1 ;wrI1 mask $end $upscope $end $scope struct \[4] $end -$var wire 4 U addr $end -$var wire 1 V en $end -$var wire 1 W clk $end -$var wire 1 X data $end -$var wire 1 Y mask $end +$var wire 4 ^%H-d addr $end +$var wire 1 {{"vF en $end +$var wire 1 sfo}Z clk $end +$var wire 1 VxyrG data $end +$var wire 1 rjp*# mask $end $upscope $end $scope struct \[5] $end -$var wire 4 Z addr $end -$var wire 1 [ en $end -$var wire 1 \ clk $end -$var wire 1 ] data $end -$var wire 1 ^ mask $end +$var wire 4 %xhho addr $end +$var wire 1 ]0GiL en $end +$var wire 1 )|%6{ clk $end +$var wire 1 ,3Sf| data $end +$var wire 1 oJrGc mask $end $upscope $end $scope struct \[6] $end -$var wire 4 _ addr $end -$var wire 1 ` en $end -$var wire 1 a clk $end -$var wire 1 b data $end -$var wire 1 c mask $end +$var wire 4 TdJW4 addr $end +$var wire 1 LjMuL en $end +$var wire 1 t'l~] clk $end +$var wire 1 <}D%K data $end +$var wire 1 @0}S5 mask $end $upscope $end $scope struct \[7] $end -$var wire 4 d addr $end -$var wire 1 e en $end -$var wire 1 f clk $end -$var wire 1 g data $end -$var wire 1 h mask $end +$var wire 4 @T;Mg addr $end +$var wire 1 lGp}g en $end +$var wire 1 [|v\H$ addr $end +$var wire 1 1dk]f en $end +$var wire 1 B(P|B clk $end +$var wire 1 {)s\9 data $end $upscope $end $scope struct w1 $end -$var wire 4 m addr $end -$var wire 1 n en $end -$var wire 1 o clk $end -$var wire 1 p data $end -$var wire 1 q mask $end +$var wire 4 |Xtj6 addr $end +$var wire 1 kEHuz en $end +$var wire 1 .7gMQ clk $end +$var wire 1 GC4id data $end +$var wire 1 po>X< mask $end $upscope $end $upscope $end $scope struct mem_1 $end $scope struct contents $end $scope struct \[0] $end -$var reg 1 c" mem_1 $end +$var reg 1 lk3NH mem_1 $end $upscope $end $scope struct \[1] $end -$var reg 1 d" mem_1 $end +$var reg 1 V]u6p mem_1 $end $upscope $end $scope struct \[2] $end -$var reg 1 e" mem_1 $end +$var reg 1 U=Gh> mem_1 $end $upscope $end $scope struct \[3] $end -$var reg 1 f" mem_1 $end +$var reg 1 1Fg?Y mem_1 $end $upscope $end $scope struct \[4] $end -$var reg 1 g" mem_1 $end +$var reg 1 x[-fM mem_1 $end $upscope $end $scope struct \[5] $end -$var reg 1 h" mem_1 $end +$var reg 1 $1^H, mem_1 $end $upscope $end $scope struct \[6] $end -$var reg 1 i" mem_1 $end +$var reg 1 0M$4D mem_1 $end $upscope $end $scope struct \[7] $end -$var reg 1 j" mem_1 $end +$var reg 1 CN_fu mem_1 $end $upscope $end $scope struct \[8] $end -$var reg 1 k" mem_1 $end +$var reg 1 K/ql@ mem_1 $end $upscope $end $scope struct \[9] $end -$var reg 1 l" mem_1 $end +$var reg 1 '%]Ik mem_1 $end $upscope $end $scope struct \[10] $end -$var reg 1 m" mem_1 $end +$var reg 1 M[~-; mem_1 $end $upscope $end $scope struct \[11] $end -$var reg 1 n" mem_1 $end +$var reg 1 ae(_Y mem_1 $end $upscope $end $scope struct \[12] $end -$var reg 1 o" mem_1 $end +$var reg 1 @~%Yu mem_1 $end $upscope $end $scope struct \[13] $end -$var reg 1 p" mem_1 $end +$var reg 1 bly?K mem_1 $end $upscope $end $scope struct \[14] $end -$var reg 1 q" mem_1 $end +$var reg 1 ;l0g- mem_1 $end $upscope $end $scope struct \[15] $end -$var reg 1 r" mem_1 $end +$var reg 1 Pc5L mem_1 $end $upscope $end $upscope $end $scope struct r0 $end -$var wire 4 r addr $end -$var wire 1 s en $end -$var wire 1 t clk $end -$var wire 1 u data $end +$var wire 4 ,SVcw addr $end +$var wire 1 crI6R en $end +$var wire 1 7}oLq clk $end +$var wire 1 pv)Ph data $end $upscope $end $scope struct w1 $end -$var wire 4 v addr $end -$var wire 1 w en $end -$var wire 1 x clk $end -$var wire 1 y data $end -$var wire 1 z mask $end +$var wire 4 E%~x' addr $end +$var wire 1 K9WYT en $end +$var wire 1 a~%H' clk $end +$var wire 1 |=vD0 data $end +$var wire 1 ]K`^ mask $end $upscope $end $upscope $end $scope struct mem_2 $end $scope struct contents $end $scope struct \[0] $end -$var reg 1 s" mem_2 $end +$var reg 1 S33J- mem_2 $end $upscope $end $scope struct \[1] $end -$var reg 1 t" mem_2 $end +$var reg 1 6|@8V mem_2 $end $upscope $end $scope struct \[2] $end -$var reg 1 u" mem_2 $end +$var reg 1 >&bO) mem_2 $end $upscope $end $scope struct \[3] $end -$var reg 1 v" mem_2 $end +$var reg 1 I6cQ4 mem_2 $end $upscope $end $scope struct \[4] $end -$var reg 1 w" mem_2 $end +$var reg 1 6<\}Q mem_2 $end $upscope $end $scope struct \[5] $end -$var reg 1 x" mem_2 $end +$var reg 1 f:Ue2 mem_2 $end $upscope $end $scope struct \[6] $end -$var reg 1 y" mem_2 $end +$var reg 1 5Me%A mem_2 $end $upscope $end $scope struct \[7] $end -$var reg 1 z" mem_2 $end +$var reg 1 o?yX1 mem_2 $end $upscope $end $scope struct \[8] $end -$var reg 1 {" mem_2 $end +$var reg 1 _usg8 mem_2 $end $upscope $end $scope struct \[9] $end -$var reg 1 |" mem_2 $end +$var reg 1 VrGM\ mem_2 $end $upscope $end $scope struct \[10] $end -$var reg 1 }" mem_2 $end +$var reg 1 "CN$B mem_2 $end $upscope $end $scope struct \[11] $end -$var reg 1 ~" mem_2 $end +$var reg 1 &Kn]3 mem_2 $end $upscope $end $scope struct \[12] $end -$var reg 1 !# mem_2 $end +$var reg 1 pidX) mem_2 $end $upscope $end $scope struct \[13] $end -$var reg 1 "# mem_2 $end +$var reg 1 JXxH( mem_2 $end $upscope $end $scope struct \[14] $end -$var reg 1 ## mem_2 $end +$var reg 1 alU~# mem_2 $end $upscope $end $scope struct \[15] $end -$var reg 1 $# mem_2 $end +$var reg 1 o4-M= mem_2 $end $upscope $end $upscope $end $scope struct r0 $end -$var wire 4 { addr $end -$var wire 1 | en $end -$var wire 1 } clk $end -$var wire 1 ~ data $end +$var wire 4 8K@uI addr $end +$var wire 1 BL~4g en $end +$var wire 1 B{,;o mem_3 $end $upscope $end $scope struct \[9] $end -$var reg 1 .# mem_3 $end +$var reg 1 @|$h( mem_3 $end $upscope $end $scope struct \[10] $end -$var reg 1 /# mem_3 $end +$var reg 1 sey{< mem_3 $end $upscope $end $scope struct \[11] $end -$var reg 1 0# mem_3 $end +$var reg 1 RbWU} mem_3 $end $upscope $end $scope struct \[12] $end -$var reg 1 1# mem_3 $end +$var reg 1 S09. mem_3 $end $upscope $end $upscope $end $scope struct r0 $end -$var wire 4 &" addr $end -$var wire 1 '" en $end -$var wire 1 (" clk $end -$var wire 1 )" data $end +$var wire 4 QLM%y addr $end +$var wire 1 7k:)O en $end +$var wire 1 }oa[9 clk $end +$var wire 1 GfxP1 data $end $upscope $end $scope struct w1 $end -$var wire 4 *" addr $end -$var wire 1 +" en $end -$var wire 1 ," clk $end -$var wire 1 -" data $end -$var wire 1 ." mask $end +$var wire 4 z$\>X addr $end +$var wire 1 J%@q: en $end +$var wire 1 xI.Te clk $end +$var wire 1 ),_Fe data $end +$var wire 1 %MYTb mask $end $upscope $end $upscope $end $scope struct mem_4 $end $scope struct contents $end $scope struct \[0] $end -$var reg 1 5# mem_4 $end +$var reg 1 qH-C: mem_4 $end $upscope $end $scope struct \[1] $end -$var reg 1 6# mem_4 $end +$var reg 1 7085? mem_4 $end $upscope $end $scope struct \[2] $end -$var reg 1 7# mem_4 $end +$var reg 1 OvgNF mem_4 $end $upscope $end $scope struct \[3] $end -$var reg 1 8# mem_4 $end +$var reg 1 RYxHq mem_4 $end $upscope $end $scope struct \[4] $end -$var reg 1 9# mem_4 $end +$var reg 1 vxZgk mem_4 $end $upscope $end $scope struct \[5] $end -$var reg 1 :# mem_4 $end +$var reg 1 5$~C^ mem_4 $end $upscope $end $scope struct \[6] $end -$var reg 1 ;# mem_4 $end +$var reg 1 xtUn" mem_4 $end $upscope $end $scope struct \[7] $end -$var reg 1 <# mem_4 $end +$var reg 1 (z5:+ mem_4 $end $upscope $end $scope struct \[8] $end -$var reg 1 =# mem_4 $end +$var reg 1 YjR,s mem_4 $end $upscope $end $scope struct \[9] $end -$var reg 1 ># mem_4 $end +$var reg 1 rT%&} mem_4 $end $upscope $end $scope struct \[10] $end -$var reg 1 ?# mem_4 $end +$var reg 1 O!KVd mem_4 $end $upscope $end $scope struct \[11] $end -$var reg 1 @# mem_4 $end +$var reg 1 ?7>@X mem_4 $end $upscope $end $scope struct \[12] $end -$var reg 1 A# mem_4 $end +$var reg 1 nZ6qC mem_4 $end $upscope $end $scope struct \[13] $end -$var reg 1 B# mem_4 $end +$var reg 1 gYe2 mem_4 $end $upscope $end $scope struct \[14] $end -$var reg 1 C# mem_4 $end +$var reg 1 B#~Pl mem_4 $end $upscope $end $scope struct \[15] $end -$var reg 1 D# mem_4 $end +$var reg 1 lG!\@ mem_4 $end $upscope $end $upscope $end $scope struct r0 $end -$var wire 4 /" addr $end -$var wire 1 0" en $end -$var wire 1 1" clk $end -$var wire 1 2" data $end +$var wire 4 (M75i addr $end +$var wire 1 Eieoc en $end +$var wire 1 y0m-; clk $end +$var wire 1 3EUJ' data $end $upscope $end $scope struct w1 $end -$var wire 4 3" addr $end -$var wire 1 4" en $end -$var wire 1 5" clk $end -$var wire 1 6" data $end -$var wire 1 7" mask $end +$var wire 4 'N|N? addr $end +$var wire 1 /S-9% en $end +$var wire 1 0vX"- clk $end +$var wire 1 HE6Kx data $end +$var wire 1 hQ>V( mask $end $upscope $end $upscope $end $scope struct mem_5 $end $scope struct contents $end $scope struct \[0] $end -$var reg 1 E# mem_5 $end +$var reg 1 1GGb_ mem_5 $end $upscope $end $scope struct \[1] $end -$var reg 1 F# mem_5 $end +$var reg 1 LxqC. mem_5 $end $upscope $end $scope struct \[2] $end -$var reg 1 G# mem_5 $end +$var reg 1 3&byj mem_5 $end $upscope $end $scope struct \[3] $end -$var reg 1 H# mem_5 $end +$var reg 1 ]c~pH mem_5 $end $upscope $end $scope struct \[4] $end -$var reg 1 I# mem_5 $end +$var reg 1 gn[Z# mem_5 $end $upscope $end $scope struct \[5] $end -$var reg 1 J# mem_5 $end +$var reg 1 kk4^N mem_5 $end $upscope $end $scope struct \[6] $end -$var reg 1 K# mem_5 $end +$var reg 1 FM>f& mem_5 $end $upscope $end $scope struct \[7] $end -$var reg 1 L# mem_5 $end +$var reg 1 JURf" mem_5 $end $upscope $end $scope struct \[8] $end -$var reg 1 M# mem_5 $end +$var reg 1 ^|(GS mem_5 $end $upscope $end $scope struct \[9] $end -$var reg 1 N# mem_5 $end +$var reg 1 q>Dbi mem_5 $end $upscope $end $scope struct \[10] $end -$var reg 1 O# mem_5 $end +$var reg 1 v,X*" mem_5 $end $upscope $end $scope struct \[11] $end -$var reg 1 P# mem_5 $end +$var reg 1 rU3!' mem_5 $end $upscope $end $scope struct \[12] $end -$var reg 1 Q# mem_5 $end +$var reg 1 ubZS. mem_5 $end $upscope $end $scope struct \[13] $end -$var reg 1 R# mem_5 $end +$var reg 1 lS`!+ mem_5 $end $upscope $end $scope struct \[14] $end -$var reg 1 S# mem_5 $end +$var reg 1 wlw&y mem_5 $end $upscope $end $scope struct \[15] $end -$var reg 1 T# mem_5 $end +$var reg 1 VVy9L mem_5 $end $upscope $end $upscope $end $scope struct r0 $end -$var wire 4 8" addr $end -$var wire 1 9" en $end -$var wire 1 :" clk $end -$var wire 1 ;" data $end +$var wire 4 ].DK0 addr $end +$var wire 1 C#?U9 en $end +$var wire 1 E~'G) clk $end +$var wire 1 m0~w" data $end $upscope $end $scope struct w1 $end -$var wire 4 <" addr $end -$var wire 1 =" en $end -$var wire 1 >" clk $end -$var wire 1 ?" data $end -$var wire 1 @" mask $end +$var wire 4 6Sh6[ addr $end +$var wire 1 vYM@u en $end +$var wire 1 =hC'C clk $end +$var wire 1 %\?Z# data $end +$var wire 1 +[l=? mask $end $upscope $end $upscope $end $scope struct mem_6 $end $scope struct contents $end $scope struct \[0] $end -$var reg 1 U# mem_6 $end +$var reg 1 V#g\W mem_6 $end $upscope $end $scope struct \[1] $end -$var reg 1 V# mem_6 $end +$var reg 1 X@70L mem_6 $end $upscope $end $scope struct \[2] $end -$var reg 1 W# mem_6 $end +$var reg 1 o/;vI mem_6 $end $upscope $end $scope struct \[3] $end -$var reg 1 X# mem_6 $end +$var reg 1 nNNhp mem_6 $end $upscope $end $scope struct \[4] $end -$var reg 1 Y# mem_6 $end +$var reg 1 g[SEK mem_6 $end $upscope $end $scope struct \[5] $end -$var reg 1 Z# mem_6 $end +$var reg 1 49L)5 mem_6 $end $upscope $end $scope struct \[6] $end -$var reg 1 [# mem_6 $end +$var reg 1 fl?5< mem_6 $end $upscope $end $scope struct \[7] $end -$var reg 1 \# mem_6 $end +$var reg 1 {,;|[ mem_6 $end $upscope $end $scope struct \[8] $end -$var reg 1 ]# mem_6 $end +$var reg 1 kFDen mem_6 $end $upscope $end $scope struct \[9] $end -$var reg 1 ^# mem_6 $end +$var reg 1 lu;*r mem_6 $end $upscope $end $scope struct \[10] $end -$var reg 1 _# mem_6 $end +$var reg 1 sinoU mem_6 $end $upscope $end $scope struct \[11] $end -$var reg 1 `# mem_6 $end +$var reg 1 >o]Q( mem_6 $end $upscope $end $scope struct \[12] $end -$var reg 1 a# mem_6 $end +$var reg 1 !1]}f mem_6 $end $upscope $end $scope struct \[13] $end -$var reg 1 b# mem_6 $end +$var reg 1 >IRWA mem_6 $end $upscope $end $scope struct \[14] $end -$var reg 1 c# mem_6 $end +$var reg 1 ]GER# mem_6 $end $upscope $end $scope struct \[15] $end -$var reg 1 d# mem_6 $end +$var reg 1 s&5]X mem_6 $end $upscope $end $upscope $end $scope struct r0 $end -$var wire 4 A" addr $end -$var wire 1 B" en $end -$var wire 1 C" clk $end -$var wire 1 D" data $end +$var wire 4 ZWBn} addr $end +$var wire 1 |$cvr en $end +$var wire 1 T)in_ clk $end +$var wire 1 )McFt data $end $upscope $end $scope struct w1 $end -$var wire 4 E" addr $end -$var wire 1 F" en $end -$var wire 1 G" clk $end -$var wire 1 H" data $end -$var wire 1 I" mask $end +$var wire 4 gpGf3 addr $end +$var wire 1 `kT)O en $end +$var wire 1 fjh5& clk $end +$var wire 1 >&/MW data $end +$var wire 1 *XTPN mask $end $upscope $end $upscope $end $scope struct mem_7 $end $scope struct contents $end $scope struct \[0] $end -$var reg 1 e# mem_7 $end +$var reg 1 <1w8% mem_7 $end $upscope $end $scope struct \[1] $end -$var reg 1 f# mem_7 $end +$var reg 1 33nkV mem_7 $end $upscope $end $scope struct \[2] $end -$var reg 1 g# mem_7 $end +$var reg 1 px}q] mem_7 $end $upscope $end $scope struct \[3] $end -$var reg 1 h# mem_7 $end +$var reg 1 cmnxp mem_7 $end $upscope $end $scope struct \[4] $end -$var reg 1 i# mem_7 $end +$var reg 1 3rQ$Z mem_7 $end $upscope $end $scope struct \[5] $end -$var reg 1 j# mem_7 $end +$var reg 1 5k{84 mem_7 $end $upscope $end $scope struct \[6] $end -$var reg 1 k# mem_7 $end +$var reg 1 PO#rR mem_7 $end $upscope $end $scope struct \[7] $end -$var reg 1 l# mem_7 $end +$var reg 1 ki$A7 mem_7 $end $upscope $end $scope struct \[8] $end -$var reg 1 m# mem_7 $end +$var reg 1 qM^Sv mem_7 $end $upscope $end $scope struct \[9] $end -$var reg 1 n# mem_7 $end +$var reg 1 dF]W- mem_7 $end $upscope $end $scope struct \[10] $end -$var reg 1 o# mem_7 $end +$var reg 1 RzEG+ mem_7 $end $upscope $end $scope struct \[11] $end -$var reg 1 p# mem_7 $end +$var reg 1 "W|s6 mem_7 $end $upscope $end $scope struct \[12] $end -$var reg 1 q# mem_7 $end +$var reg 1 shQ1m mem_7 $end $upscope $end $scope struct \[13] $end -$var reg 1 r# mem_7 $end +$var reg 1 hN^kl mem_7 $end $upscope $end $scope struct \[14] $end -$var reg 1 s# mem_7 $end +$var reg 1 fc7WM mem_7 $end $upscope $end $scope struct \[15] $end -$var reg 1 t# mem_7 $end +$var reg 1 K0W.8 mem_7 $end $upscope $end $upscope $end $scope struct r0 $end -$var wire 4 J" addr $end -$var wire 1 K" en $end -$var wire 1 L" clk $end -$var wire 1 M" data $end +$var wire 4 lJ\tx addr $end +$var wire 1 O2d5] en $end +$var wire 1 $Kx=q clk $end +$var wire 1 p[RX3 data $end $upscope $end $scope struct w1 $end -$var wire 4 N" addr $end -$var wire 1 O" en $end -$var wire 1 P" clk $end -$var wire 1 Q" data $end -$var wire 1 R" mask $end +$var wire 4 i|V&P addr $end +$var wire 1 `A40g en $end +$var wire 1 }&U]O clk $end +$var wire 1 {g%2| data $end +$var wire 1 A%,}] mask $end $upscope $end $upscope $end $upscope $end $enddefinitions $end $dumpvars -0S" -0T" -0U" -0V" -0W" -0X" -0Y" -0Z" -0[" -0\" -0]" -0^" -0_" -0`" -0a" -0b" -1c" -0d" -0e" -0f" -0g" -0h" -0i" -0j" -0k" -0l" -0m" -0n" -0o" -0p" -0q" -0r" -0s" -0t" -0u" -0v" -0w" -1x" -0y" -0z" -0{" -0|" -0}" -0~" -0!# -0"# -0## -0$# -1%# -1&# -0'# -0(# -1)# -1*# -1+# -1,# -0-# -0.# -0/# -00# -01# -02# -03# -04# -05# -06# -07# -08# -09# -0:# -0;# -0<# -0=# -0># -1?# -0@# -0A# -0B# -0C# -0D# -1E# -0F# -1G# -0H# -1I# -1J# -0K# -0L# -0M# -0N# -1O# -1P# -0Q# -0R# -0S# -0T# -0U# -0V# -0W# -0X# -0Y# -1Z# -1[# -0\# -0]# -1^# -1_# -1`# -1a# -0b# -0c# -0d# -1e# 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+072ujb +b0 "I):@ +0rw'Lc +0Vvn/E +0.[P*8 +b0 W9?X. +04Dh3Z +0$\W(J +0cH{Ze +0_OA4l +b0 6,|K% +0#'qYA +0QI!iU +0|di=b +0BCB!} +b0 $i,h9 +0=4Sky +0EC,z> +0y;\Pv +01XcmV +b0 IC,mz +0LM^hS +0mm5\_ +0KYJ1[ +0;wrI1 +b0 ^%H-d +0{{"vF +0sfo}Z +0VxyrG +0rjp*# +b0 %xhho +0]0GiL +0)|%6{ +0,3Sf| +0oJrGc +b0 TdJW4 +0LjMuL +0t'l~] +0<}D%K +0@0}S5 +b0 @T;Mg +0lGp}g +0[|v\H$ +01dk]f +0B(P|B +0{)s\9 +b0 |Xtj6 +0kEHuz +0.7gMQ +0GC4id +0po>X< +b0 ,SVcw +0crI6R +07}oLq +0pv)Ph +b0 E%~x' +0K9WYT +0a~%H' +0|=vD0 +0]K`^ +b0 8K@uI +0BL~4g +0BX +0J%@q: +0xI.Te +0),_Fe +0%MYTb +b0 (M75i +0Eieoc +0y0m-; +03EUJ' +b0 'N|N? +0/S-9% +00vX"- +0HE6Kx +0hQ>V( +b0 ].DK0 +0C#?U9 +0E~'G) +0m0~w" +b0 6Sh6[ +0vYM@u +0=hC'C +0%\?Z# +0+[l=? +b0 ZWBn} +0|$cvr +0T)in_ +0)McFt +b0 gpGf3 +0`kT)O +0fjh5& +0>&/MW +0*XTPN +b0 lJ\tx +0O2d5] +0$Kx=q +0p[RX3 +b0 i|V&P +0`A40g +0}&U]O +0{g%2| +0A%,}] $end #1000000 -1# -1' -1+ -1/ -13 -17 -1; -1? -1C -1H -1M -1R -1W -1\ -1a -1f -1k -1o -1t -1x -1} -1#" -1(" -1," -11" -15" -1:" -1>" -1C" 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+05Gki< +0jJ+ac +0V1=.M +0(v:Ix +0l=z|A +0hP6aI +0Vvn/E +0$\W(J +0QI!iU +0EC,z> +0mm5\_ +0sfo}Z +0)|%6{ +0t'l~] +0[|v(0), ty: UInt<4>, }, + maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1176,6 +1177,7 @@ Simulation { kind: BigBool { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1184,6 +1186,7 @@ Simulation { kind: BigClock { index: StatePartIndex(2), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1193,6 +1196,7 @@ Simulation { index: StatePartIndex(3), ty: UInt<8>, }, + maybe_changed: true, state: 0xb0, last_state: 0xb0, }, @@ -1202,6 +1206,7 @@ Simulation { index: StatePartIndex(4), ty: SInt<8>, }, + maybe_changed: true, state: 0xc0, last_state: 0xc0, }, @@ -1211,6 +1216,7 @@ Simulation { index: StatePartIndex(5), ty: UInt<4>, }, + maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1219,6 +1225,7 @@ Simulation { kind: BigBool { index: StatePartIndex(6), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1227,6 +1234,7 @@ Simulation { kind: BigClock { index: StatePartIndex(7), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1236,6 +1244,7 @@ Simulation { index: StatePartIndex(8), ty: UInt<8>, }, + maybe_changed: true, state: 0xd0, last_state: 0xd0, }, @@ -1245,6 +1254,7 @@ Simulation { index: StatePartIndex(9), ty: SInt<8>, }, + maybe_changed: true, state: 0xe0, last_state: 0xe0, }, @@ -1253,6 +1263,7 @@ Simulation { kind: BigBool { index: StatePartIndex(10), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1261,6 +1272,7 @@ Simulation { kind: BigBool { index: StatePartIndex(11), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1270,6 +1282,7 @@ Simulation { index: StatePartIndex(12), ty: UInt<4>, }, + maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1278,6 +1291,7 @@ Simulation { kind: BigBool { index: StatePartIndex(13), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1286,6 +1300,7 @@ Simulation { kind: BigClock { index: StatePartIndex(14), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1295,6 +1310,7 @@ Simulation { index: StatePartIndex(15), ty: UInt<8>, }, + maybe_changed: true, state: 0xb0, last_state: 0xb0, }, @@ -1304,6 +1320,7 @@ Simulation { index: StatePartIndex(16), ty: SInt<8>, }, + maybe_changed: true, state: 0xc0, last_state: 0xc0, }, @@ -1313,6 +1330,7 @@ Simulation { index: StatePartIndex(17), ty: UInt<4>, }, + maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1321,6 +1339,7 @@ Simulation { kind: BigBool { index: StatePartIndex(18), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1329,6 +1348,7 @@ Simulation { kind: BigClock { index: StatePartIndex(19), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1338,6 +1358,7 @@ Simulation { index: StatePartIndex(20), ty: UInt<8>, }, + maybe_changed: true, state: 0xd0, last_state: 0xd0, }, @@ -1347,6 +1368,7 @@ Simulation { index: StatePartIndex(21), ty: SInt<8>, }, + maybe_changed: true, state: 0xe0, last_state: 0xe0, }, @@ -1355,6 +1377,7 @@ Simulation { kind: BigBool { index: StatePartIndex(22), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1363,6 +1386,7 @@ Simulation { kind: BigBool { index: StatePartIndex(23), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, diff --git a/crates/fayalite/tests/sim/expected/memories.vcd b/crates/fayalite/tests/sim/expected/memories.vcd index d8f5817..7a54fbf 100644 --- a/crates/fayalite/tests/sim/expected/memories.vcd +++ b/crates/fayalite/tests/sim/expected/memories.vcd @@ -1,408 +1,408 @@ $timescale 1 ps $end $scope module memories $end $scope struct r $end -$var wire 4 ! addr $end -$var wire 1 " en $end -$var wire 1 # clk $end +$var wire 4 z&0Qk addr $end +$var wire 1 o.T)# en $end +$var wire 1 :XNoK clk $end $scope struct data $end -$var wire 8 $ \0 $end -$var wire 8 % \1 $end +$var wire 8 Cq]A% \0 $end +$var wire 8 avKNj \1 $end $upscope $end $upscope $end $scope struct w $end -$var wire 4 & addr $end -$var wire 1 ' en $end -$var wire 1 ( clk $end +$var wire 4 p \0 $end -$var reg 8 N \1 $end +$var reg 8 dr6lq \0 $end +$var reg 8 fc"UR \1 $end $upscope $end $upscope $end $scope struct \[6] $end $scope struct mem $end -$var reg 8 ? \0 $end -$var reg 8 O \1 $end +$var reg 8 xpw5\ \0 $end +$var reg 8 dd$?K \1 $end $upscope $end $upscope $end $scope struct \[7] $end $scope struct mem $end -$var reg 8 @ \0 $end -$var reg 8 P \1 $end +$var reg 8 vH;}2 \0 $end +$var reg 8 ILB?4 \1 $end $upscope $end $upscope $end $scope struct \[8] $end $scope struct mem $end -$var reg 8 A \0 $end -$var reg 8 Q \1 $end +$var reg 8 /X4v> \0 $end +$var reg 8 &V*EE \1 $end $upscope $end $upscope $end $scope struct \[9] $end $scope struct mem $end -$var reg 8 B \0 $end -$var reg 8 R \1 $end +$var reg 8 IczZe \0 $end +$var reg 8 unX>R \1 $end $upscope $end $upscope $end $scope struct \[10] $end $scope struct mem $end -$var reg 8 C \0 $end -$var reg 8 S \1 $end +$var reg 8 0hTyY \0 $end +$var reg 8 9K_w) \1 $end $upscope $end $upscope $end $scope struct \[11] $end $scope struct mem $end -$var reg 8 D \0 $end -$var reg 8 T \1 $end +$var reg 8 +C/Sz \0 $end +$var reg 8 }Y{:o \1 $end $upscope $end $upscope $end $scope struct \[12] $end $scope struct mem $end -$var reg 8 E \0 $end -$var reg 8 U \1 $end +$var reg 8 S6-5u \0 $end +$var reg 8 9q6)w \1 $end $upscope $end $upscope $end $scope struct \[13] $end $scope struct mem $end -$var reg 8 F \0 $end -$var reg 8 V \1 $end +$var reg 8 !c -b100011 N -b1 ? -b100011 O -b1 @ -b100011 P -b1 A -b100011 Q -b1 B -b100011 R -b1 C -b100011 S -b1 D -b100011 T -b1 E -b100011 U -b1 F -b100011 V -b1 G -b100011 W -b1 H -b100011 X -b0 ! -0" -0# -b0 $ -b0 % -b0 & -0' -0( -b0 ) -b0 * -0+ -0, -b0 - -0. -0/ -b0 0 -b0 1 -b0 2 -03 -04 -b0 5 -b0 6 -07 -08 +b1 4d[cL +b100011 {qEUV +b1 c`NPR +b100011 vK:33 +b1 ihYp_ +b100011 QZb%P +b1 ,O%<$ +b100011 @?uSf +b1 N[IF& +b100011 Zf9lw +b1 dr6lq +b100011 fc"UR +b1 xpw5\ +b100011 dd$?K +b1 vH;}2 +b100011 ILB?4 +b1 /X4v> +b100011 &V*EE +b1 IczZe +b100011 unX>R +b1 0hTyY +b100011 9K_w) +b1 +C/Sz +b100011 }Y{:o +b1 S6-5u +b100011 9q6)w +b1 !c8T +1DC/;" #2000000 -1" -0# -b1 $ -b100011 % -1' -0( -b10000 ) -b100000 * -1+ -1, -1. -0/ -b1 0 -b100011 1 -13 -04 -b10000 5 -b100000 6 -17 -18 +1o.T)# +0:XNoK +b1 Cq]A% +b100011 avKNj +1#9)l8 +0QX!^| +b10000 G"IXQ +b100000 h\t:E +1FCuNz +1/Y7%J +1jy78F +0\o>8T +b1 \k#l +b100011 olx7O +1"7?3I +0DC/;" +b10000 0DrV' +b100000 wa!Cx +1u^b&R +1Ic\|v #3000000 -b10000 9 -b100000 I -1# -b10000 $ -b100000 % -1( -1/ -b10000 0 -b100000 1 -14 +b10000 4d[cL +b100000 {qEUV +1:XNoK +b10000 Cq]A% +b100000 avKNj +1QX!^| +1\o>8T +b10000 \k#l +b100000 olx7O +1DC/;" #4000000 -0# -0( -b110000 ) -b1000000 * -0+ -0/ -04 -b110000 5 -b1000000 6 -07 +0:XNoK +0QX!^| +b110000 G"IXQ +b1000000 h\t:E +0FCuNz +0\o>8T +0DC/;" +b110000 0DrV' +b1000000 wa!Cx +0u^b&R #5000000 -b10000 9 -b1000000 I -1# -b1000000 % -1( -1/ -b1000000 1 -14 +b10000 4d[cL +b1000000 {qEUV +1:XNoK +b1000000 avKNj +1QX!^| +1\o>8T +b1000000 olx7O +1DC/;" #6000000 -0# -0( -b1010000 ) -b1100000 * -1+ -0, -0/ -04 -b1010000 5 -b1100000 6 -17 -08 +0:XNoK +0QX!^| +b1010000 G"IXQ +b1100000 h\t:E +1FCuNz +0/Y7%J +0\o>8T +0DC/;" +b1010000 0DrV' +b1100000 wa!Cx +1u^b&R +0Ic\|v #7000000 -b1010000 9 -b1000000 I -1# -b1010000 $ -1( -1/ -b1010000 0 -14 +b1010000 4d[cL +b1000000 {qEUV +1:XNoK +b1010000 Cq]A% +1QX!^| +1\o>8T +b1010000 \k#l +1DC/;" #8000000 -0# -0( -b1110000 ) -b10000000 * -0+ -0/ -04 -b1110000 5 -b10000000 6 -07 +0:XNoK +0QX!^| +b1110000 G"IXQ +b10000000 h\t:E +0FCuNz +0\o>8T +0DC/;" +b1110000 0DrV' +b10000000 wa!Cx +0u^b&R #9000000 -1# -1( -1/ -14 +1:XNoK +1QX!^| +1\o>8T +1DC/;" #10000000 -0# -0' -0( -b10010000 ) -b10100000 * -0/ -03 -04 -b10010000 5 -b10100000 6 +0:XNoK +0#9)l8 +0QX!^| +b10010000 G"IXQ +b10100000 h\t:E +0\o>8T +0"7?3I +0DC/;" +b10010000 0DrV' +b10100000 wa!Cx #11000000 -1# -1( -1/ -14 +1:XNoK +1QX!^| +1\o>8T +1DC/;" #12000000 -0# -b1 & -1' -0( -1+ -1, -0/ -b1 2 -13 -04 -17 -18 +0:XNoK +b1 p8T +b1 H,W!J +1"7?3I +0DC/;" +1u^b&R +1Ic\|v #13000000 -b10010000 : -b10100000 J -1# -1( -1/ -14 +b10010000 c`NPR +b10100000 vK:33 +1:XNoK +1QX!^| +1\o>8T +1DC/;" #14000000 -0# -b10 & -0( -b10110000 ) -b11000000 * -0/ -b10 2 -04 -b10110000 5 -b11000000 6 +0:XNoK +b10 p8T +b10 H,W!J +0DC/;" +b10110000 0DrV' +b11000000 wa!Cx #15000000 -b10110000 ; -b11000000 K -1# -1( -1/ -14 +b10110000 ihYp_ +b11000000 QZb%P +1:XNoK +1QX!^| +1\o>8T +1DC/;" #16000000 -0# -0' -0( -b11010000 ) -b11100000 * -0/ -03 -04 -b11010000 5 -b11100000 6 +0:XNoK +0#9)l8 +0QX!^| +b11010000 G"IXQ +b11100000 h\t:E +0\o>8T +0"7?3I +0DC/;" +b11010000 0DrV' +b11100000 wa!Cx #17000000 -1# -1( -1/ -14 +1:XNoK +1QX!^| +1\o>8T +1DC/;" #18000000 -b1 ! -0# -b10010000 $ -b10100000 % -0( -b1 - -0/ -b10010000 0 -b10100000 1 -04 +b1 z&0Qk +0:XNoK +b10010000 Cq]A% +b10100000 avKNj +0QX!^| +b1 ="2wN +0\o>8T +b10010000 \k#l +b10100000 olx7O +0DC/;" #19000000 -1# -1( -1/ -14 +1:XNoK +1QX!^| +1\o>8T +1DC/;" #20000000 -b10 ! -0# -b10110000 $ -b11000000 % -0( -b10 - -0/ -b10110000 0 -b11000000 1 -04 +b10 z&0Qk +0:XNoK +b10110000 Cq]A% +b11000000 avKNj +0QX!^| +b10 ="2wN +0\o>8T +b10110000 \k#l +b11000000 olx7O +0DC/;" #21000000 -1# -1( -1/ -14 +1:XNoK +1QX!^| +1\o>8T +1DC/;" #22000000 -0# -0( -0/ -04 +0:XNoK +0QX!^| +0\o>8T +0DC/;" diff --git a/crates/fayalite/tests/sim/expected/memories2.txt b/crates/fayalite/tests/sim/expected/memories2.txt index b4041ba..1f78fcf 100644 --- a/crates/fayalite/tests/sim/expected/memories2.txt +++ b/crates/fayalite/tests/sim/expected/memories2.txt @@ -943,6 +943,7 @@ Simulation { index: StatePartIndex(0), ty: UInt<3>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -951,6 +952,7 @@ Simulation { kind: BigBool { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -959,6 +961,7 @@ Simulation { kind: BigClock { index: StatePartIndex(2), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -968,6 +971,7 @@ Simulation { index: StatePartIndex(3), ty: UInt<2>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -976,6 +980,7 @@ Simulation { kind: BigBool { index: StatePartIndex(4), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -985,6 +990,7 @@ Simulation { index: StatePartIndex(5), ty: UInt<2>, }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -993,6 +999,7 @@ Simulation { kind: BigBool { index: StatePartIndex(6), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1002,6 +1009,7 @@ Simulation { index: StatePartIndex(7), ty: UInt<3>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1010,6 +1018,7 @@ Simulation { kind: BigBool { index: StatePartIndex(8), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1018,6 +1027,7 @@ Simulation { kind: BigClock { index: StatePartIndex(9), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1030,6 +1040,7 @@ Simulation { HdlSome(Bool), }, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1038,6 +1049,7 @@ Simulation { kind: BigBool { index: StatePartIndex(16), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1046,6 +1058,7 @@ Simulation { kind: BigBool { index: StatePartIndex(11), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1058,6 +1071,7 @@ Simulation { HdlSome(Bool), }, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1066,6 +1080,7 @@ Simulation { kind: BigBool { index: StatePartIndex(19), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1074,6 +1089,7 @@ Simulation { kind: BigBool { index: StatePartIndex(13), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, diff --git a/crates/fayalite/tests/sim/expected/memories2.vcd b/crates/fayalite/tests/sim/expected/memories2.vcd index 0ac20f1..182029e 100644 --- a/crates/fayalite/tests/sim/expected/memories2.vcd +++ b/crates/fayalite/tests/sim/expected/memories2.vcd @@ -1,363 +1,363 @@ $timescale 1 ps $end $scope module memories2 $end $scope struct rw $end -$var wire 3 ! addr $end -$var wire 1 " en $end -$var wire 1 # clk $end -$var wire 2 $ rdata $end -$var wire 1 % wmode $end -$var wire 2 & wdata $end -$var wire 1 ' wmask $end +$var wire 3 xkkG> addr $end +$var wire 1 HoA{1 en $end +$var wire 1 C*2BQ clk $end +$var wire 2 ueF!x rdata $end +$var wire 1 m\l/p wmode $end +$var wire 2 WmjEh wdata $end +$var wire 1 +3E@H wmask $end $upscope $end $scope struct mem $end $scope struct contents $end $scope struct \[0] $end $scope struct mem $end -$var string 1 1 \$tag $end -$var reg 1 6 HdlSome $end +$var string 1 ujd9u \$tag $end +$var reg 1 *5lV# HdlSome $end $upscope $end $upscope $end $scope struct \[1] $end $scope struct mem $end -$var string 1 2 \$tag $end -$var reg 1 7 HdlSome $end +$var string 1 *qL|n \$tag $end +$var reg 1 ^/FDC HdlSome $end $upscope $end $upscope $end $scope struct \[2] $end $scope struct mem $end -$var string 1 3 \$tag $end -$var reg 1 8 HdlSome $end +$var string 1 r*7|@ \$tag $end +$var reg 1 YMY"3 HdlSome $end $upscope $end $upscope $end $scope struct \[3] $end $scope struct mem $end -$var string 1 4 \$tag $end -$var reg 1 9 HdlSome $end +$var string 1 jj/6F \$tag $end +$var reg 1 S+Uy} HdlSome $end $upscope $end $upscope $end $scope struct \[4] $end $scope struct mem $end -$var string 1 5 \$tag $end -$var reg 1 : HdlSome $end +$var string 1 H72IP \$tag $end +$var reg 1 vH{({ HdlSome $end $upscope $end $upscope $end $upscope $end $scope struct rw0 $end -$var wire 3 ( addr $end -$var wire 1 ) en $end -$var wire 1 * clk $end +$var wire 3 uabMI addr $end +$var wire 1 LEn[l en $end +$var wire 1 OpH)U clk $end $scope struct rdata $end -$var string 1 + \$tag $end -$var wire 1 , HdlSome $end +$var string 1 [}rcZ \$tag $end +$var wire 1 5f=Y~ HdlSome $end $upscope $end -$var wire 1 - wmode $end +$var wire 1 6c_9_ wmode $end $scope struct wdata $end -$var string 1 . \$tag $end -$var wire 1 / HdlSome $end +$var string 1 $hfRN \$tag $end +$var wire 1 rop,b HdlSome $end $upscope $end -$var wire 1 0 wmask $end +$var wire 1 Ly=US wmask $end $upscope $end $upscope $end $upscope $end $enddefinitions $end $dumpvars -sHdlSome\x20(1) 1 -16 -sHdlSome\x20(1) 2 -17 -sHdlSome\x20(1) 3 -18 -sHdlSome\x20(1) 4 -19 -sHdlSome\x20(1) 5 -1: -b0 ! -0" -0# -b0 $ -0% -b0 & -0' -b0 ( -0) -0* -sHdlNone\x20(0) + -0, -0- -sHdlNone\x20(0) . -0/ -00 +sHdlSome\x20(1) ujd9u +1*5lV# +sHdlSome\x20(1) *qL|n +1^/FDC +sHdlSome\x20(1) r*7|@ +1YMY"3 +sHdlSome\x20(1) jj/6F +1S+Uy} +sHdlSome\x20(1) H72IP +1vH{({ +b0 xkkG> +0HoA{1 +0C*2BQ +b0 ueF!x +0m\l/p +b0 WmjEh +0+3E@H +b0 uabMI +0LEn[l +0OpH)U +sHdlNone\x20(0) [}rcZ +05f=Y~ +06c_9_ +sHdlNone\x20(0) $hfRN +0rop,b +0Ly=US $end #250000 -1# -1* +1C*2BQ +1OpH)U #500000 #750000 -0# -0* +0C*2BQ +0OpH)U #1000000 -1" -1) +1HoA{1 +1LEn[l #1250000 -1# -b11 $ -1* -sHdlSome\x20(1) + -1, +1C*2BQ +b11 ueF!x +1OpH)U +sHdlSome\x20(1) [}rcZ +15f=Y~ #1500000 #1750000 -0# -0* +0C*2BQ +0OpH)U #2000000 -0" -0) +0HoA{1 +0LEn[l #2250000 -1# -b0 $ -1* -sHdlNone\x20(0) + -0, +1C*2BQ +b0 ueF!x +1OpH)U +sHdlNone\x20(0) [}rcZ +05f=Y~ #2500000 #2750000 -0# -0* +0C*2BQ +0OpH)U #3000000 -1" -1% -1' -1) -1- -10 +1HoA{1 +1m\l/p +1+3E@H +1LEn[l +16c_9_ +1Ly=US #3250000 -sHdlNone\x20(0) 1 -06 -1# -1* +sHdlNone\x20(0) ujd9u +0*5lV# +1C*2BQ +1OpH)U #3500000 #3750000 -0# -0* +0C*2BQ +0OpH)U #4000000 -0% -0' -0- -00 +0m\l/p +0+3E@H +06c_9_ +0Ly=US #4250000 -1# -1* +1C*2BQ +1OpH)U #4500000 #4750000 -0# -0* +0C*2BQ +0OpH)U #5000000 -1% -b11 & -1- -sHdlSome\x20(1) . -1/ +1m\l/p +b11 WmjEh +16c_9_ +sHdlSome\x20(1) $hfRN +1rop,b #5250000 -1# -1* +1C*2BQ +1OpH)U #5500000 #5750000 -0# -0* +0C*2BQ +0OpH)U #6000000 -b1 ! -b1 & -1' -b1 ( -0/ -10 +b1 xkkG> +b1 WmjEh +1+3E@H +b1 uabMI +0rop,b +1Ly=US #6250000 -sHdlSome\x20(1) 2 -07 -1# -1* +sHdlSome\x20(1) *qL|n +0^/FDC +1C*2BQ +1OpH)U #6500000 #6750000 -0# -0* +0C*2BQ +0OpH)U #7000000 -b10 ! -b10 & -b10 ( -sHdlNone\x20(0) . +b10 xkkG> +b10 WmjEh +b10 uabMI +sHdlNone\x20(0) $hfRN #7250000 -sHdlNone\x20(0) 3 -08 -1# -1* +sHdlNone\x20(0) r*7|@ +0YMY"3 +1C*2BQ +1OpH)U #7500000 #7750000 -0# -0* +0C*2BQ +0OpH)U #8000000 -b11 ! -b11 & -b11 ( -sHdlSome\x20(1) . -1/ +b11 xkkG> +b11 WmjEh +b11 uabMI +sHdlSome\x20(1) $hfRN +1rop,b #8250000 -sHdlSome\x20(1) 4 -19 -1# -1* +sHdlSome\x20(1) jj/6F +1S+Uy} +1C*2BQ +1OpH)U #8500000 #8750000 -0# -0* +0C*2BQ +0OpH)U #9000000 -b100 ! -b10 & -b100 ( -sHdlNone\x20(0) . -0/ +b100 xkkG> +b10 WmjEh +b100 uabMI +sHdlNone\x20(0) $hfRN +0rop,b #9250000 -sHdlNone\x20(0) 5 -0: -1# -1* +sHdlNone\x20(0) H72IP +0vH{({ +1C*2BQ +1OpH)U #9500000 #9750000 -0# -0* +0C*2BQ +0OpH)U #10000000 -b101 ! -b1 & -b101 ( -sHdlSome\x20(1) . +b101 xkkG> +b1 WmjEh +b101 uabMI +sHdlSome\x20(1) $hfRN #10250000 -1# -1* +1C*2BQ +1OpH)U #10500000 #10750000 -0# -0* +0C*2BQ +0OpH)U #11000000 -b110 ! -b110 ( +b110 xkkG> +b110 uabMI #11250000 -1# -1* +1C*2BQ +1OpH)U #11500000 #11750000 -0# -0* +0C*2BQ +0OpH)U #12000000 -b111 ! -b111 ( +b111 xkkG> +b111 uabMI #12250000 -1# -1* +1C*2BQ +1OpH)U #12500000 #12750000 -0# -0* +0C*2BQ +0OpH)U #13000000 -0% -b0 & -0' -0- -sHdlNone\x20(0) . -00 +0m\l/p +b0 WmjEh +0+3E@H +06c_9_ +sHdlNone\x20(0) $hfRN +0Ly=US #13250000 -1# -1* +1C*2BQ +1OpH)U #13500000 #13750000 -0# -0* +0C*2BQ +0OpH)U #14000000 -b110 ! -b110 ( +b110 xkkG> +b110 uabMI #14250000 -1# -1* +1C*2BQ +1OpH)U #14500000 #14750000 -0# -0* +0C*2BQ +0OpH)U #15000000 -b101 ! -b101 ( +b101 xkkG> +b101 uabMI #15250000 -1# -1* +1C*2BQ +1OpH)U #15500000 #15750000 -0# -0* +0C*2BQ +0OpH)U #16000000 -b100 ! -b100 ( +b100 xkkG> +b100 uabMI #16250000 -1# -1* +1C*2BQ +1OpH)U #16500000 #16750000 -0# -0* +0C*2BQ +0OpH)U #17000000 -b11 ! -b11 ( +b11 xkkG> +b11 uabMI #17250000 -1# -b11 $ -1* -sHdlSome\x20(1) + -1, +1C*2BQ +b11 ueF!x +1OpH)U +sHdlSome\x20(1) [}rcZ +15f=Y~ #17500000 #17750000 -0# -0* +0C*2BQ +0OpH)U #18000000 -b10 ! -b10 ( +b10 xkkG> +b10 uabMI #18250000 -1# -b0 $ -1* -sHdlNone\x20(0) + -0, +1C*2BQ +b0 ueF!x +1OpH)U +sHdlNone\x20(0) [}rcZ +05f=Y~ #18500000 #18750000 -0# -0* +0C*2BQ +0OpH)U #19000000 -b0 ! -b0 ( +b0 xkkG> +b0 uabMI #19250000 -1# -1* +1C*2BQ +1OpH)U #19500000 #19750000 -0# -0* +0C*2BQ +0OpH)U #20000000 -b1 ! -b1 ( +b1 xkkG> +b1 uabMI #20250000 -1# -b1 $ -1* -sHdlSome\x20(1) + +1C*2BQ +b1 ueF!x +1OpH)U +sHdlSome\x20(1) [}rcZ #20500000 #20750000 -0# -0* +0C*2BQ +0OpH)U #21000000 -b0 ! -0" -b0 ( -0) +b0 xkkG> +0HoA{1 +b0 uabMI +0LEn[l #21250000 -1# -b0 $ -1* -sHdlNone\x20(0) + +1C*2BQ +b0 ueF!x +1OpH)U +sHdlNone\x20(0) [}rcZ #21500000 #21750000 -0# -0* +0C*2BQ +0OpH)U #22000000 diff --git a/crates/fayalite/tests/sim/expected/memories3.txt b/crates/fayalite/tests/sim/expected/memories3.txt index 2213912..75720a8 100644 --- a/crates/fayalite/tests/sim/expected/memories3.txt +++ b/crates/fayalite/tests/sim/expected/memories3.txt @@ -2391,6 +2391,7 @@ Simulation { index: StatePartIndex(0), ty: UInt<3>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2399,6 +2400,7 @@ Simulation { kind: BigBool { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2407,6 +2409,7 @@ Simulation { kind: BigClock { index: StatePartIndex(2), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -2416,6 +2419,7 @@ Simulation { index: StatePartIndex(3), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2425,6 +2429,7 @@ Simulation { index: StatePartIndex(4), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2434,6 +2439,7 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2443,6 +2449,7 @@ Simulation { index: StatePartIndex(6), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2452,6 +2459,7 @@ Simulation { index: StatePartIndex(7), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2461,6 +2469,7 @@ Simulation { index: StatePartIndex(8), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2470,6 +2479,7 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2479,6 +2489,7 @@ Simulation { index: StatePartIndex(10), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2488,6 +2499,7 @@ Simulation { index: StatePartIndex(11), ty: UInt<3>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2496,6 +2508,7 @@ Simulation { kind: BigBool { index: StatePartIndex(12), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2504,6 +2517,7 @@ Simulation { kind: BigClock { index: StatePartIndex(13), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -2513,6 +2527,7 @@ Simulation { index: StatePartIndex(14), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2522,6 +2537,7 @@ Simulation { index: StatePartIndex(15), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2531,6 +2547,7 @@ Simulation { index: StatePartIndex(16), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2540,6 +2557,7 @@ Simulation { index: StatePartIndex(17), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2549,6 +2567,7 @@ Simulation { index: StatePartIndex(18), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2558,6 +2577,7 @@ Simulation { index: StatePartIndex(19), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2567,6 +2587,7 @@ Simulation { index: StatePartIndex(20), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2576,6 +2597,7 @@ Simulation { index: StatePartIndex(21), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2584,6 +2606,7 @@ Simulation { kind: BigBool { index: StatePartIndex(22), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2592,6 +2615,7 @@ Simulation { kind: BigBool { index: StatePartIndex(23), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2600,6 +2624,7 @@ Simulation { kind: BigBool { index: StatePartIndex(24), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2608,6 +2633,7 @@ Simulation { kind: BigBool { index: StatePartIndex(25), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2616,6 +2642,7 @@ Simulation { kind: BigBool { index: StatePartIndex(26), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2624,6 +2651,7 @@ Simulation { kind: BigBool { index: StatePartIndex(27), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2632,6 +2660,7 @@ Simulation { kind: BigBool { index: StatePartIndex(28), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2640,6 +2669,7 @@ Simulation { kind: BigBool { index: StatePartIndex(29), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2649,6 +2679,7 @@ Simulation { index: StatePartIndex(30), ty: UInt<3>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2657,6 +2688,7 @@ Simulation { kind: BigBool { index: StatePartIndex(31), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2665,6 +2697,7 @@ Simulation { kind: BigClock { index: StatePartIndex(32), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -2674,6 +2707,7 @@ Simulation { index: StatePartIndex(33), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2683,6 +2717,7 @@ Simulation { index: StatePartIndex(34), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2692,6 +2727,7 @@ Simulation { index: StatePartIndex(35), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2701,6 +2737,7 @@ Simulation { index: StatePartIndex(36), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2710,6 +2747,7 @@ Simulation { index: StatePartIndex(37), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2719,6 +2757,7 @@ Simulation { index: StatePartIndex(38), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2728,6 +2767,7 @@ Simulation { index: StatePartIndex(39), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2737,6 +2777,7 @@ Simulation { index: StatePartIndex(40), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2746,6 +2787,7 @@ Simulation { index: StatePartIndex(57), ty: UInt<3>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2754,6 +2796,7 @@ Simulation { kind: BigBool { index: StatePartIndex(58), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2762,6 +2805,7 @@ Simulation { kind: BigClock { index: StatePartIndex(59), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -2771,6 +2815,7 @@ Simulation { index: StatePartIndex(60), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2780,6 +2825,7 @@ Simulation { index: StatePartIndex(61), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2789,6 +2835,7 @@ Simulation { index: StatePartIndex(62), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2798,6 +2845,7 @@ Simulation { index: StatePartIndex(63), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2807,6 +2855,7 @@ Simulation { index: StatePartIndex(64), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2816,6 +2865,7 @@ Simulation { index: StatePartIndex(65), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2825,6 +2875,7 @@ Simulation { index: StatePartIndex(66), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2834,6 +2885,7 @@ Simulation { index: StatePartIndex(67), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2842,6 +2894,7 @@ Simulation { kind: BigBool { index: StatePartIndex(68), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2850,6 +2903,7 @@ Simulation { kind: BigBool { index: StatePartIndex(69), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2858,6 +2912,7 @@ Simulation { kind: BigBool { index: StatePartIndex(70), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2866,6 +2921,7 @@ Simulation { kind: BigBool { index: StatePartIndex(71), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2874,6 +2930,7 @@ Simulation { kind: BigBool { index: StatePartIndex(72), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2882,6 +2939,7 @@ Simulation { kind: BigBool { index: StatePartIndex(73), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2890,6 +2948,7 @@ Simulation { kind: BigBool { index: StatePartIndex(74), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2898,6 +2957,7 @@ Simulation { kind: BigBool { index: StatePartIndex(75), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, diff --git a/crates/fayalite/tests/sim/expected/memories3.vcd b/crates/fayalite/tests/sim/expected/memories3.vcd index 32ee75e..9495de9 100644 --- a/crates/fayalite/tests/sim/expected/memories3.vcd +++ b/crates/fayalite/tests/sim/expected/memories3.vcd @@ -1,836 +1,836 @@ $timescale 1 ps $end $scope module memories3 $end $scope struct r $end -$var wire 3 ! addr $end -$var wire 1 " en $end -$var wire 1 # clk $end +$var wire 3 }Q=~y addr $end +$var wire 1 ,Ca!' en $end +$var wire 1 dJF\@ clk $end $scope struct data $end -$var wire 8 $ \[0] $end -$var wire 8 % \[1] $end -$var wire 8 & \[2] $end -$var wire 8 ' \[3] $end -$var wire 8 ( \[4] $end -$var wire 8 ) \[5] $end -$var wire 8 * \[6] $end -$var wire 8 + \[7] $end +$var wire 8 "w$'Q \[0] $end +$var wire 8 mIo&U \[1] $end +$var wire 8 LJ\m% \[2] $end +$var wire 8 `Zp>N \[3] $end +$var wire 8 YR.PG \[4] $end +$var wire 8 BZ&)B \[5] $end +$var wire 8 _$[8D \[6] $end +$var wire 8 tc)n] \[7] $end $upscope $end $upscope $end $scope struct w $end -$var wire 3 , addr $end -$var wire 1 - en $end -$var wire 1 . clk $end +$var wire 3 bs-Rg addr $end +$var wire 1 *T~2b en $end +$var wire 1 }[YPW clk $end $scope struct data $end -$var wire 8 / \[0] $end -$var wire 8 0 \[1] $end -$var wire 8 1 \[2] $end -$var wire 8 2 \[3] $end -$var wire 8 3 \[4] $end -$var wire 8 4 \[5] $end -$var wire 8 5 \[6] $end -$var wire 8 6 \[7] $end +$var wire 8 6,aYz \[0] $end +$var wire 8 Bq5kY \[1] $end +$var wire 8 :lN4y \[2] $end +$var wire 8 +9uC] \[3] $end +$var wire 8 /EG3; \[4] $end +$var wire 8 >=e$j \[5] $end +$var wire 8 >wz^~ \[6] $end +$var wire 8 CYt2z \[7] $end $upscope $end $scope struct mask $end -$var wire 1 7 \[0] $end -$var wire 1 8 \[1] $end -$var wire 1 9 \[2] $end -$var wire 1 : \[3] $end -$var wire 1 ; \[4] $end -$var wire 1 < \[5] $end -$var wire 1 = \[6] $end -$var wire 1 > \[7] $end +$var wire 1 :.XL} \[0] $end +$var wire 1 0b%VN \[1] $end +$var wire 1 *w)7y \[2] $end +$var wire 1 1dg() \[3] $end +$var wire 1 s%c_Q \[0] $end +$var reg 8 B$aO# \[1] $end +$var reg 8 .=-:e \[2] $end +$var reg 8 WqHtO \[3] $end +$var reg 8 \P/B8 \[4] $end +$var reg 8 ~f|@~ \[5] $end +$var reg 8 [xw38 \[6] $end +$var reg 8 ,mMiC \[7] $end $upscope $end $upscope $end $scope struct \[6] $end $scope struct mem $end -$var reg 8 c \[0] $end -$var reg 8 k \[1] $end -$var reg 8 s \[2] $end -$var reg 8 { \[3] $end -$var reg 8 %" \[4] $end -$var reg 8 -" \[5] $end -$var reg 8 5" \[6] $end -$var reg 8 =" \[7] $end +$var reg 8 T){Kr \[0] $end +$var reg 8 JCt-5 \[1] $end +$var reg 8 JJ`q% \[2] $end +$var reg 8 &8m;f \[3] $end +$var reg 8 .N&;O \[4] $end +$var reg 8 9CPW} \[5] $end +$var reg 8 ~cUnd \[6] $end +$var reg 8 S6,C. \[7] $end $upscope $end $upscope $end $scope struct \[7] $end $scope struct mem $end -$var reg 8 d \[0] $end -$var reg 8 l \[1] $end -$var reg 8 t \[2] $end -$var reg 8 | \[3] $end -$var reg 8 &" \[4] $end -$var reg 8 ." \[5] $end -$var reg 8 6" \[6] $end -$var reg 8 >" \[7] $end +$var reg 8 h,t%t \[0] $end +$var reg 8 M.'tT \[1] $end +$var reg 8 WH^lq \[2] $end +$var reg 8 wk@1l \[3] $end +$var reg 8 XPVW/ \[4] $end +$var reg 8 8i**= \[5] $end +$var reg 8 T7yLi \[6] $end +$var reg 8 xPnYC \[7] $end $upscope $end $upscope $end $upscope $end $scope struct r0 $end -$var wire 3 ? addr $end -$var wire 1 @ en $end -$var wire 1 A clk $end +$var wire 3 ]7,pz addr $end +$var wire 1 ]ky*D en $end +$var wire 1 pK0f; clk $end $scope struct data $end -$var wire 8 B \[0] $end -$var wire 8 C \[1] $end -$var wire 8 D \[2] $end -$var wire 8 E \[3] $end -$var wire 8 F \[4] $end -$var wire 8 G \[5] $end -$var wire 8 H \[6] $end -$var wire 8 I \[7] $end +$var wire 8 Wz+1. \[0] $end +$var wire 8 q-WOU \[1] $end +$var wire 8 ,iWd9 \[2] $end +$var wire 8 P,^c) \[3] $end +$var wire 8 s?0AD \[4] $end +$var wire 8 {,&!. \[5] $end +$var wire 8 0~wS+ \[6] $end +$var wire 8 ZqG9i \[7] $end $upscope $end $upscope $end $scope struct w1 $end -$var wire 3 J addr $end -$var wire 1 K en $end -$var wire 1 L clk $end +$var wire 3 iuiB`l[ \[6] $end +$var wire 8 481V} \[7] $end $upscope $end $scope struct mask $end -$var wire 1 U \[0] $end -$var wire 1 V \[1] $end -$var wire 1 W \[2] $end -$var wire 1 X \[3] $end -$var wire 1 Y \[4] $end -$var wire 1 Z \[5] $end -$var wire 1 [ \[6] $end -$var wire 1 \ \[7] $end +$var wire 1 E`@Pc \[0] $end +$var wire 1 Hm9Lt \[1] $end +$var wire 1 D@ZT~ \[2] $end +$var wire 1 %ZXkA \[3] $end +$var wire 1 dO-sf \[4] $end +$var wire 1 uE-x9 \[5] $end +$var wire 1 [w<$[ \[6] $end +$var wire 1 *7bb6 \[7] $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end $dumpvars -b0 ] -b0 e -b0 m -b0 u -b0 } -b0 '" -b0 /" -b0 7" -b0 ^ -b0 f -b0 n -b0 v -b0 ~ -b0 (" -b0 0" -b0 8" -b0 _ -b0 g -b0 o -b0 w -b0 !" -b0 )" -b0 1" -b0 9" -b0 ` -b0 h -b0 p -b0 x -b0 "" -b0 *" -b0 2" -b0 :" -b0 a -b0 i -b0 q -b0 y -b0 #" -b0 +" -b0 3" -b0 ;" -b0 b -b0 j -b0 r -b0 z -b0 $" -b0 ," -b0 4" -b0 <" -b0 c -b0 k -b0 s -b0 { -b0 %" -b0 -" -b0 5" -b0 =" -b0 d -b0 l -b0 t -b0 | -b0 &" -b0 ." -b0 6" -b0 >" -b0 ! -0" -0# -b0 $ -b0 % -b0 & -b0 ' -b0 ( -b0 ) -b0 * -b0 + -b0 , -1- -0. -b10010 / -b110100 0 -b1010110 1 -b1111000 2 -b10011010 3 -b10111100 4 -b11011110 5 -b11110000 6 -07 -18 -09 -1: -1; -0< -0= -1> -b0 ? -0@ -0A -b0 B -b0 C -b0 D -b0 E -b0 F -b0 G -b0 H -b0 I -b0 J -1K -0L -b10010 M -b110100 N -b1010110 O -b1111000 P -b10011010 Q -b10111100 R -b11011110 S -b11110000 T -0U -1V -0W -1X -1Y -0Z -0[ -1\ +b0 bS^uZ +b0 +MZoR +b0 buliE +b0 X1my. +b0 pmEg% +b0 J;&2w +b0 #'ZC$ +b0 zdBci +b0 !=66X +b0 -#Dd6 +b0 l}7)5 +b0 8,]`a +b0 yES{c +b0 ;J^L" +b0 qUI{d +b0 %U;af +b0 ~\!qw +b0 \K4+l +b0 V7%F. +b0 R@/Mx +b0 ,VoRT +b0 `L=0w +b0 kP[@C +b0 2^Xew +b0 O&Qy} +b0 YRUF" +b0 c_Q +b0 B$aO# +b0 .=-:e +b0 WqHtO +b0 \P/B8 +b0 ~f|@~ +b0 [xw38 +b0 ,mMiC +b0 T){Kr +b0 JCt-5 +b0 JJ`q% +b0 &8m;f +b0 .N&;O +b0 9CPW} +b0 ~cUnd +b0 S6,C. +b0 h,t%t +b0 M.'tT +b0 WH^lq +b0 wk@1l +b0 XPVW/ +b0 8i**= +b0 T7yLi +b0 xPnYC +b0 }Q=~y +0,Ca!' +0dJF\@ +b0 "w$'Q +b0 mIo&U +b0 LJ\m% +b0 `Zp>N +b0 YR.PG +b0 BZ&)B +b0 _$[8D +b0 tc)n] +b0 bs-Rg +1*T~2b +0}[YPW +b10010 6,aYz +b110100 Bq5kY +b1010110 :lN4y +b1111000 +9uC] +b10011010 /EG3; +b10111100 >=e$j +b11011110 >wz^~ +b11110000 CYt2z +0:.XL} +10b%VN +0*w)7y +11dg() +1s%B`l[ +b11110000 481V} +0E`@Pc +1Hm9Lt +0D@ZT~ +1%ZXkA +1dO-sf +0uE-x9 +0[w<$[ +1*7bb6 $end #250000 -1# -1. -1A -1L +1dJF\@ +1}[YPW +1pK0f; +1=[Eug #500000 #750000 -0# -0. -0A -0L +0dJF\@ +0}[YPW +0pK0f; +0=[Eug #1000000 -1" -b1 , -0- -b0 / -b0 0 -b0 1 -b0 2 -b0 3 -b0 4 -b0 5 -b0 6 -08 -0: -0; -0> -1@ -b1 J -0K -b0 M -b0 N -b0 O -b0 P -b0 Q -b0 R -b0 S -b0 T -0V -0X -0Y -0\ +1,Ca!' +b1 bs-Rg +0*T~2b +b0 6,aYz +b0 Bq5kY +b0 :lN4y +b0 +9uC] +b0 /EG3; +b0 >=e$j +b0 >wz^~ +b0 CYt2z +00b%VN +01dg() +0s%B`l[ +b0 481V} +0Hm9Lt +0%ZXkA +0dO-sf +0*7bb6 #1250000 -b0 ] -b110100 e -b0 m -b1111000 u -b10011010 } -b0 '" -b0 /" -b11110000 7" -1# -1. -1A -1L +b0 bS^uZ +b110100 +MZoR +b0 buliE +b1111000 X1my. +b10011010 pmEg% +b0 J;&2w +b0 #'ZC$ +b11110000 zdBci +1dJF\@ +1}[YPW +1pK0f; +1=[Eug #1500000 #1750000 -0# -0. -0A -0L +0dJF\@ +0}[YPW +0pK0f; +0=[Eug #2000000 #2250000 -1# -1. -1A -1L +1dJF\@ +1}[YPW +1pK0f; +1=[Eug #2500000 #2750000 -0# -0. -0A -0L +0dJF\@ +0}[YPW +0pK0f; +0=[Eug #3000000 -b0 , -1- -b11111110 / -b11011100 0 -b10111010 1 -b10011000 2 -b1110110 3 -b1010100 4 -b110010 5 -b10000 6 -17 -18 -19 -1: -1; -1< -1= -1> -b0 J -1K -b11111110 M -b11011100 N -b10111010 O -b10011000 P -b1110110 Q -b1010100 R -b110010 S -b10000 T -1U -1V -1W -1X -1Y -1Z -1[ -1\ +b0 bs-Rg +1*T~2b +b11111110 6,aYz +b11011100 Bq5kY +b10111010 :lN4y +b10011000 +9uC] +b1110110 /EG3; +b1010100 >=e$j +b110010 >wz^~ +b10000 CYt2z +1:.XL} +10b%VN +1*w)7y +11dg() +1s%B`l[ +b10000 481V} +1E`@Pc +1Hm9Lt +1D@ZT~ +1%ZXkA +1dO-sf +1uE-x9 +1[w<$[ +1*7bb6 #3250000 -1# -b110100 % -b1111000 ' -b10011010 ( -b11110000 + -1. -1A -b110100 C -b1111000 E -b10011010 F -b11110000 I -1L +1dJF\@ +b110100 mIo&U +b1111000 `Zp>N +b10011010 YR.PG +b11110000 tc)n] +1}[YPW +1pK0f; +b110100 q-WOU +b1111000 P,^c) +b10011010 s?0AD +b11110000 ZqG9i +1=[Eug #3500000 #3750000 -0# -0. -0A -0L +0dJF\@ +0}[YPW +0pK0f; +0=[Eug #4000000 #4250000 -b11111110 ] -b11011100 e -b10111010 m -b10011000 u -b1110110 } -b1010100 '" -b110010 /" -b10000 7" -1# -1. -1A -1L +b11111110 bS^uZ +b11011100 +MZoR +b10111010 buliE +b10011000 X1my. +b1110110 pmEg% +b1010100 J;&2w +b110010 #'ZC$ +b10000 zdBci +1dJF\@ +1}[YPW +1pK0f; +1=[Eug #4500000 #4750000 -0# -0. -0A -0L +0dJF\@ +0}[YPW +0pK0f; +0=[Eug #5000000 #5250000 -b11111110 ] -b11011100 e -b10111010 m -b10011000 u -b1110110 } -b1010100 '" -b110010 /" -b10000 7" -1# -1. -1A -1L +b11111110 bS^uZ +b11011100 +MZoR +b10111010 buliE +b10011000 X1my. +b1110110 pmEg% +b1010100 J;&2w +b110010 #'ZC$ +b10000 zdBci +1dJF\@ +1}[YPW +1pK0f; +1=[Eug #5500000 #5750000 -0# -0. -0A -0L +0dJF\@ +0}[YPW +0pK0f; +0=[Eug #6000000 -0" -b1 , -b10011 / -b1010111 0 -b10011011 1 -b11011111 2 -b10 3 -b1000110 4 -b10001010 5 -b11001110 6 -0@ -b1 J -b10011 M -b1010111 N -b10011011 O -b11011111 P -b10 Q -b1000110 R -b10001010 S -b11001110 T +0,Ca!' +b1 bs-Rg +b10011 6,aYz +b1010111 Bq5kY +b10011011 :lN4y +b11011111 +9uC] +b10 /EG3; +b1000110 >=e$j +b10001010 >wz^~ +b11001110 CYt2z +0]ky*D +b1 iuiB`l[ +b11001110 481V} #6250000 -b11111110 ] -b11011100 e -b10111010 m -b10011000 u -b1110110 } -b1010100 '" -b110010 /" -b10000 7" -1# -b11111110 $ -b11011100 % -b10111010 & -b10011000 ' -b1110110 ( -b1010100 ) -b110010 * -b10000 + -1. -1A -b11111110 B -b11011100 C -b10111010 D -b10011000 E -b1110110 F -b1010100 G -b110010 H -b10000 I -1L +b11111110 bS^uZ +b11011100 +MZoR +b10111010 buliE +b10011000 X1my. +b1110110 pmEg% +b1010100 J;&2w +b110010 #'ZC$ +b10000 zdBci +1dJF\@ +b11111110 "w$'Q +b11011100 mIo&U +b10111010 LJ\m% +b10011000 `Zp>N +b1110110 YR.PG +b1010100 BZ&)B +b110010 _$[8D +b10000 tc)n] +1}[YPW +1pK0f; +b11111110 Wz+1. +b11011100 q-WOU +b10111010 ,iWd9 +b10011000 P,^c) +b1110110 s?0AD +b1010100 {,&!. +b110010 0~wS+ +b10000 ZqG9i +1=[Eug #6500000 #6750000 -0# -0. -0A -0L +0dJF\@ +0}[YPW +0pK0f; +0=[Eug #7000000 -b10 , -b1110100 / -b1100101 0 -b1110011 1 -b1110100 2 -b1101001 3 -b1101110 4 -b1100111 5 -b100001 6 -b10 J -b1110100 M -b1100101 N -b1110011 O -b1110100 P -b1101001 Q -b1101110 R -b1100111 S -b100001 T +b10 bs-Rg +b1110100 6,aYz +b1100101 Bq5kY +b1110011 :lN4y +b1110100 +9uC] +b1101001 /EG3; +b1101110 >=e$j +b1100111 >wz^~ +b100001 CYt2z +b10 iuiB`l[ +b100001 481V} #7250000 -b10011 ^ -b1010111 f -b10011011 n -b11011111 v -b10 ~ -b1000110 (" -b10001010 0" -b11001110 8" -1# -b0 $ -b0 % -b0 & -b0 ' -b0 ( -b0 ) -b0 * -b0 + -1. -1A -b0 B -b0 C -b0 D -b0 E -b0 F -b0 G -b0 H -b0 I -1L +b10011 !=66X +b1010111 -#Dd6 +b10011011 l}7)5 +b11011111 8,]`a +b10 yES{c +b1000110 ;J^L" +b10001010 qUI{d +b11001110 %U;af +1dJF\@ +b0 "w$'Q +b0 mIo&U +b0 LJ\m% +b0 `Zp>N +b0 YR.PG +b0 BZ&)B +b0 _$[8D +b0 tc)n] +1}[YPW +1pK0f; +b0 Wz+1. +b0 q-WOU +b0 ,iWd9 +b0 P,^c) +b0 s?0AD +b0 {,&!. +b0 0~wS+ +b0 ZqG9i +1=[Eug #7500000 #7750000 -0# -0. -0A -0L +0dJF\@ +0}[YPW +0pK0f; +0=[Eug #8000000 -b11 , -b1101101 / -b1101111 0 -b1110010 1 -b1100101 2 -b100000 3 -b1110100 4 -b1110011 5 -b1110100 6 -b11 J -b1101101 M -b1101111 N -b1110010 O -b1100101 P -b100000 Q -b1110100 R -b1110011 S -b1110100 T +b11 bs-Rg +b1101101 6,aYz +b1101111 Bq5kY +b1110010 :lN4y +b1100101 +9uC] +b100000 /EG3; +b1110100 >=e$j +b1110011 >wz^~ +b1110100 CYt2z +b11 iuiB`l[ +b1110100 481V} #8250000 -b1110100 _ -b1100101 g -b1110011 o -b1110100 w -b1101001 !" -b1101110 )" -b1100111 1" -b100001 9" -1# -1. -1A -1L +b1110100 ~\!qw +b1100101 \K4+l +b1110011 V7%F. +b1110100 R@/Mx +b1101001 ,VoRT +b1101110 `L=0w +b1100111 kP[@C +b100001 2^Xew +1dJF\@ +1}[YPW +1pK0f; +1=[Eug #8500000 #8750000 -0# -0. -0A -0L +0dJF\@ +0}[YPW +0pK0f; +0=[Eug #9000000 -1" -b0 , -0- -b0 / -b0 0 -b0 1 -b0 2 -b0 3 -b0 4 -b0 5 -b0 6 -07 -08 -09 -0: -0; -0< -0= -0> -1@ -b0 J -0K -b0 M -b0 N -b0 O -b0 P -b0 Q -b0 R -b0 S -b0 T -0U -0V -0W -0X -0Y -0Z -0[ -0\ +1,Ca!' +b0 bs-Rg +0*T~2b +b0 6,aYz +b0 Bq5kY +b0 :lN4y +b0 +9uC] +b0 /EG3; +b0 >=e$j +b0 >wz^~ +b0 CYt2z +0:.XL} +00b%VN +0*w)7y +01dg() +0s%B`l[ +b0 481V} +0E`@Pc +0Hm9Lt +0D@ZT~ +0%ZXkA +0dO-sf +0uE-x9 +0[w<$[ +0*7bb6 #9250000 -b1101101 ` -b1101111 h -b1110010 p -b1100101 x -b100000 "" -b1110100 *" -b1110011 2" -b1110100 :" -1# -1. -1A -1L +b1101101 O&Qy} +b1101111 YRUF" +b1110010 N +b1110110 YR.PG +b1010100 BZ&)B +b110010 _$[8D +b10000 tc)n] +1}[YPW +1pK0f; +b11111110 Wz+1. +b11011100 q-WOU +b10111010 ,iWd9 +b10011000 P,^c) +b1110110 s?0AD +b1010100 {,&!. +b110010 0~wS+ +b10000 ZqG9i +1=[Eug #10500000 #10750000 -0# -0. -0A -0L +0dJF\@ +0}[YPW +0pK0f; +0=[Eug #11000000 -b10 ! -b10 ? +b10 }Q=~y +b10 ]7,pz #11250000 -1# -b10011 $ -b1010111 % -b10011011 & -b11011111 ' -b10 ( -b1000110 ) -b10001010 * -b11001110 + -1. -1A -b10011 B -b1010111 C -b10011011 D -b11011111 E -b10 F -b1000110 G -b10001010 H -b11001110 I -1L +1dJF\@ +b10011 "w$'Q +b1010111 mIo&U +b10011011 LJ\m% +b11011111 `Zp>N +b10 YR.PG +b1000110 BZ&)B +b10001010 _$[8D +b11001110 tc)n] +1}[YPW +1pK0f; +b10011 Wz+1. +b1010111 q-WOU +b10011011 ,iWd9 +b11011111 P,^c) +b10 s?0AD +b1000110 {,&!. +b10001010 0~wS+ +b11001110 ZqG9i +1=[Eug #11500000 #11750000 -0# -0. -0A -0L +0dJF\@ +0}[YPW +0pK0f; +0=[Eug #12000000 -b11 ! -b11 ? +b11 }Q=~y +b11 ]7,pz #12250000 -1# -b1110100 $ -b1100101 % -b1110011 & -b1110100 ' -b1101001 ( -b1101110 ) -b1100111 * -b100001 + -1. -1A -b1110100 B -b1100101 C -b1110011 D -b1110100 E -b1101001 F -b1101110 G -b1100111 H -b100001 I -1L +1dJF\@ +b1110100 "w$'Q +b1100101 mIo&U +b1110011 LJ\m% +b1110100 `Zp>N +b1101001 YR.PG +b1101110 BZ&)B +b1100111 _$[8D +b100001 tc)n] +1}[YPW +1pK0f; +b1110100 Wz+1. +b1100101 q-WOU +b1110011 ,iWd9 +b1110100 P,^c) +b1101001 s?0AD +b1101110 {,&!. +b1100111 0~wS+ +b100001 ZqG9i +1=[Eug #12500000 #12750000 -0# -0. -0A -0L +0dJF\@ +0}[YPW +0pK0f; +0=[Eug #13000000 -b0 ! -0" -b0 ? -0@ +b0 }Q=~y +0,Ca!' +b0 ]7,pz +0]ky*D #13250000 -1# -b1101101 $ -b1101111 % -b1110010 & -b1100101 ' -b100000 ( -b1110100 ) -b1110011 * -b1110100 + -1. -1A -b1101101 B -b1101111 C -b1110010 D -b1100101 E -b100000 F -b1110100 G -b1110011 H -b1110100 I -1L +1dJF\@ +b1101101 "w$'Q +b1101111 mIo&U +b1110010 LJ\m% +b1100101 `Zp>N +b100000 YR.PG +b1110100 BZ&)B +b1110011 _$[8D +b1110100 tc)n] +1}[YPW +1pK0f; +b1101101 Wz+1. +b1101111 q-WOU +b1110010 ,iWd9 +b1100101 P,^c) +b100000 s?0AD +b1110100 {,&!. +b1110011 0~wS+ +b1110100 ZqG9i +1=[Eug #13500000 #13750000 -0# -0. -0A -0L +0dJF\@ +0}[YPW +0pK0f; +0=[Eug #14000000 #14250000 -1# -b0 $ -b0 % -b0 & -b0 ' -b0 ( -b0 ) -b0 * -b0 + -1. -1A -b0 B -b0 C -b0 D -b0 E -b0 F -b0 G -b0 H -b0 I -1L +1dJF\@ +b0 "w$'Q +b0 mIo&U +b0 LJ\m% +b0 `Zp>N +b0 YR.PG +b0 BZ&)B +b0 _$[8D +b0 tc)n] +1}[YPW +1pK0f; +b0 Wz+1. +b0 q-WOU +b0 ,iWd9 +b0 P,^c) +b0 s?0AD +b0 {,&!. +b0 0~wS+ +b0 ZqG9i +1=[Eug #14500000 #14750000 -0# -0. -0A -0L +0dJF\@ +0}[YPW +0pK0f; +0=[Eug #15000000 diff --git a/crates/fayalite/tests/sim/expected/mod1.txt b/crates/fayalite/tests/sim/expected/mod1.txt index 3f7a55e..a1de89a 100644 --- a/crates/fayalite/tests/sim/expected/mod1.txt +++ b/crates/fayalite/tests/sim/expected/mod1.txt @@ -445,6 +445,7 @@ Simulation { index: StatePartIndex(0), ty: UInt<4>, }, + maybe_changed: true, state: 0xa, last_state: 0x3, }, @@ -454,6 +455,7 @@ Simulation { index: StatePartIndex(1), ty: SInt<2>, }, + maybe_changed: true, state: 0x2, last_state: 0x3, }, @@ -463,6 +465,7 @@ Simulation { index: StatePartIndex(2), ty: SInt<2>, }, + maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -472,6 +475,7 @@ Simulation { index: StatePartIndex(3), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xe, }, @@ -481,6 +485,7 @@ Simulation { index: StatePartIndex(8), ty: UInt<4>, }, + maybe_changed: true, state: 0xa, last_state: 0x3, }, @@ -490,6 +495,7 @@ Simulation { index: StatePartIndex(9), ty: SInt<2>, }, + maybe_changed: true, state: 0x2, last_state: 0x3, }, @@ -499,6 +505,7 @@ Simulation { index: StatePartIndex(10), ty: SInt<2>, }, + maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -508,6 +515,7 @@ Simulation { index: StatePartIndex(11), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xe, }, @@ -517,6 +525,7 @@ Simulation { index: StatePartIndex(4), ty: UInt<4>, }, + maybe_changed: true, state: 0xa, last_state: 0x3, }, @@ -526,6 +535,7 @@ Simulation { index: StatePartIndex(5), ty: SInt<2>, }, + maybe_changed: true, state: 0x2, last_state: 0x3, }, @@ -535,6 +545,7 @@ Simulation { index: StatePartIndex(6), ty: SInt<2>, }, + maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -544,6 +555,7 @@ Simulation { index: StatePartIndex(7), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xe, }, diff --git a/crates/fayalite/tests/sim/expected/mod1.vcd b/crates/fayalite/tests/sim/expected/mod1.vcd index 0d1a6f4..b12db8f 100644 --- a/crates/fayalite/tests/sim/expected/mod1.vcd +++ b/crates/fayalite/tests/sim/expected/mod1.vcd @@ -1,47 +1,34 @@ $timescale 1 ps $end $scope module mod1 $end $scope struct o $end -$var wire 4 ! i $end -$var wire 2 " o $end -$var wire 2 # i2 $end -$var wire 4 $ o2 $end +$var wire 4 avK(^ i $end +$var wire 2 Q2~aG o $end +$var wire 2 DXK'| i2 $end +$var wire 4 cPuix o2 $end $upscope $end -$scope struct child $end -$var wire 4 ) i $end -$var wire 2 * o $end -$var wire 2 + i2 $end -$var wire 4 , o2 $end -$upscope $end -$scope module mod1_child $end -$var wire 4 % i $end -$var wire 2 & o $end -$var wire 2 ' i2 $end -$var wire 4 ( o2 $end +$scope module child $end +$var wire 4 ($5K7 i $end +$var wire 2 %6Wv" o $end +$var wire 2 +|-AU i2 $end +$var wire 4 Hw?%j o2 $end $upscope $end $upscope $end $enddefinitions $end $dumpvars -b11 ! -b11 " -b10 # -b1110 $ -b11 % -b11 & -b10 ' -b1110 ( -b11 ) -b11 * -b10 + -b1110 , +b11 avK(^ +b11 Q2~aG +b10 DXK'| +b1110 cPuix +b11 ($5K7 +b11 %6Wv" +b10 +|-AU +b1110 Hw?%j $end #1000000 -b1010 ! -b10 " -b1111 $ -b1010 % -b10 & -b1111 ( -b1010 ) -b10 * -b1111 , +b1010 avK(^ +b10 Q2~aG +b1111 cPuix +b1010 ($5K7 +b10 %6Wv" +b1111 Hw?%j #2000000 diff --git a/crates/fayalite/tests/sim/expected/phantom_const.txt b/crates/fayalite/tests/sim/expected/phantom_const.txt index 94072ac..c9adae4 100644 --- a/crates/fayalite/tests/sim/expected/phantom_const.txt +++ b/crates/fayalite/tests/sim/expected/phantom_const.txt @@ -373,6 +373,7 @@ Simulation { ["a","b"], ), }, + maybe_changed: true, state: PhantomConst, last_state: PhantomConst, }, @@ -383,6 +384,7 @@ Simulation { ["a","b"], ), }, + maybe_changed: true, state: PhantomConst, last_state: PhantomConst, }, @@ -392,6 +394,7 @@ Simulation { index: StatePartIndex(0), ty: UInt<0>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -400,6 +403,7 @@ Simulation { kind: BigBool { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -408,6 +412,7 @@ Simulation { kind: BigClock { index: StatePartIndex(2), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -418,6 +423,7 @@ Simulation { "mem_element", ), }, + maybe_changed: true, state: PhantomConst, last_state: PhantomConst, }, diff --git a/crates/fayalite/tests/sim/expected/phantom_const.vcd b/crates/fayalite/tests/sim/expected/phantom_const.vcd index ba3869b..8611124 100644 --- a/crates/fayalite/tests/sim/expected/phantom_const.vcd +++ b/crates/fayalite/tests/sim/expected/phantom_const.vcd @@ -1,31 +1,31 @@ $timescale 1 ps $end $scope module phantom_const $end $scope struct out $end -$var string 1 ! \[0] $end -$var string 1 " \[1] $end +$var string 1 Ru)8A \[0] $end +$var string 1 y&ssi \[1] $end $upscope $end $scope struct mem $end $scope struct contents $end $scope struct \[0] $end -$var string 1 ' mem $end +$var string 1 =+olp mem $end $upscope $end $upscope $end $scope struct r0 $end -$var string 0 # addr $end -$var wire 1 $ en $end -$var wire 1 % clk $end -$var string 1 & data $end +$var string 0 U5SS1 addr $end +$var wire 1 rx@_T en $end +$var wire 1 o[(us clk $end +$var string 1 %Bg(6 data $end $upscope $end $upscope $end $upscope $end $enddefinitions $end $dumpvars -s0 ' -sPhantomConst([\"a\",\"b\"]) ! -sPhantomConst([\"a\",\"b\"]) " -s0 # -0$ -0% -sPhantomConst(\"mem_element\") & +s0 =+olp +sPhantomConst([\"a\",\"b\"]) Ru)8A +sPhantomConst([\"a\",\"b\"]) y&ssi +s0 U5SS1 +0rx@_T +0o[(us +sPhantomConst(\"mem_element\") %Bg(6 $end #1000000 diff --git a/crates/fayalite/tests/sim/expected/queue_1_false_false.txt b/crates/fayalite/tests/sim/expected/queue_1_false_false.txt new file mode 100644 index 0000000..e349bbd --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_1_false_false.txt @@ -0,0 +1,2164 @@ +Simulation { + state: State { + insns: Insns { + state_layout: StateLayout { + ty: TypeLayout { + small_slots: StatePartLayout { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 70, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count_lower", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 1>, + data: [ + // len = 0x1 + [0x0]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + dest_width: 1, + }, + 1: CastToUInt { + dest: StatePartIndex(68), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 0, + }, + // at: ready_valid.rs:178:13 + 2: Copy { + dest: StatePartIndex(66), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<0> }, + src: StatePartIndex(68), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 3: CastToUInt { + dest: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(66), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<0> }, + dest_width: 1, + }, + 4: Const { + dest: StatePartIndex(63), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x1, + }, + 5: CastToUInt { + dest: StatePartIndex(64), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(63), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 1, + }, + 6: Const { + dest: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x0, + }, + 7: CmpEq { + dest: StatePartIndex(57), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + }, + 8: CmpEq { + dest: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + }, + 9: Const { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + value: 0x0, + }, + 10: Copy { + dest: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + }, + 11: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 12: Add { + dest: StatePartIndex(58), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 13: CastToUInt { + dest: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(58), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 0, + }, + 14: Add { + dest: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 15: CastToUInt { + dest: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 0, + }, + 16: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 17: Copy { + dest: StatePartIndex(42), // (0x19) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 18: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 19: Copy { + dest: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<0> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:114:5 + 20: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 21: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 22: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 23: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 24: Copy { + dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<0> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 25: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 26: CmpEq { + dest: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:104:5 + 27: Copy { + dest: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 28: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 29: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 30: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 31: And { + dest: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 32: Copy { + dest: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 33: NotU { + dest: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 34: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 35: BranchIfZero { + target: 38, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 36: BranchIfZero { + target: 38, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 37: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<1> }, + src: StatePartIndex(64), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:88:26 + 38: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 39: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 40: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:84:31 + 41: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 42: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 43: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 44: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 45: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 46: CastToUInt { + dest: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 1, + }, + // at: ready_valid.rs:166:5 + 47: BranchIfZero { + target: 50, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 48: BranchIfNonZero { + target: 50, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 49: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<1> }, + src: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:166:5 + 50: BranchIfNonZero { + target: 52, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:182:13 + 51: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<1> }, + src: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:91:19 + 52: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<0> }, + }, + 53: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 54: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 55: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<0> }, + }, + 56: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 57: BranchIfSmallZero { + target: 60, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 58: MemoryReadUInt { + dest: StatePartIndex(14), // (0x19) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 1>, + // data: [ + // // len = 0x1 + // [0x0]: 0x19, + // ], + // }) (), + addr: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + stride: 8, + start: 0, + width: 8, + }, + 59: Branch { + target: 61, + }, + 60: Const { + dest: StatePartIndex(14), // (0x19) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 61: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 62: Copy { + dest: StatePartIndex(47), // (0x19) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x19) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 63: Shl { + dest: StatePartIndex(49), // (0x32) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x19) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 64: Or { + dest: StatePartIndex(50), // (0x33) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x32) SlotDebugData { name: "", ty: UInt<9> }, + }, + 65: CastToUInt { + dest: StatePartIndex(51), // (0x33) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x33) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 66: Copy { + dest: StatePartIndex(52), // (0x33) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x33) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 67: BranchIfZero { + target: 69, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 68: Copy { + dest: StatePartIndex(6), // (0x33) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x33) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 69: BranchIfNonZero { + target: 71, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:136:13 + 70: Copy { + dest: StatePartIndex(6), // (0x33) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 71: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 72: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 73: Copy { + dest: StatePartIndex(8), // (0x33) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x33) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 74: SliceInt { + dest: StatePartIndex(9), // (0x19) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x33) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 75: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x33) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 76: BranchIfSmallNeImmediate { + target: 78, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 77: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 78: BranchIfSmallNeImmediate { + target: 80, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 79: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 80: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 81: BranchIfZero { + target: 86, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 82: BranchIfZero { + target: 84, + value: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 83: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:158:9 + 84: BranchIfNonZero { + target: 86, + value: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 85: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 86: Copy { + dest: StatePartIndex(4), // (0x33) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x33) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 87: SliceInt { + dest: StatePartIndex(5), // (0x19) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x33) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 88: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x33) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 89: BranchIfSmallNeImmediate { + target: 91, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 90: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 91: BranchIfSmallNeImmediate { + target: 93, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 92: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 93: Copy { + dest: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 94: Copy { + dest: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 95: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 96: CmpNe { + dest: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 97: BranchIfZero { + target: 99, + value: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 98: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 99: BranchIfZero { + target: 104, + value: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 100: BranchIfZero { + target: 102, + value: StatePartIndex(57), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 101: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:148:9 + 102: BranchIfNonZero { + target: 104, + value: StatePartIndex(57), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 103: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:118:30 + 104: BranchIfSmallNeImmediate { + target: 106, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 105: Copy { + dest: StatePartIndex(42), // (0x19) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x19) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 106: Copy { + dest: StatePartIndex(18), // (0x19) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x19) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 107: BranchIfSmallZero { + target: 112, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 108: BranchIfSmallNonZero { + target: 111, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 109: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + src: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + }, + 110: Branch { + target: 112, + }, + 111: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:86:25 + 112: BranchIfSmallZero { + target: 117, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 113: BranchIfSmallNonZero { + target: 116, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 114: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + src: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + }, + 115: Branch { + target: 117, + }, + 116: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:88:26 + 117: BranchIfSmallZero { + target: 122, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 118: BranchIfSmallNonZero { + target: 121, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 119: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 120: Branch { + target: 122, + }, + 121: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 122: BranchIfSmallZero { + target: 123, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 123: BranchIfSmallZero { + target: 131, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 124: CopySmall { + dest: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + }, + 125: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 126: Copy { + dest: StatePartIndex(20), // (0x19) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x19) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 127: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 128: BranchIfSmallZero { + target: 131, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 129: BranchIfZero { + target: 131, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 130: MemoryWriteUInt { + value: StatePartIndex(20), // (0x19) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 1>, + // data: [ + // // len = 0x1 + // [0x0]: 0x19, + // ], + // }) (), + addr: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + stride: 8, + start: 0, + width: 8, + }, + 131: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 132: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 133: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 134: Return, + ], + .. + }, + pc: 134, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 1>, + data: [ + // len = 0x1 + [0x0]: 0x19, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 51, + 0, + 51, + 25, + 51, + 0, + 51, + 25, + 1, + 0, + 1, + 0, + 25, + 0, + 0, + 0, + 25, + 1, + 25, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 25, + 0, + 0, + 1, + 1, + 25, + 1, + 50, + 51, + 51, + 51, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<1>, + flow: Sink, + }, + ty: UInt<1>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 1, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + }, + ], + array_type: Array, 1>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<0>, + flow: Duplex, + }, + ty: UInt<0>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<0>, + flow: Duplex, + }, + ty: UInt<0>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + TraceWire { + name: "count_lower", + child: TraceUInt { + location: TraceScalarId(29), + name: "count_lower", + ty: UInt<0>, + flow: Duplex, + }, + ty: UInt<0>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x19, + last_state: 0x19, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x19, + last_state: 0x19, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<1>, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<0>, + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x19, + last_state: 0x19, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<0>, + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x19, + last_state: 0x19, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<0>, + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<0>, + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x19, + last_state: 0x19, + }, + SimTrace { + id: TraceScalarId(29), + kind: BigUInt { + index: StatePartIndex(66), + ty: UInt<0>, + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 1, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + }, + ], + array_type: Array, 1>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_1_false_false.vcd b/crates/fayalite/tests/sim/expected/queue_1_false_false.vcd new file mode 100644 index 0000000..30dbbec --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_1_false_false.vcd @@ -0,0 +1,1916 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 1 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var string 0 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var string 0 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var string 0 Xk?#v inp_index_reg $end +$var string 0 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 68, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count_lower", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 1>, + data: [ + // len = 0x1 + [0x0]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + dest_width: 1, + }, + 1: CastToUInt { + dest: StatePartIndex(66), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 0, + }, + // at: ready_valid.rs:178:13 + 2: Copy { + dest: StatePartIndex(64), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<0> }, + src: StatePartIndex(66), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 3: CastToUInt { + dest: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(64), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<0> }, + dest_width: 1, + }, + 4: Const { + dest: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x1, + }, + 5: CastToUInt { + dest: StatePartIndex(62), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 1, + }, + 6: Const { + dest: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x0, + }, + 7: CmpEq { + dest: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + }, + 8: CmpEq { + dest: StatePartIndex(58), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + }, + 9: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 10: Add { + dest: StatePartIndex(56), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 11: CastToUInt { + dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(56), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 0, + }, + 12: Add { + dest: StatePartIndex(59), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 13: CastToUInt { + dest: StatePartIndex(60), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(59), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 0, + }, + 14: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 15: Copy { + dest: StatePartIndex(42), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 16: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 17: Copy { + dest: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<0> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:114:5 + 18: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 19: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 20: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 21: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 22: Copy { + dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<0> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 23: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 24: CmpEq { + dest: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:104:5 + 25: Copy { + dest: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 26: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 27: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 28: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 29: And { + dest: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 30: Copy { + dest: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 31: NotU { + dest: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 32: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 33: BranchIfZero { + target: 36, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 34: BranchIfZero { + target: 36, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 35: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<1> }, + src: StatePartIndex(62), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:88:26 + 36: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 37: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 38: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:84:31 + 39: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 40: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 41: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 42: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 43: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 44: CastToUInt { + dest: StatePartIndex(63), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 1, + }, + // at: ready_valid.rs:166:5 + 45: BranchIfZero { + target: 48, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 46: BranchIfNonZero { + target: 48, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 47: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<1> }, + src: StatePartIndex(63), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:166:5 + 48: BranchIfNonZero { + target: 50, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:182:13 + 49: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<1> }, + src: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:91:19 + 50: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<0> }, + }, + 51: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 52: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 53: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<0> }, + }, + 54: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 55: BranchIfSmallZero { + target: 58, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 56: MemoryReadUInt { + dest: StatePartIndex(14), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 1>, + // data: [ + // // len = 0x1 + // [0x0]: 0x1f, + // ], + // }) (), + addr: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + stride: 8, + start: 0, + width: 8, + }, + 57: Branch { + target: 59, + }, + 58: Const { + dest: StatePartIndex(14), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 59: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 60: Copy { + dest: StatePartIndex(47), // (0x1f) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 61: Shl { + dest: StatePartIndex(49), // (0x3e) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x1f) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 62: Or { + dest: StatePartIndex(50), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x3e) SlotDebugData { name: "", ty: UInt<9> }, + }, + 63: CastToUInt { + dest: StatePartIndex(51), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 64: Copy { + dest: StatePartIndex(52), // (0x3f) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 65: BranchIfZero { + target: 67, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 66: Copy { + dest: StatePartIndex(6), // (0x3f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x3f) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 67: BranchIfNonZero { + target: 69, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:134:13 + 68: Copy { + dest: StatePartIndex(6), // (0x3f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(2), // (0x3f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 69: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 70: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 71: Copy { + dest: StatePartIndex(8), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x3f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 72: SliceInt { + dest: StatePartIndex(9), // (0x1f) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 73: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x3f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 74: BranchIfSmallNeImmediate { + target: 76, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 75: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 76: BranchIfSmallNeImmediate { + target: 78, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 77: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 78: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 79: BranchIfZero { + target: 84, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 80: BranchIfZero { + target: 82, + value: StatePartIndex(58), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 81: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:158:9 + 82: BranchIfNonZero { + target: 84, + value: StatePartIndex(58), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 83: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(60), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 84: Copy { + dest: StatePartIndex(4), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x3f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 85: SliceInt { + dest: StatePartIndex(5), // (0x1f) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 86: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x3f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 87: BranchIfSmallNeImmediate { + target: 89, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 88: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 89: BranchIfSmallNeImmediate { + target: 91, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 90: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 91: Copy { + dest: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 92: Copy { + dest: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 93: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 94: CmpNe { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 95: BranchIfZero { + target: 97, + value: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 96: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 97: BranchIfZero { + target: 102, + value: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 98: BranchIfZero { + target: 100, + value: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 99: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:148:9 + 100: BranchIfNonZero { + target: 102, + value: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 101: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:118:30 + 102: BranchIfSmallNeImmediate { + target: 104, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 103: Copy { + dest: StatePartIndex(42), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x1f) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 104: Copy { + dest: StatePartIndex(18), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 105: BranchIfSmallZero { + target: 110, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 106: BranchIfSmallNonZero { + target: 109, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 107: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + src: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + }, + 108: Branch { + target: 110, + }, + 109: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:86:25 + 110: BranchIfSmallZero { + target: 115, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 111: BranchIfSmallNonZero { + target: 114, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 112: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + src: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + }, + 113: Branch { + target: 115, + }, + 114: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:88:26 + 115: BranchIfSmallZero { + target: 120, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 116: BranchIfSmallNonZero { + target: 119, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 117: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 118: Branch { + target: 120, + }, + 119: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 120: BranchIfSmallZero { + target: 121, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 121: BranchIfSmallZero { + target: 129, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 122: CopySmall { + dest: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + }, + 123: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 124: Copy { + dest: StatePartIndex(20), // (0x1f) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 125: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 126: BranchIfSmallZero { + target: 129, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 127: BranchIfZero { + target: 129, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 128: MemoryWriteUInt { + value: StatePartIndex(20), // (0x1f) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 1>, + // data: [ + // // len = 0x1 + // [0x0]: 0x1f, + // ], + // }) (), + addr: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + stride: 8, + start: 0, + width: 8, + }, + 129: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 130: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 131: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 132: Return, + ], + .. + }, + pc: 132, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 1>, + data: [ + // len = 0x1 + [0x0]: 0x1f, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 63, + 0, + 63, + 31, + 63, + 0, + 63, + 31, + 1, + 0, + 1, + 0, + 31, + 0, + 0, + 0, + 31, + 1, + 31, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 31, + 0, + 0, + 1, + 1, + 31, + 1, + 62, + 63, + 63, + 63, + 0, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<1>, + flow: Sink, + }, + ty: UInt<1>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 1, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + }, + ], + array_type: Array, 1>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<0>, + flow: Duplex, + }, + ty: UInt<0>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<0>, + flow: Duplex, + }, + ty: UInt<0>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + TraceWire { + name: "count_lower", + child: TraceUInt { + location: TraceScalarId(29), + name: "count_lower", + ty: UInt<0>, + flow: Duplex, + }, + ty: UInt<0>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x1f, + last_state: 0x1f, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x1f, + last_state: 0x1f, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<1>, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<0>, + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x1f, + last_state: 0x1f, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<0>, + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x1f, + last_state: 0x1f, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<0>, + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<0>, + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x1f, + last_state: 0x1f, + }, + SimTrace { + id: TraceScalarId(29), + kind: BigUInt { + index: StatePartIndex(64), + ty: UInt<0>, + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 1, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + }, + ], + array_type: Array, 1>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_1_false_true.vcd b/crates/fayalite/tests/sim/expected/queue_1_false_true.vcd new file mode 100644 index 0000000..cc36d02 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_1_false_true.vcd @@ -0,0 +1,1836 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 1 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var string 0 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var string 0 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var string 0 Xk?#v inp_index_reg $end +$var string 0 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 70, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count_lower", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 1>, + data: [ + // len = 0x1 + [0x0]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + dest_width: 1, + }, + 1: CastToUInt { + dest: StatePartIndex(68), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 0, + }, + // at: ready_valid.rs:178:13 + 2: Copy { + dest: StatePartIndex(66), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<0> }, + src: StatePartIndex(68), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 3: CastToUInt { + dest: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(66), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<0> }, + dest_width: 1, + }, + 4: Const { + dest: StatePartIndex(63), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x1, + }, + 5: CastToUInt { + dest: StatePartIndex(64), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(63), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 1, + }, + 6: Const { + dest: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x0, + }, + 7: CmpEq { + dest: StatePartIndex(57), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + }, + 8: CmpEq { + dest: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + }, + 9: Const { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + value: 0x0, + }, + 10: Copy { + dest: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + }, + 11: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 12: Add { + dest: StatePartIndex(58), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 13: CastToUInt { + dest: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(58), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 0, + }, + 14: Add { + dest: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 15: CastToUInt { + dest: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 0, + }, + 16: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 17: Copy { + dest: StatePartIndex(42), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 18: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 19: Copy { + dest: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<0> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:114:5 + 20: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 21: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 22: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 23: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 24: Copy { + dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<0> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 25: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 26: CmpEq { + dest: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:104:5 + 27: Copy { + dest: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 28: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 29: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 30: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 31: And { + dest: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 32: Copy { + dest: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 33: NotU { + dest: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 34: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:124:9 + 35: BranchIfZero { + target: 37, + value: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:125:13 + 36: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 37: BranchIfZero { + target: 40, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 38: BranchIfZero { + target: 40, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 39: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<1> }, + src: StatePartIndex(64), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:88:26 + 40: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 41: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 42: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:84:31 + 43: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 44: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 45: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 46: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 47: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 48: CastToUInt { + dest: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 1, + }, + // at: ready_valid.rs:166:5 + 49: BranchIfZero { + target: 52, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 50: BranchIfNonZero { + target: 52, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 51: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<1> }, + src: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:166:5 + 52: BranchIfNonZero { + target: 54, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:182:13 + 53: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<1> }, + src: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:91:19 + 54: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<0> }, + }, + 55: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 56: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 57: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<0> }, + }, + 58: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 59: BranchIfSmallZero { + target: 62, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 60: MemoryReadUInt { + dest: StatePartIndex(14), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 1>, + // data: [ + // // len = 0x1 + // [0x0]: 0x1f, + // ], + // }) (), + addr: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + stride: 8, + start: 0, + width: 8, + }, + 61: Branch { + target: 63, + }, + 62: Const { + dest: StatePartIndex(14), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 63: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 64: Copy { + dest: StatePartIndex(47), // (0x1f) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 65: Shl { + dest: StatePartIndex(49), // (0x3e) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x1f) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 66: Or { + dest: StatePartIndex(50), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x3e) SlotDebugData { name: "", ty: UInt<9> }, + }, + 67: CastToUInt { + dest: StatePartIndex(51), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 68: Copy { + dest: StatePartIndex(52), // (0x3f) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 69: BranchIfZero { + target: 71, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 70: Copy { + dest: StatePartIndex(6), // (0x3f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x3f) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 71: BranchIfNonZero { + target: 73, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:136:13 + 72: Copy { + dest: StatePartIndex(6), // (0x3f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 73: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 74: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 75: Copy { + dest: StatePartIndex(8), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x3f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 76: SliceInt { + dest: StatePartIndex(9), // (0x1f) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 77: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x3f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 78: BranchIfSmallNeImmediate { + target: 80, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 79: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 80: BranchIfSmallNeImmediate { + target: 82, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 81: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 82: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 83: BranchIfZero { + target: 88, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 84: BranchIfZero { + target: 86, + value: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 85: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:158:9 + 86: BranchIfNonZero { + target: 88, + value: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 87: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 88: Copy { + dest: StatePartIndex(4), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x3f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 89: SliceInt { + dest: StatePartIndex(5), // (0x1f) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 90: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x3f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 91: BranchIfSmallNeImmediate { + target: 93, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 92: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 93: BranchIfSmallNeImmediate { + target: 95, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 94: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 95: Copy { + dest: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 96: Copy { + dest: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 97: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 98: CmpNe { + dest: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 99: BranchIfZero { + target: 101, + value: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 100: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 101: BranchIfZero { + target: 106, + value: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 102: BranchIfZero { + target: 104, + value: StatePartIndex(57), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 103: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:148:9 + 104: BranchIfNonZero { + target: 106, + value: StatePartIndex(57), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 105: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:118:30 + 106: BranchIfSmallNeImmediate { + target: 108, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 107: Copy { + dest: StatePartIndex(42), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x1f) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 108: Copy { + dest: StatePartIndex(18), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 109: BranchIfSmallZero { + target: 114, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 110: BranchIfSmallNonZero { + target: 113, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 111: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + src: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + }, + 112: Branch { + target: 114, + }, + 113: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:86:25 + 114: BranchIfSmallZero { + target: 119, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 115: BranchIfSmallNonZero { + target: 118, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 116: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + src: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + }, + 117: Branch { + target: 119, + }, + 118: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:88:26 + 119: BranchIfSmallZero { + target: 124, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 120: BranchIfSmallNonZero { + target: 123, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 121: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 122: Branch { + target: 124, + }, + 123: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 124: BranchIfSmallZero { + target: 125, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 125: BranchIfSmallZero { + target: 133, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 126: CopySmall { + dest: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + }, + 127: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 128: Copy { + dest: StatePartIndex(20), // (0x1f) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 129: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 130: BranchIfSmallZero { + target: 133, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 131: BranchIfZero { + target: 133, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 132: MemoryWriteUInt { + value: StatePartIndex(20), // (0x1f) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 1>, + // data: [ + // // len = 0x1 + // [0x0]: 0x1f, + // ], + // }) (), + addr: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + stride: 8, + start: 0, + width: 8, + }, + 133: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 134: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 135: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 136: Return, + ], + .. + }, + pc: 136, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 1>, + data: [ + // len = 0x1 + [0x0]: 0x1f, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 63, + 0, + 63, + 31, + 63, + 0, + 63, + 31, + 1, + 0, + 1, + 0, + 31, + 0, + 0, + 0, + 31, + 1, + 31, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 31, + 0, + 0, + 1, + 1, + 31, + 1, + 62, + 63, + 63, + 63, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<1>, + flow: Sink, + }, + ty: UInt<1>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 1, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + }, + ], + array_type: Array, 1>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<0>, + flow: Duplex, + }, + ty: UInt<0>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<0>, + flow: Duplex, + }, + ty: UInt<0>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + TraceWire { + name: "count_lower", + child: TraceUInt { + location: TraceScalarId(29), + name: "count_lower", + ty: UInt<0>, + flow: Duplex, + }, + ty: UInt<0>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x1f, + last_state: 0x1f, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x1f, + last_state: 0x1f, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<1>, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<0>, + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x1f, + last_state: 0x1f, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<0>, + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x1f, + last_state: 0x1f, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<0>, + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<0>, + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x1f, + last_state: 0x1f, + }, + SimTrace { + id: TraceScalarId(29), + kind: BigUInt { + index: StatePartIndex(66), + ty: UInt<0>, + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 1, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + }, + ], + array_type: Array, 1>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_1_true_false.vcd b/crates/fayalite/tests/sim/expected/queue_1_true_false.vcd new file mode 100644 index 0000000..0ddf51e --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_1_true_false.vcd @@ -0,0 +1,1821 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 1 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var string 0 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var string 0 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var string 0 Xk?#v inp_index_reg $end +$var string 0 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 68, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count_lower", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 1>, + data: [ + // len = 0x1 + [0x0]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + dest_width: 1, + }, + 1: CastToUInt { + dest: StatePartIndex(66), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 0, + }, + // at: ready_valid.rs:178:13 + 2: Copy { + dest: StatePartIndex(64), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<0> }, + src: StatePartIndex(66), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 3: CastToUInt { + dest: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(64), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<0> }, + dest_width: 1, + }, + 4: Const { + dest: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x1, + }, + 5: CastToUInt { + dest: StatePartIndex(62), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 1, + }, + 6: Const { + dest: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x0, + }, + 7: CmpEq { + dest: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + }, + 8: CmpEq { + dest: StatePartIndex(58), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + }, + 9: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 10: Add { + dest: StatePartIndex(56), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 11: CastToUInt { + dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(56), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 0, + }, + 12: Add { + dest: StatePartIndex(59), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 13: CastToUInt { + dest: StatePartIndex(60), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(59), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 0, + }, + 14: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 15: Copy { + dest: StatePartIndex(42), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 16: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 17: Copy { + dest: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<0> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:114:5 + 18: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 19: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 20: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 21: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 22: Copy { + dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<0> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 23: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 24: CmpEq { + dest: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:104:5 + 25: Copy { + dest: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 26: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 27: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 28: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 29: And { + dest: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 30: Copy { + dest: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 31: NotU { + dest: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 32: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:124:9 + 33: BranchIfZero { + target: 35, + value: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:125:13 + 34: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 35: BranchIfZero { + target: 38, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 36: BranchIfZero { + target: 38, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 37: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<1> }, + src: StatePartIndex(62), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:88:26 + 38: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 39: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 40: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:84:31 + 41: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 42: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 43: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 44: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 45: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 46: CastToUInt { + dest: StatePartIndex(63), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 1, + }, + // at: ready_valid.rs:166:5 + 47: BranchIfZero { + target: 50, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 48: BranchIfNonZero { + target: 50, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 49: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<1> }, + src: StatePartIndex(63), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:166:5 + 50: BranchIfNonZero { + target: 52, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:182:13 + 51: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<1> }, + src: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:91:19 + 52: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<0> }, + }, + 53: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 54: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 55: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<0> }, + }, + 56: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 57: BranchIfSmallZero { + target: 60, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 58: MemoryReadUInt { + dest: StatePartIndex(14), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 1>, + // data: [ + // // len = 0x1 + // [0x0]: 0x23, + // ], + // }) (), + addr: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + stride: 8, + start: 0, + width: 8, + }, + 59: Branch { + target: 61, + }, + 60: Const { + dest: StatePartIndex(14), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 61: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 62: Copy { + dest: StatePartIndex(47), // (0x23) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 63: Shl { + dest: StatePartIndex(49), // (0x46) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x23) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 64: Or { + dest: StatePartIndex(50), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x46) SlotDebugData { name: "", ty: UInt<9> }, + }, + 65: CastToUInt { + dest: StatePartIndex(51), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 66: Copy { + dest: StatePartIndex(52), // (0x47) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 67: BranchIfZero { + target: 69, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 68: Copy { + dest: StatePartIndex(6), // (0x47) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x47) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 69: BranchIfNonZero { + target: 71, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:134:13 + 70: Copy { + dest: StatePartIndex(6), // (0x47) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(2), // (0x47) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 71: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 72: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 73: Copy { + dest: StatePartIndex(8), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x47) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 74: SliceInt { + dest: StatePartIndex(9), // (0x23) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 75: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x47) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 76: BranchIfSmallNeImmediate { + target: 78, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 77: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 78: BranchIfSmallNeImmediate { + target: 80, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 79: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 80: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 81: BranchIfZero { + target: 86, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 82: BranchIfZero { + target: 84, + value: StatePartIndex(58), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 83: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:158:9 + 84: BranchIfNonZero { + target: 86, + value: StatePartIndex(58), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 85: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(60), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 86: Copy { + dest: StatePartIndex(4), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x47) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 87: SliceInt { + dest: StatePartIndex(5), // (0x23) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 88: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x47) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 89: BranchIfSmallNeImmediate { + target: 91, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 90: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 91: BranchIfSmallNeImmediate { + target: 93, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 92: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 93: Copy { + dest: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 94: Copy { + dest: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 95: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 96: CmpNe { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 97: BranchIfZero { + target: 99, + value: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 98: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 99: BranchIfZero { + target: 104, + value: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 100: BranchIfZero { + target: 102, + value: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 101: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:148:9 + 102: BranchIfNonZero { + target: 104, + value: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 103: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:118:30 + 104: BranchIfSmallNeImmediate { + target: 106, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 105: Copy { + dest: StatePartIndex(42), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x23) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 106: Copy { + dest: StatePartIndex(18), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 107: BranchIfSmallZero { + target: 112, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 108: BranchIfSmallNonZero { + target: 111, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 109: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + src: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + }, + 110: Branch { + target: 112, + }, + 111: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:86:25 + 112: BranchIfSmallZero { + target: 117, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 113: BranchIfSmallNonZero { + target: 116, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 114: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + src: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + }, + 115: Branch { + target: 117, + }, + 116: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:88:26 + 117: BranchIfSmallZero { + target: 122, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 118: BranchIfSmallNonZero { + target: 121, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 119: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 120: Branch { + target: 122, + }, + 121: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 122: BranchIfSmallZero { + target: 123, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 123: BranchIfSmallZero { + target: 131, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 124: CopySmall { + dest: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + }, + 125: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 126: Copy { + dest: StatePartIndex(20), // (0x23) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 127: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 128: BranchIfSmallZero { + target: 131, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 129: BranchIfZero { + target: 131, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 130: MemoryWriteUInt { + value: StatePartIndex(20), // (0x23) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 1>, + // data: [ + // // len = 0x1 + // [0x0]: 0x23, + // ], + // }) (), + addr: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + stride: 8, + start: 0, + width: 8, + }, + 131: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 132: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 133: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 134: Return, + ], + .. + }, + pc: 134, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 1>, + data: [ + // len = 0x1 + [0x0]: 0x23, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 71, + 0, + 71, + 35, + 71, + 0, + 71, + 35, + 1, + 0, + 1, + 0, + 35, + 0, + 0, + 0, + 35, + 1, + 35, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 35, + 0, + 0, + 1, + 1, + 35, + 1, + 70, + 71, + 71, + 71, + 0, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<1>, + flow: Sink, + }, + ty: UInt<1>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 1, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + }, + ], + array_type: Array, 1>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<0>, + flow: Duplex, + }, + ty: UInt<0>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<0>, + flow: Duplex, + }, + ty: UInt<0>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + TraceWire { + name: "count_lower", + child: TraceUInt { + location: TraceScalarId(29), + name: "count_lower", + ty: UInt<0>, + flow: Duplex, + }, + ty: UInt<0>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x23, + last_state: 0x23, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x23, + last_state: 0x23, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<1>, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<0>, + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x23, + last_state: 0x23, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<0>, + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x23, + last_state: 0x23, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<0>, + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<0>, + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x23, + last_state: 0x23, + }, + SimTrace { + id: TraceScalarId(29), + kind: BigUInt { + index: StatePartIndex(64), + ty: UInt<0>, + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 1, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + }, + ], + array_type: Array, 1>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_1_true_true.vcd b/crates/fayalite/tests/sim/expected/queue_1_true_true.vcd new file mode 100644 index 0000000..9fc4356 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_1_true_true.vcd @@ -0,0 +1,1804 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 1 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var string 0 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var string 0 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var string 0 Xk?#v inp_index_reg $end +$var string 0 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 72, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count_lower", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 2>, + data: [ + // len = 0x2 + [0x0]: 0x00, + [0x1]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(69), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + dest_width: 2, + }, + 1: CastToUInt { + dest: StatePartIndex(70), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(69), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: ready_valid.rs:178:13 + 2: Copy { + dest: StatePartIndex(68), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<1> }, + src: StatePartIndex(70), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 3: CastToUInt { + dest: StatePartIndex(71), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(68), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<1> }, + dest_width: 2, + }, + 4: Const { + dest: StatePartIndex(65), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x2, + }, + 5: CastToUInt { + dest: StatePartIndex(66), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(65), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 2, + }, + 6: Const { + dest: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 7: CastToUInt { + dest: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 1, + }, + 8: CastToUInt { + dest: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 2, + }, + 9: Const { + dest: StatePartIndex(56), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x1, + }, + 10: CmpEq { + dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(56), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + }, + 11: CmpEq { + dest: StatePartIndex(62), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(56), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + }, + 12: Const { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + value: 0x0, + }, + 13: Copy { + dest: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + }, + 14: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 15: Add { + dest: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 16: CastToUInt { + dest: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + 17: Add { + dest: StatePartIndex(63), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 18: CastToUInt { + dest: StatePartIndex(64), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(63), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + 19: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 20: Copy { + dest: StatePartIndex(42), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 21: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 22: Copy { + dest: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<1> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:114:5 + 23: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 24: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 25: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 26: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 27: Copy { + dest: StatePartIndex(11), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<1> }, + src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 28: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 29: CmpEq { + dest: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:104:5 + 30: Copy { + dest: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 31: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 32: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 33: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 34: And { + dest: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 35: Copy { + dest: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 36: NotU { + dest: StatePartIndex(44), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 37: Copy { + dest: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 38: BranchIfZero { + target: 43, + value: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 39: BranchIfZero { + target: 41, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 40: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(66), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:168:9 + 41: BranchIfNonZero { + target: 43, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 42: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:166:5 + 43: BranchIfNonZero { + target: 45, + value: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:182:13 + 44: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(71), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 45: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 46: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 47: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:84:31 + 48: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 49: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 50: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 51: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 52: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x0, + }, + // at: ready_valid.rs:91:19 + 53: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<1> }, + }, + 54: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 55: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 56: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(11), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<1> }, + }, + 57: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 58: BranchIfSmallZero { + target: 61, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 59: MemoryReadUInt { + dest: StatePartIndex(14), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 2>, + // data: [ + // // len = 0x2 + // [0x0]: 0x22, + // [0x1]: 0x23, + // ], + // }) (), + addr: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: UInt<1> }, + stride: 8, + start: 0, + width: 8, + }, + 60: Branch { + target: 62, + }, + 61: Const { + dest: StatePartIndex(14), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 62: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 63: Copy { + dest: StatePartIndex(47), // (0x23) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 64: Shl { + dest: StatePartIndex(49), // (0x46) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x23) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 65: Or { + dest: StatePartIndex(50), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x46) SlotDebugData { name: "", ty: UInt<9> }, + }, + 66: CastToUInt { + dest: StatePartIndex(51), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 67: Copy { + dest: StatePartIndex(52), // (0x47) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 68: BranchIfZero { + target: 70, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 69: Copy { + dest: StatePartIndex(6), // (0x47) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x47) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 70: BranchIfNonZero { + target: 72, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:136:13 + 71: Copy { + dest: StatePartIndex(6), // (0x47) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 72: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 73: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 74: Copy { + dest: StatePartIndex(8), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x47) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 75: SliceInt { + dest: StatePartIndex(9), // (0x23) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 76: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x47) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 77: BranchIfSmallNeImmediate { + target: 79, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 78: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 79: BranchIfSmallNeImmediate { + target: 81, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 80: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 81: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 82: BranchIfZero { + target: 87, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 83: BranchIfZero { + target: 85, + value: StatePartIndex(62), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 84: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:158:9 + 85: BranchIfNonZero { + target: 87, + value: StatePartIndex(62), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 86: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(64), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 87: Copy { + dest: StatePartIndex(4), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x47) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 88: SliceInt { + dest: StatePartIndex(5), // (0x23) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 89: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x47) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 90: BranchIfSmallNeImmediate { + target: 92, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 91: Copy { + dest: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 92: BranchIfSmallNeImmediate { + target: 94, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 93: Copy { + dest: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 94: Copy { + dest: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 95: Copy { + dest: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 96: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 97: CmpNe { + dest: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 98: BranchIfZero { + target: 100, + value: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 99: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 100: BranchIfZero { + target: 105, + value: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 101: BranchIfZero { + target: 103, + value: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 102: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:148:9 + 103: BranchIfNonZero { + target: 105, + value: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 104: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:118:30 + 105: BranchIfSmallNeImmediate { + target: 107, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 106: Copy { + dest: StatePartIndex(42), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x23) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 107: Copy { + dest: StatePartIndex(18), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 108: BranchIfSmallZero { + target: 113, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 109: BranchIfSmallNonZero { + target: 112, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 110: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + src: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + }, + 111: Branch { + target: 113, + }, + 112: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:86:25 + 113: BranchIfSmallZero { + target: 118, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 114: BranchIfSmallNonZero { + target: 117, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 115: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + src: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + }, + 116: Branch { + target: 118, + }, + 117: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:88:26 + 118: BranchIfSmallZero { + target: 123, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 119: BranchIfSmallNonZero { + target: 122, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 120: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 121: Branch { + target: 123, + }, + 122: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 123: BranchIfSmallZero { + target: 124, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 124: BranchIfSmallZero { + target: 132, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 125: CopySmall { + dest: StatePartIndex(12), // (0x1 1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 126: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 127: Copy { + dest: StatePartIndex(20), // (0x23) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 128: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 129: BranchIfSmallZero { + target: 132, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 130: BranchIfZero { + target: 132, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 131: MemoryWriteUInt { + value: StatePartIndex(20), // (0x23) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 2>, + // data: [ + // // len = 0x2 + // [0x0]: 0x22, + // [0x1]: 0x23, + // ], + // }) (), + addr: StatePartIndex(12), // (0x1 1) SlotDebugData { name: "", ty: UInt<1> }, + stride: 8, + start: 0, + width: 8, + }, + 132: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 133: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 134: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 135: Return, + ], + .. + }, + pc: 135, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 2>, + data: [ + // len = 0x2 + [0x0]: 0x22, + [0x1]: 0x23, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 1, + 1, + 0, + 0, + 1, + 0, + 1, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 71, + 1, + 71, + 35, + 71, + 0, + 71, + 35, + 1, + 1, + 1, + 0, + 35, + 0, + 1, + 0, + 35, + 1, + 35, + 1, + 0, + 1, + 0, + 1, + 1, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 35, + 0, + 1, + 1, + 1, + 35, + 1, + 70, + 71, + 71, + 71, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 2, + 0, + 2, + 2, + 0, + 1, + 3, + 1, + 1, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<2>, + flow: Sink, + }, + ty: UInt<2>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 2, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + }, + ], + array_type: Array, 2>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + TraceWire { + name: "count_lower", + child: TraceUInt { + location: TraceScalarId(29), + name: "count_lower", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x23, + last_state: 0x23, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x23, + last_state: 0x23, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<1>, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x23, + last_state: 0x23, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<1>, + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x23, + last_state: 0x23, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<1>, + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<1>, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x23, + last_state: 0x23, + }, + SimTrace { + id: TraceScalarId(29), + kind: BigUInt { + index: StatePartIndex(68), + ty: UInt<1>, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 2, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + }, + ], + array_type: Array, 2>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_2_false_false.vcd b/crates/fayalite/tests/sim/expected/queue_2_false_false.vcd new file mode 100644 index 0000000..92a7278 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_2_false_false.vcd @@ -0,0 +1,2117 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 2 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$scope struct \[1] $end +$var reg 8 5F$iE mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 1 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var wire 1 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var reg 1 Xk?#v inp_index_reg $end +$var reg 1 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 70, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count_lower", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 2>, + data: [ + // len = 0x2 + [0x0]: 0x00, + [0x1]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(67), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + dest_width: 2, + }, + 1: CastToUInt { + dest: StatePartIndex(68), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(67), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: ready_valid.rs:178:13 + 2: Copy { + dest: StatePartIndex(66), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<1> }, + src: StatePartIndex(68), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 3: CastToUInt { + dest: StatePartIndex(69), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(66), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<1> }, + dest_width: 2, + }, + 4: Const { + dest: StatePartIndex(63), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x2, + }, + 5: CastToUInt { + dest: StatePartIndex(64), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(63), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 2, + }, + 6: Const { + dest: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 7: CastToUInt { + dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 1, + }, + 8: CastToUInt { + dest: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 2, + }, + 9: Const { + dest: StatePartIndex(54), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x1, + }, + 10: CmpEq { + dest: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(54), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + }, + 11: CmpEq { + dest: StatePartIndex(60), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(54), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + }, + 12: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 13: Add { + dest: StatePartIndex(58), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 14: CastToUInt { + dest: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(58), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + 15: Add { + dest: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 16: CastToUInt { + dest: StatePartIndex(62), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + 17: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 18: Copy { + dest: StatePartIndex(42), // (0x26) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 19: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 20: Copy { + dest: StatePartIndex(15), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<1> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:114:5 + 21: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 22: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 23: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 24: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 25: Copy { + dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<1> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 26: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 27: CmpEq { + dest: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:104:5 + 28: Copy { + dest: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 29: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 30: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 31: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 32: And { + dest: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 33: Copy { + dest: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 34: NotU { + dest: StatePartIndex(44), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 35: Copy { + dest: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 36: BranchIfZero { + target: 41, + value: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 37: BranchIfZero { + target: 39, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 38: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(64), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:168:9 + 39: BranchIfNonZero { + target: 41, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 40: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:166:5 + 41: BranchIfNonZero { + target: 43, + value: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:182:13 + 42: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(69), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 43: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 44: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 45: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:84:31 + 46: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 47: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 48: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 49: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 50: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x0, + }, + // at: ready_valid.rs:91:19 + 51: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x1 1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(15), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<1> }, + }, + 52: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 53: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 54: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<1> }, + }, + 55: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 56: BranchIfSmallZero { + target: 59, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 57: MemoryReadUInt { + dest: StatePartIndex(14), // (0x26) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 2>, + // data: [ + // // len = 0x2 + // [0x0]: 0x26, + // [0x1]: 0x25, + // ], + // }) (), + addr: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + stride: 8, + start: 0, + width: 8, + }, + 58: Branch { + target: 60, + }, + 59: Const { + dest: StatePartIndex(14), // (0x26) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 60: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 61: Copy { + dest: StatePartIndex(47), // (0x26) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x26) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 62: Shl { + dest: StatePartIndex(49), // (0x4c) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x26) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 63: Or { + dest: StatePartIndex(50), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x4c) SlotDebugData { name: "", ty: UInt<9> }, + }, + 64: CastToUInt { + dest: StatePartIndex(51), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 65: Copy { + dest: StatePartIndex(52), // (0x4d) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 66: BranchIfZero { + target: 68, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 67: Copy { + dest: StatePartIndex(6), // (0x4d) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x4d) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 68: BranchIfNonZero { + target: 70, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:134:13 + 69: Copy { + dest: StatePartIndex(6), // (0x4d) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(2), // (0x4d) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 70: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 71: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 72: Copy { + dest: StatePartIndex(8), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x4d) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 73: SliceInt { + dest: StatePartIndex(9), // (0x26) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 74: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x4d) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 75: BranchIfSmallNeImmediate { + target: 77, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 76: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 77: BranchIfSmallNeImmediate { + target: 79, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 78: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 79: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 80: BranchIfZero { + target: 85, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 81: BranchIfZero { + target: 83, + value: StatePartIndex(60), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 82: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:158:9 + 83: BranchIfNonZero { + target: 85, + value: StatePartIndex(60), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 84: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(62), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 85: Copy { + dest: StatePartIndex(4), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x4d) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 86: SliceInt { + dest: StatePartIndex(5), // (0x26) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 87: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x4d) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 88: BranchIfSmallNeImmediate { + target: 90, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 89: Copy { + dest: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 90: BranchIfSmallNeImmediate { + target: 92, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 91: Copy { + dest: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 92: Copy { + dest: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 93: Copy { + dest: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 94: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 95: CmpNe { + dest: StatePartIndex(53), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 96: BranchIfZero { + target: 98, + value: StatePartIndex(53), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 97: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 98: BranchIfZero { + target: 103, + value: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 99: BranchIfZero { + target: 101, + value: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 100: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:148:9 + 101: BranchIfNonZero { + target: 103, + value: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 102: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:118:30 + 103: BranchIfSmallNeImmediate { + target: 105, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 104: Copy { + dest: StatePartIndex(42), // (0x26) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x26) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 105: Copy { + dest: StatePartIndex(18), // (0x26) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x26) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 106: BranchIfSmallZero { + target: 111, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 107: BranchIfSmallNonZero { + target: 110, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 108: Copy { + dest: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + src: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + }, + 109: Branch { + target: 111, + }, + 110: Copy { + dest: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:86:25 + 111: BranchIfSmallZero { + target: 116, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 112: BranchIfSmallNonZero { + target: 115, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 113: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + src: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + }, + 114: Branch { + target: 116, + }, + 115: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:88:26 + 116: BranchIfSmallZero { + target: 121, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 117: BranchIfSmallNonZero { + target: 120, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 118: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 119: Branch { + target: 121, + }, + 120: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 121: BranchIfSmallZero { + target: 122, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 122: BranchIfSmallZero { + target: 130, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 123: CopySmall { + dest: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(11), // (0x1 1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 124: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 125: Copy { + dest: StatePartIndex(20), // (0x26) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x26) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 126: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 127: BranchIfSmallZero { + target: 130, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 128: BranchIfZero { + target: 130, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 129: MemoryWriteUInt { + value: StatePartIndex(20), // (0x26) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 2>, + // data: [ + // // len = 0x2 + // [0x0]: 0x26, + // [0x1]: 0x25, + // ], + // }) (), + addr: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + stride: 8, + start: 0, + width: 8, + }, + 130: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 131: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 132: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 133: Return, + ], + .. + }, + pc: 133, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 2>, + data: [ + // len = 0x2 + [0x0]: 0x26, + [0x1]: 0x25, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 77, + 1, + 77, + 38, + 77, + 0, + 77, + 38, + 1, + 0, + 1, + 0, + 38, + 1, + 1, + 0, + 38, + 1, + 38, + 1, + 1, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 38, + 0, + 1, + 1, + 1, + 38, + 1, + 76, + 77, + 77, + 77, + 1, + 1, + 1, + 0, + 0, + 2, + 0, + 0, + 1, + 1, + 2, + 2, + 0, + 1, + 1, + 1, + 1, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<2>, + flow: Sink, + }, + ty: UInt<2>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 2, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + }, + ], + array_type: Array, 2>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + TraceWire { + name: "count_lower", + child: TraceUInt { + location: TraceScalarId(29), + name: "count_lower", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x26, + last_state: 0x26, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x26, + last_state: 0x26, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<1>, + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x26, + last_state: 0x26, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<1>, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x26, + last_state: 0x26, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<1>, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<1>, + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x26, + last_state: 0x26, + }, + SimTrace { + id: TraceScalarId(29), + kind: BigUInt { + index: StatePartIndex(66), + ty: UInt<1>, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 2, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + }, + ], + array_type: Array, 2>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_2_false_true.vcd b/crates/fayalite/tests/sim/expected/queue_2_false_true.vcd new file mode 100644 index 0000000..55da6e1 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_2_false_true.vcd @@ -0,0 +1,2075 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 2 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$scope struct \[1] $end +$var reg 8 5F$iE mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 1 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var wire 1 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var reg 1 Xk?#v inp_index_reg $end +$var reg 1 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 72, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count_lower", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 2>, + data: [ + // len = 0x2 + [0x0]: 0x00, + [0x1]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + dest_width: 2, + }, + 1: CastToUInt { + dest: StatePartIndex(70), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: ready_valid.rs:178:13 + 2: Copy { + dest: StatePartIndex(68), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<1> }, + src: StatePartIndex(70), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 3: CastToUInt { + dest: StatePartIndex(71), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(68), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<1> }, + dest_width: 2, + }, + 4: Const { + dest: StatePartIndex(65), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x2, + }, + 5: CastToUInt { + dest: StatePartIndex(66), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(65), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 2, + }, + 6: Const { + dest: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 7: CastToUInt { + dest: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 1, + }, + 8: CastToUInt { + dest: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 2, + }, + 9: Const { + dest: StatePartIndex(56), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x1, + }, + 10: CmpEq { + dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(56), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + }, + 11: CmpEq { + dest: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(56), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + }, + 12: Const { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + value: 0x0, + }, + 13: Copy { + dest: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + }, + 14: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 15: Add { + dest: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 16: CastToUInt { + dest: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + 17: Add { + dest: StatePartIndex(63), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 18: CastToUInt { + dest: StatePartIndex(64), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(63), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + 19: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 20: Copy { + dest: StatePartIndex(42), // (0x27) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 21: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 22: Copy { + dest: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<1> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:114:5 + 23: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 24: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 25: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 26: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 27: Copy { + dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<1> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 28: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 29: CmpEq { + dest: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:104:5 + 30: Copy { + dest: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 31: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 32: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 33: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 34: And { + dest: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 35: Copy { + dest: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 36: NotU { + dest: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 37: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:124:9 + 38: BranchIfZero { + target: 40, + value: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:125:13 + 39: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 40: BranchIfZero { + target: 45, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 41: BranchIfZero { + target: 43, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 42: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(66), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:168:9 + 43: BranchIfNonZero { + target: 45, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 44: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:166:5 + 45: BranchIfNonZero { + target: 47, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:182:13 + 46: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(71), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 47: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 48: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 49: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:84:31 + 50: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 51: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 52: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 53: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 54: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x0, + }, + // at: ready_valid.rs:91:19 + 55: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<1> }, + }, + 56: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 57: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 58: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<1> }, + }, + 59: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 60: BranchIfSmallZero { + target: 63, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 61: MemoryReadUInt { + dest: StatePartIndex(14), // (0x26) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 2>, + // data: [ + // // len = 0x2 + // [0x0]: 0x26, + // [0x1]: 0x27, + // ], + // }) (), + addr: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + stride: 8, + start: 0, + width: 8, + }, + 62: Branch { + target: 64, + }, + 63: Const { + dest: StatePartIndex(14), // (0x26) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 64: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 65: Copy { + dest: StatePartIndex(47), // (0x26) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x26) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 66: Shl { + dest: StatePartIndex(49), // (0x4c) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x26) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 67: Or { + dest: StatePartIndex(50), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x4c) SlotDebugData { name: "", ty: UInt<9> }, + }, + 68: CastToUInt { + dest: StatePartIndex(51), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 69: Copy { + dest: StatePartIndex(52), // (0x4d) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 70: BranchIfZero { + target: 72, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 71: Copy { + dest: StatePartIndex(6), // (0x4d) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x4d) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 72: BranchIfNonZero { + target: 74, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:136:13 + 73: Copy { + dest: StatePartIndex(6), // (0x4d) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 74: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 75: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 76: Copy { + dest: StatePartIndex(8), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x4d) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 77: SliceInt { + dest: StatePartIndex(9), // (0x26) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 78: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x4d) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 79: BranchIfSmallNeImmediate { + target: 81, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 80: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 81: BranchIfSmallNeImmediate { + target: 83, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 82: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 83: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 84: BranchIfZero { + target: 89, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 85: BranchIfZero { + target: 87, + value: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 86: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:158:9 + 87: BranchIfNonZero { + target: 89, + value: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 88: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(64), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 89: Copy { + dest: StatePartIndex(4), // (0x4f) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x4f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 90: SliceInt { + dest: StatePartIndex(5), // (0x27) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x4f) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 91: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x4f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 92: BranchIfSmallNeImmediate { + target: 94, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 93: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 94: BranchIfSmallNeImmediate { + target: 96, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 95: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 96: Copy { + dest: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 97: Copy { + dest: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 98: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 99: CmpNe { + dest: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 100: BranchIfZero { + target: 102, + value: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 101: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 102: BranchIfZero { + target: 107, + value: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 103: BranchIfZero { + target: 105, + value: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 104: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:148:9 + 105: BranchIfNonZero { + target: 107, + value: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 106: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:118:30 + 107: BranchIfSmallNeImmediate { + target: 109, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 108: Copy { + dest: StatePartIndex(42), // (0x27) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x27) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 109: Copy { + dest: StatePartIndex(18), // (0x27) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x27) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 110: BranchIfSmallZero { + target: 115, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 111: BranchIfSmallNonZero { + target: 114, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 112: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + src: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + }, + 113: Branch { + target: 115, + }, + 114: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:86:25 + 115: BranchIfSmallZero { + target: 120, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 116: BranchIfSmallNonZero { + target: 119, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 117: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + src: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + }, + 118: Branch { + target: 120, + }, + 119: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:88:26 + 120: BranchIfSmallZero { + target: 125, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 121: BranchIfSmallNonZero { + target: 124, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 122: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 123: Branch { + target: 125, + }, + 124: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 125: BranchIfSmallZero { + target: 126, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 126: BranchIfSmallZero { + target: 134, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 127: CopySmall { + dest: StatePartIndex(12), // (0x1 1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 128: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 129: Copy { + dest: StatePartIndex(20), // (0x27) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x27) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 130: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 131: BranchIfSmallZero { + target: 134, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 132: BranchIfZero { + target: 134, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 133: MemoryWriteUInt { + value: StatePartIndex(20), // (0x27) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 2>, + // data: [ + // // len = 0x2 + // [0x0]: 0x26, + // [0x1]: 0x27, + // ], + // }) (), + addr: StatePartIndex(12), // (0x1 1) SlotDebugData { name: "", ty: UInt<1> }, + stride: 8, + start: 0, + width: 8, + }, + 134: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 135: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 136: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 137: Return, + ], + .. + }, + pc: 137, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 2>, + data: [ + // len = 0x2 + [0x0]: 0x26, + [0x1]: 0x27, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 79, + 0, + 79, + 39, + 77, + 0, + 77, + 38, + 2, + 0, + 1, + 0, + 38, + 0, + 0, + 0, + 39, + 1, + 39, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 39, + 0, + 0, + 1, + 1, + 38, + 1, + 76, + 77, + 77, + 77, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 1, + 1, + 0, + 1, + 1, + 2, + 2, + 0, + 0, + 0, + 0, + 0, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<2>, + flow: Sink, + }, + ty: UInt<2>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 2, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + }, + ], + array_type: Array, 2>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + TraceWire { + name: "count_lower", + child: TraceUInt { + location: TraceScalarId(29), + name: "count_lower", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x27, + last_state: 0x27, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x26, + last_state: 0x26, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<1>, + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x26, + last_state: 0x26, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<1>, + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x27, + last_state: 0x27, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<1>, + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<1>, + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x27, + last_state: 0x27, + }, + SimTrace { + id: TraceScalarId(29), + kind: BigUInt { + index: StatePartIndex(68), + ty: UInt<1>, + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 2, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + }, + ], + array_type: Array, 2>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_2_true_false.vcd b/crates/fayalite/tests/sim/expected/queue_2_true_false.vcd new file mode 100644 index 0000000..e54b985 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_2_true_false.vcd @@ -0,0 +1,2035 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 2 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$scope struct \[1] $end +$var reg 8 5F$iE mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 1 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var wire 1 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var reg 1 Xk?#v inp_index_reg $end +$var reg 1 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 70, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count_lower", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 2>, + data: [ + // len = 0x2 + [0x0]: 0x00, + [0x1]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + dest_width: 2, + }, + 1: CastToUInt { + dest: StatePartIndex(68), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: ready_valid.rs:178:13 + 2: Copy { + dest: StatePartIndex(66), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<1> }, + src: StatePartIndex(68), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 3: CastToUInt { + dest: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(66), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<1> }, + dest_width: 2, + }, + 4: Const { + dest: StatePartIndex(63), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x2, + }, + 5: CastToUInt { + dest: StatePartIndex(64), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(63), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 2, + }, + 6: Const { + dest: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 7: CastToUInt { + dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 1, + }, + 8: CastToUInt { + dest: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 2, + }, + 9: Const { + dest: StatePartIndex(54), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x1, + }, + 10: CmpEq { + dest: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(54), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + }, + 11: CmpEq { + dest: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(54), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + }, + 12: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 13: Add { + dest: StatePartIndex(58), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 14: CastToUInt { + dest: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(58), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + 15: Add { + dest: StatePartIndex(61), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 16: CastToUInt { + dest: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(61), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + 17: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 18: Copy { + dest: StatePartIndex(42), // (0x2a) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 19: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 20: Copy { + dest: StatePartIndex(15), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<1> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:114:5 + 21: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 22: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 23: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 24: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 25: Copy { + dest: StatePartIndex(11), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<1> }, + src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 26: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 27: CmpEq { + dest: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:104:5 + 28: Copy { + dest: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 29: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 30: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 31: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 32: And { + dest: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 33: Copy { + dest: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 34: NotU { + dest: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 35: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:124:9 + 36: BranchIfZero { + target: 38, + value: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:125:13 + 37: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 38: BranchIfZero { + target: 43, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 39: BranchIfZero { + target: 41, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 40: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(64), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:168:9 + 41: BranchIfNonZero { + target: 43, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 42: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:166:5 + 43: BranchIfNonZero { + target: 45, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:182:13 + 44: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 45: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 46: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 47: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:84:31 + 48: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 49: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 50: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 51: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 52: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x0, + }, + // at: ready_valid.rs:91:19 + 53: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x1 1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(15), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<1> }, + }, + 54: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 55: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 56: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(11), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<1> }, + }, + 57: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 58: BranchIfSmallZero { + target: 61, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 59: MemoryReadUInt { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 2>, + // data: [ + // // len = 0x2 + // [0x0]: 0x2a, + // [0x1]: 0x29, + // ], + // }) (), + addr: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: UInt<1> }, + stride: 8, + start: 0, + width: 8, + }, + 60: Branch { + target: 62, + }, + 61: Const { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 62: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 63: Copy { + dest: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 64: Shl { + dest: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 65: Or { + dest: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + }, + 66: CastToUInt { + dest: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 67: Copy { + dest: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 68: BranchIfZero { + target: 70, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 69: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 70: BranchIfNonZero { + target: 72, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:134:13 + 71: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(2), // (0x55) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 72: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 73: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 74: Copy { + dest: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 75: SliceInt { + dest: StatePartIndex(9), // (0x29) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 76: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 77: BranchIfSmallNeImmediate { + target: 79, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 78: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 79: BranchIfSmallNeImmediate { + target: 81, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 80: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 81: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 82: BranchIfZero { + target: 87, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 83: BranchIfZero { + target: 85, + value: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 84: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:158:9 + 85: BranchIfNonZero { + target: 87, + value: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 86: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 87: Copy { + dest: StatePartIndex(4), // (0x55) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x55) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 88: SliceInt { + dest: StatePartIndex(5), // (0x2a) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x55) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 89: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x55) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 90: BranchIfSmallNeImmediate { + target: 92, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 91: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 92: BranchIfSmallNeImmediate { + target: 94, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 93: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 94: Copy { + dest: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 95: Copy { + dest: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 96: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 97: CmpNe { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 98: BranchIfZero { + target: 100, + value: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 99: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 100: BranchIfZero { + target: 105, + value: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 101: BranchIfZero { + target: 103, + value: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 102: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:148:9 + 103: BranchIfNonZero { + target: 105, + value: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 104: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:118:30 + 105: BranchIfSmallNeImmediate { + target: 107, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 106: Copy { + dest: StatePartIndex(42), // (0x2a) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x2a) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 107: Copy { + dest: StatePartIndex(18), // (0x2a) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x2a) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 108: BranchIfSmallZero { + target: 113, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 109: BranchIfSmallNonZero { + target: 112, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 110: Copy { + dest: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + src: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + }, + 111: Branch { + target: 113, + }, + 112: Copy { + dest: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:86:25 + 113: BranchIfSmallZero { + target: 118, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 114: BranchIfSmallNonZero { + target: 117, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 115: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + src: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + }, + 116: Branch { + target: 118, + }, + 117: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:88:26 + 118: BranchIfSmallZero { + target: 123, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 119: BranchIfSmallNonZero { + target: 122, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 120: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 121: Branch { + target: 123, + }, + 122: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 123: BranchIfSmallZero { + target: 124, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 124: BranchIfSmallZero { + target: 132, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 125: CopySmall { + dest: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(11), // (0x1 1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 126: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 127: Copy { + dest: StatePartIndex(20), // (0x2a) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x2a) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 128: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 129: BranchIfSmallZero { + target: 132, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 130: BranchIfZero { + target: 132, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 131: MemoryWriteUInt { + value: StatePartIndex(20), // (0x2a) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 2>, + // data: [ + // // len = 0x2 + // [0x0]: 0x2a, + // [0x1]: 0x29, + // ], + // }) (), + addr: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + stride: 8, + start: 0, + width: 8, + }, + 132: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 133: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 134: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 135: Return, + ], + .. + }, + pc: 135, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 2>, + data: [ + // len = 0x2 + [0x0]: 0x2a, + [0x1]: 0x29, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 1, + 1, + 0, + 0, + 0, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 85, + 0, + 85, + 42, + 83, + 0, + 83, + 41, + 2, + 1, + 1, + 0, + 41, + 1, + 0, + 0, + 42, + 1, + 42, + 1, + 1, + 1, + 0, + 1, + 1, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 42, + 0, + 0, + 1, + 1, + 41, + 1, + 82, + 83, + 83, + 83, + 0, + 1, + 1, + 0, + 0, + 2, + 0, + 1, + 2, + 0, + 2, + 2, + 0, + 0, + 0, + 0, + 0, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<2>, + flow: Sink, + }, + ty: UInt<2>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 2, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + }, + ], + array_type: Array, 2>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + TraceWire { + name: "count_lower", + child: TraceUInt { + location: TraceScalarId(29), + name: "count_lower", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x2a, + last_state: 0x2a, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<1>, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<1>, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x2a, + last_state: 0x2a, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<1>, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<1>, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x2a, + last_state: 0x2a, + }, + SimTrace { + id: TraceScalarId(29), + kind: BigUInt { + index: StatePartIndex(66), + ty: UInt<1>, + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 2, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + }, + ], + array_type: Array, 2>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_2_true_true.vcd b/crates/fayalite/tests/sim/expected/queue_2_true_true.vcd new file mode 100644 index 0000000..f58f9ab --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_2_true_true.vcd @@ -0,0 +1,2043 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 2 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$scope struct \[1] $end +$var reg 8 5F$iE mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 1 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var wire 1 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var reg 1 Xk?#v inp_index_reg $end +$var reg 1 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 73, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<66>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 3>, + data: [ + // len = 0x3 + [0x0]: 0x00, + [0x1]: 0x00, + [0x2]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(71), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + dest_width: 3, + }, + 1: CastToUInt { + dest: StatePartIndex(72), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(71), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 2: CmpLt { + dest: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + 3: Const { + dest: StatePartIndex(65), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x3, + }, + 4: CastToUInt { + dest: StatePartIndex(66), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(65), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 2, + }, + 5: Add { + dest: StatePartIndex(68), // (0x5) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(65), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + }, + 6: SubU { + dest: StatePartIndex(69), // (0x5) SlotDebugData { name: "", ty: UInt<66> }, + lhs: StatePartIndex(68), // (0x5) SlotDebugData { name: "", ty: UInt<65> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + dest_width: 66, + }, + 7: CastToUInt { + dest: StatePartIndex(70), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(69), // (0x5) SlotDebugData { name: "", ty: UInt<66> }, + dest_width: 2, + }, + 8: Const { + dest: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 9: CastToUInt { + dest: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 2, + }, + 10: Const { + dest: StatePartIndex(56), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x2, + }, + 11: CmpEq { + dest: StatePartIndex(57), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(56), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + }, + 12: CmpEq { + dest: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(56), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + }, + 13: Const { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + value: 0x0, + }, + 14: Copy { + dest: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + }, + 15: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 16: Add { + dest: StatePartIndex(60), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 17: CastToUInt { + dest: StatePartIndex(61), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(60), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 18: Add { + dest: StatePartIndex(63), // (0x1) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 19: CastToUInt { + dest: StatePartIndex(64), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(63), // (0x1) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 20: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 21: Copy { + dest: StatePartIndex(42), // (0x28) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 22: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 23: Copy { + dest: StatePartIndex(15), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + src: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:114:5 + 24: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 25: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 26: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 27: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 28: Copy { + dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 29: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 30: CmpEq { + dest: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:104:5 + 31: Copy { + dest: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 32: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 33: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 34: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 35: And { + dest: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 36: Copy { + dest: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 37: NotU { + dest: StatePartIndex(44), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 38: Copy { + dest: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 39: BranchIfZero { + target: 44, + value: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 40: BranchIfZero { + target: 42, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 41: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(66), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:168:9 + 42: BranchIfNonZero { + target: 44, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 43: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:166:5 + 44: BranchIfNonZero { + target: 49, + value: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:186:13 + 45: BranchIfZero { + target: 47, + value: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:187:17 + 46: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(70), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:186:13 + 47: BranchIfNonZero { + target: 49, + value: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:189:17 + 48: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(72), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 49: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 50: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 51: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:84:31 + 52: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 53: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 54: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 55: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 56: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + value: 0x0, + }, + // at: ready_valid.rs:91:19 + 57: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x2 2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(15), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + }, + 58: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 59: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 60: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + }, + 61: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 62: BranchIfSmallZero { + target: 65, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 63: MemoryReadUInt { + dest: StatePartIndex(14), // (0x27) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 3>, + // data: [ + // // len = 0x3 + // [0x0]: 0x27, + // [0x1]: 0x28, + // [0x2]: 0x26, + // ], + // }) (), + addr: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 64: Branch { + target: 66, + }, + 65: Const { + dest: StatePartIndex(14), // (0x27) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 66: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 67: Copy { + dest: StatePartIndex(47), // (0x27) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x27) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 68: Shl { + dest: StatePartIndex(49), // (0x4e) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x27) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 69: Or { + dest: StatePartIndex(50), // (0x4f) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x4e) SlotDebugData { name: "", ty: UInt<9> }, + }, + 70: CastToUInt { + dest: StatePartIndex(51), // (0x4f) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x4f) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 71: Copy { + dest: StatePartIndex(52), // (0x4f) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x4f) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 72: BranchIfZero { + target: 74, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 73: Copy { + dest: StatePartIndex(6), // (0x4f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x4f) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 74: BranchIfNonZero { + target: 76, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:136:13 + 75: Copy { + dest: StatePartIndex(6), // (0x4f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 76: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 77: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 78: Copy { + dest: StatePartIndex(8), // (0x4f) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x4f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 79: SliceInt { + dest: StatePartIndex(9), // (0x27) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x4f) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 80: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x4f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 81: BranchIfSmallNeImmediate { + target: 83, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 82: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 83: BranchIfSmallNeImmediate { + target: 85, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 84: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 85: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 86: BranchIfZero { + target: 91, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 87: BranchIfZero { + target: 89, + value: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 88: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:158:9 + 89: BranchIfNonZero { + target: 91, + value: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 90: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(64), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 91: Copy { + dest: StatePartIndex(4), // (0x51) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x51) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 92: SliceInt { + dest: StatePartIndex(5), // (0x28) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x51) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 93: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x51) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 94: BranchIfSmallNeImmediate { + target: 96, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 95: Copy { + dest: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 96: BranchIfSmallNeImmediate { + target: 98, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 97: Copy { + dest: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 98: Copy { + dest: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 99: Copy { + dest: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 100: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 101: CmpNe { + dest: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 102: BranchIfZero { + target: 104, + value: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 103: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 104: BranchIfZero { + target: 109, + value: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 105: BranchIfZero { + target: 107, + value: StatePartIndex(57), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 106: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:148:9 + 107: BranchIfNonZero { + target: 109, + value: StatePartIndex(57), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 108: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(61), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:118:30 + 109: BranchIfSmallNeImmediate { + target: 111, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 110: Copy { + dest: StatePartIndex(42), // (0x28) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x28) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 111: Copy { + dest: StatePartIndex(18), // (0x28) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x28) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 112: BranchIfSmallZero { + target: 117, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 113: BranchIfSmallNonZero { + target: 116, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 114: Copy { + dest: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + }, + 115: Branch { + target: 117, + }, + 116: Copy { + dest: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:86:25 + 117: BranchIfSmallZero { + target: 122, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 118: BranchIfSmallNonZero { + target: 121, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 119: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + }, + 120: Branch { + target: 122, + }, + 121: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 122: BranchIfSmallZero { + target: 127, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 123: BranchIfSmallNonZero { + target: 126, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 124: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 125: Branch { + target: 127, + }, + 126: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 127: BranchIfSmallZero { + target: 128, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 128: BranchIfSmallZero { + target: 136, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 129: CopySmall { + dest: StatePartIndex(12), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x2 2) SlotDebugData { name: "", ty: UInt<2> }, + }, + 130: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 131: Copy { + dest: StatePartIndex(20), // (0x28) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x28) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 132: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 133: BranchIfSmallZero { + target: 136, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 134: BranchIfZero { + target: 136, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 135: MemoryWriteUInt { + value: StatePartIndex(20), // (0x28) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 3>, + // data: [ + // // len = 0x3 + // [0x0]: 0x27, + // [0x1]: 0x28, + // [0x2]: 0x26, + // ], + // }) (), + addr: StatePartIndex(12), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 136: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 137: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 138: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 139: Return, + ], + .. + }, + pc: 139, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 3>, + data: [ + // len = 0x3 + [0x0]: 0x27, + [0x1]: 0x28, + [0x2]: 0x26, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 1, + 2, + 1, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 81, + 1, + 81, + 40, + 79, + 0, + 79, + 39, + 2, + 0, + 1, + 0, + 39, + 2, + 1, + 0, + 40, + 1, + 40, + 1, + 2, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 40, + 0, + 1, + 1, + 1, + 39, + 1, + 78, + 79, + 79, + 79, + 0, + 0, + 1, + 2, + 1, + 0, + 0, + 3, + 3, + 0, + 1, + 1, + 3, + 3, + 0, + 5, + 5, + 1, + 2, + 2, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<2>, + flow: Sink, + }, + ty: UInt<2>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 3, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 3>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x28, + last_state: 0x28, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x27, + last_state: 0x27, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x27, + last_state: 0x27, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x28, + last_state: 0x28, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x28, + last_state: 0x28, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 3, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 3>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_3_false_false.vcd b/crates/fayalite/tests/sim/expected/queue_3_false_false.vcd new file mode 100644 index 0000000..4481901 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_3_false_false.vcd @@ -0,0 +1,1990 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 2 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$scope struct \[1] $end +$var reg 8 5F$iE mem $end +$upscope $end +$scope struct \[2] $end +$var reg 8 !BEt5 mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 2 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var wire 2 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var reg 2 Xk?#v inp_index_reg $end +$var reg 2 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 71, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<66>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 3>, + data: [ + // len = 0x3 + [0x0]: 0x00, + [0x1]: 0x00, + [0x2]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(69), // (0x7) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + dest_width: 3, + }, + 1: CastToUInt { + dest: StatePartIndex(70), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(69), // (0x7) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 2: CmpLt { + dest: StatePartIndex(65), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + 3: Const { + dest: StatePartIndex(63), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x3, + }, + 4: CastToUInt { + dest: StatePartIndex(64), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(63), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 2, + }, + 5: Add { + dest: StatePartIndex(66), // (0x4) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(63), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + }, + 6: SubU { + dest: StatePartIndex(67), // (0x2) SlotDebugData { name: "", ty: UInt<66> }, + lhs: StatePartIndex(66), // (0x4) SlotDebugData { name: "", ty: UInt<65> }, + rhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + dest_width: 66, + }, + 7: CastToUInt { + dest: StatePartIndex(68), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(67), // (0x2) SlotDebugData { name: "", ty: UInt<66> }, + dest_width: 2, + }, + 8: Const { + dest: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 9: CastToUInt { + dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 2, + }, + 10: Const { + dest: StatePartIndex(54), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x2, + }, + 11: CmpEq { + dest: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(54), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + }, + 12: CmpEq { + dest: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(54), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + }, + 13: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 14: Add { + dest: StatePartIndex(58), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 15: CastToUInt { + dest: StatePartIndex(59), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(58), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 16: Add { + dest: StatePartIndex(61), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 17: CastToUInt { + dest: StatePartIndex(62), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(61), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 18: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 19: Copy { + dest: StatePartIndex(42), // (0x2a) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 20: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 21: Copy { + dest: StatePartIndex(15), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:114:5 + 22: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 23: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 24: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 25: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 26: Copy { + dest: StatePartIndex(11), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + src: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 27: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 28: CmpEq { + dest: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:104:5 + 29: Copy { + dest: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 30: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 31: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 32: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 33: And { + dest: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 34: Copy { + dest: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 35: NotU { + dest: StatePartIndex(44), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 36: Copy { + dest: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 37: BranchIfZero { + target: 42, + value: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 38: BranchIfZero { + target: 40, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 39: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(64), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:168:9 + 40: BranchIfNonZero { + target: 42, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 41: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:166:5 + 42: BranchIfNonZero { + target: 47, + value: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:186:13 + 43: BranchIfZero { + target: 45, + value: StatePartIndex(65), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:187:17 + 44: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(68), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:186:13 + 45: BranchIfNonZero { + target: 47, + value: StatePartIndex(65), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:189:17 + 46: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(70), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 47: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 48: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 49: Copy { + dest: StatePartIndex(26), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:84:31 + 50: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 51: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 52: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 53: Copy { + dest: StatePartIndex(23), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 54: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + value: 0x0, + }, + // at: ready_valid.rs:91:19 + 55: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(15), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + }, + 56: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 57: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 58: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x2 2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + }, + 59: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 60: BranchIfSmallZero { + target: 63, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 61: MemoryReadUInt { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 3>, + // data: [ + // // len = 0x3 + // [0x0]: 0x2a, + // [0x1]: 0x28, + // [0x2]: 0x29, + // ], + // }) (), + addr: StatePartIndex(6), // (0x2 2) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 62: Branch { + target: 64, + }, + 63: Const { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 64: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 65: Copy { + dest: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 66: Shl { + dest: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 67: Or { + dest: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + }, + 68: CastToUInt { + dest: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 69: Copy { + dest: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 70: BranchIfZero { + target: 72, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 71: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 72: BranchIfNonZero { + target: 74, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:134:13 + 73: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(2), // (0x55) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 74: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 75: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 76: Copy { + dest: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 77: SliceInt { + dest: StatePartIndex(9), // (0x29) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 78: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 79: BranchIfSmallNeImmediate { + target: 81, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 80: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 81: BranchIfSmallNeImmediate { + target: 83, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 82: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 83: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 84: BranchIfZero { + target: 89, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 85: BranchIfZero { + target: 87, + value: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 86: Copy { + dest: StatePartIndex(26), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:158:9 + 87: BranchIfNonZero { + target: 89, + value: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 88: Copy { + dest: StatePartIndex(26), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(62), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 89: Copy { + dest: StatePartIndex(4), // (0x55) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x55) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 90: SliceInt { + dest: StatePartIndex(5), // (0x2a) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x55) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 91: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x55) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 92: BranchIfSmallNeImmediate { + target: 94, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 93: Copy { + dest: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 94: BranchIfSmallNeImmediate { + target: 96, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 95: Copy { + dest: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 96: Copy { + dest: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 97: Copy { + dest: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 98: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 99: CmpNe { + dest: StatePartIndex(53), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 100: BranchIfZero { + target: 102, + value: StatePartIndex(53), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 101: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 102: BranchIfZero { + target: 107, + value: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 103: BranchIfZero { + target: 105, + value: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 104: Copy { + dest: StatePartIndex(23), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:148:9 + 105: BranchIfNonZero { + target: 107, + value: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 106: Copy { + dest: StatePartIndex(23), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(59), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:118:30 + 107: BranchIfSmallNeImmediate { + target: 109, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 108: Copy { + dest: StatePartIndex(42), // (0x2a) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x2a) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 109: Copy { + dest: StatePartIndex(18), // (0x2a) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x2a) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 110: BranchIfSmallZero { + target: 115, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 111: BranchIfSmallNonZero { + target: 114, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 112: Copy { + dest: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(23), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + }, + 113: Branch { + target: 115, + }, + 114: Copy { + dest: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:86:25 + 115: BranchIfSmallZero { + target: 120, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 116: BranchIfSmallNonZero { + target: 119, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 117: Copy { + dest: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(26), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + }, + 118: Branch { + target: 120, + }, + 119: Copy { + dest: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 120: BranchIfSmallZero { + target: 125, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 121: BranchIfSmallNonZero { + target: 124, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 122: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 123: Branch { + target: 125, + }, + 124: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 125: BranchIfSmallZero { + target: 126, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 126: BranchIfSmallZero { + target: 134, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 127: CopySmall { + dest: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + }, + 128: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 129: Copy { + dest: StatePartIndex(20), // (0x2a) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x2a) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 130: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 131: BranchIfSmallZero { + target: 134, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 132: BranchIfZero { + target: 134, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 133: MemoryWriteUInt { + value: StatePartIndex(20), // (0x2a) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 3>, + // data: [ + // // len = 0x3 + // [0x0]: 0x2a, + // [0x1]: 0x28, + // [0x2]: 0x29, + // ], + // }) (), + addr: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 134: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 135: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 136: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 137: Return, + ], + .. + }, + pc: 137, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 3>, + data: [ + // len = 0x3 + [0x0]: 0x2a, + [0x1]: 0x28, + [0x2]: 0x29, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 2, + 1, + 0, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 85, + 1, + 85, + 42, + 83, + 0, + 83, + 41, + 2, + 2, + 1, + 0, + 41, + 1, + 1, + 0, + 42, + 1, + 42, + 1, + 1, + 2, + 0, + 2, + 2, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 42, + 0, + 1, + 1, + 1, + 41, + 1, + 82, + 83, + 83, + 83, + 1, + 2, + 0, + 0, + 0, + 2, + 2, + 1, + 3, + 3, + 3, + 3, + 1, + 4, + 2, + 2, + 7, + 3, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<2>, + flow: Sink, + }, + ty: UInt<2>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 3, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 3>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x2a, + last_state: 0x2a, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x2a, + last_state: 0x2a, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x2a, + last_state: 0x2a, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 3, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 3>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_3_false_true.vcd b/crates/fayalite/tests/sim/expected/queue_3_false_true.vcd new file mode 100644 index 0000000..622613c --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_3_false_true.vcd @@ -0,0 +1,2002 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 2 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$scope struct \[1] $end +$var reg 8 5F$iE mem $end +$upscope $end +$scope struct \[2] $end +$var reg 8 !BEt5 mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 2 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var wire 2 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var reg 2 Xk?#v inp_index_reg $end +$var reg 2 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 73, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<66>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 3>, + data: [ + // len = 0x3 + [0x0]: 0x00, + [0x1]: 0x00, + [0x2]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(71), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + dest_width: 3, + }, + 1: CastToUInt { + dest: StatePartIndex(72), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(71), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 2: CmpLt { + dest: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + 3: Const { + dest: StatePartIndex(65), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x3, + }, + 4: CastToUInt { + dest: StatePartIndex(66), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(65), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 2, + }, + 5: Add { + dest: StatePartIndex(68), // (0x5) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(65), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + }, + 6: SubU { + dest: StatePartIndex(69), // (0x3) SlotDebugData { name: "", ty: UInt<66> }, + lhs: StatePartIndex(68), // (0x5) SlotDebugData { name: "", ty: UInt<65> }, + rhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + dest_width: 66, + }, + 7: CastToUInt { + dest: StatePartIndex(70), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(69), // (0x3) SlotDebugData { name: "", ty: UInt<66> }, + dest_width: 2, + }, + 8: Const { + dest: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 9: CastToUInt { + dest: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 2, + }, + 10: Const { + dest: StatePartIndex(56), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x2, + }, + 11: CmpEq { + dest: StatePartIndex(57), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(56), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + }, + 12: CmpEq { + dest: StatePartIndex(62), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(56), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + }, + 13: Const { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + value: 0x0, + }, + 14: Copy { + dest: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + }, + 15: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 16: Add { + dest: StatePartIndex(60), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 17: CastToUInt { + dest: StatePartIndex(61), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(60), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 18: Add { + dest: StatePartIndex(63), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 19: CastToUInt { + dest: StatePartIndex(64), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(63), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 20: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 21: Copy { + dest: StatePartIndex(42), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 22: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 23: Copy { + dest: StatePartIndex(15), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + src: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:114:5 + 24: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 25: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 26: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 27: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 28: Copy { + dest: StatePartIndex(11), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + src: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 29: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 30: CmpEq { + dest: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:104:5 + 31: Copy { + dest: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 32: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 33: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 34: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 35: And { + dest: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 36: Copy { + dest: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 37: NotU { + dest: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 38: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:124:9 + 39: BranchIfZero { + target: 41, + value: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:125:13 + 40: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 41: BranchIfZero { + target: 46, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 42: BranchIfZero { + target: 44, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 43: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(66), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:168:9 + 44: BranchIfNonZero { + target: 46, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 45: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:166:5 + 46: BranchIfNonZero { + target: 51, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:186:13 + 47: BranchIfZero { + target: 49, + value: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:187:17 + 48: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(70), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:186:13 + 49: BranchIfNonZero { + target: 51, + value: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:189:17 + 50: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(72), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 51: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 52: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 53: Copy { + dest: StatePartIndex(26), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:84:31 + 54: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 55: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 56: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 57: Copy { + dest: StatePartIndex(23), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 58: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + value: 0x0, + }, + // at: ready_valid.rs:91:19 + 59: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x2 2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(15), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + }, + 60: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 61: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 62: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x2 2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + }, + 63: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 64: BranchIfSmallZero { + target: 67, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 65: MemoryReadUInt { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 3>, + // data: [ + // // len = 0x3 + // [0x0]: 0x2a, + // [0x1]: 0x2b, + // [0x2]: 0x29, + // ], + // }) (), + addr: StatePartIndex(6), // (0x2 2) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 66: Branch { + target: 68, + }, + 67: Const { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 68: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 69: Copy { + dest: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 70: Shl { + dest: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 71: Or { + dest: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + }, + 72: CastToUInt { + dest: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 73: Copy { + dest: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 74: BranchIfZero { + target: 76, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 75: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 76: BranchIfNonZero { + target: 78, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:136:13 + 77: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 78: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 79: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 80: Copy { + dest: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 81: SliceInt { + dest: StatePartIndex(9), // (0x29) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 82: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 83: BranchIfSmallNeImmediate { + target: 85, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 84: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 85: BranchIfSmallNeImmediate { + target: 87, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 86: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 87: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 88: BranchIfZero { + target: 93, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 89: BranchIfZero { + target: 91, + value: StatePartIndex(62), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 90: Copy { + dest: StatePartIndex(26), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:158:9 + 91: BranchIfNonZero { + target: 93, + value: StatePartIndex(62), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 92: Copy { + dest: StatePartIndex(26), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(64), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 93: Copy { + dest: StatePartIndex(4), // (0x57) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x57) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 94: SliceInt { + dest: StatePartIndex(5), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x57) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 95: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x57) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 96: BranchIfSmallNeImmediate { + target: 98, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 97: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 98: BranchIfSmallNeImmediate { + target: 100, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 99: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 100: Copy { + dest: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 101: Copy { + dest: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 102: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 103: CmpNe { + dest: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 104: BranchIfZero { + target: 106, + value: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 105: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 106: BranchIfZero { + target: 111, + value: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 107: BranchIfZero { + target: 109, + value: StatePartIndex(57), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 108: Copy { + dest: StatePartIndex(23), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:148:9 + 109: BranchIfNonZero { + target: 111, + value: StatePartIndex(57), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 110: Copy { + dest: StatePartIndex(23), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(61), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:118:30 + 111: BranchIfSmallNeImmediate { + target: 113, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 112: Copy { + dest: StatePartIndex(42), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 113: Copy { + dest: StatePartIndex(18), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 114: BranchIfSmallZero { + target: 119, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 115: BranchIfSmallNonZero { + target: 118, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 116: Copy { + dest: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(23), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + }, + 117: Branch { + target: 119, + }, + 118: Copy { + dest: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:86:25 + 119: BranchIfSmallZero { + target: 124, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 120: BranchIfSmallNonZero { + target: 123, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 121: Copy { + dest: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(26), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + }, + 122: Branch { + target: 124, + }, + 123: Copy { + dest: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 124: BranchIfSmallZero { + target: 129, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 125: BranchIfSmallNonZero { + target: 128, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 126: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 127: Branch { + target: 129, + }, + 128: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 129: BranchIfSmallZero { + target: 130, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 130: BranchIfSmallZero { + target: 138, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 131: CopySmall { + dest: StatePartIndex(12), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x2 2) SlotDebugData { name: "", ty: UInt<2> }, + }, + 132: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 133: Copy { + dest: StatePartIndex(20), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 134: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 135: BranchIfSmallZero { + target: 138, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 136: BranchIfZero { + target: 138, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 137: MemoryWriteUInt { + value: StatePartIndex(20), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 3>, + // data: [ + // // len = 0x3 + // [0x0]: 0x2a, + // [0x1]: 0x2b, + // [0x2]: 0x29, + // ], + // }) (), + addr: StatePartIndex(12), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 138: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 139: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 140: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 141: Return, + ], + .. + }, + pc: 141, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 3>, + data: [ + // len = 0x3 + [0x0]: 0x2a, + [0x1]: 0x2b, + [0x2]: 0x29, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 2, + 1, + 0, + 0, + 0, + 2, + 1, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 87, + 0, + 87, + 43, + 83, + 0, + 83, + 41, + 3, + 2, + 1, + 0, + 41, + 2, + 0, + 0, + 43, + 1, + 43, + 1, + 2, + 2, + 0, + 2, + 2, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 43, + 0, + 0, + 1, + 1, + 41, + 1, + 82, + 83, + 83, + 83, + 0, + 0, + 0, + 2, + 1, + 0, + 0, + 3, + 3, + 1, + 3, + 3, + 3, + 3, + 0, + 5, + 3, + 3, + 0, + 0, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<2>, + flow: Sink, + }, + ty: UInt<2>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 3, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 3>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x2b, + last_state: 0x2b, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x3, + last_state: 0x3, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x2b, + last_state: 0x2b, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x2b, + last_state: 0x2b, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 3, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 3>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_3_true_false.vcd b/crates/fayalite/tests/sim/expected/queue_3_true_false.vcd new file mode 100644 index 0000000..53d6937 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_3_true_false.vcd @@ -0,0 +1,1949 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 2 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$scope struct \[1] $end +$var reg 8 5F$iE mem $end +$upscope $end +$scope struct \[2] $end +$var reg 8 !BEt5 mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 2 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var wire 2 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var reg 2 Xk?#v inp_index_reg $end +$var reg 2 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 71, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<66>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 3>, + data: [ + // len = 0x3 + [0x0]: 0x00, + [0x1]: 0x00, + [0x2]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + dest_width: 3, + }, + 1: CastToUInt { + dest: StatePartIndex(70), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 2: CmpLt { + dest: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + 3: Const { + dest: StatePartIndex(63), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x3, + }, + 4: CastToUInt { + dest: StatePartIndex(64), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(63), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 2, + }, + 5: Add { + dest: StatePartIndex(66), // (0x5) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(63), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + }, + 6: SubU { + dest: StatePartIndex(67), // (0x3) SlotDebugData { name: "", ty: UInt<66> }, + lhs: StatePartIndex(66), // (0x5) SlotDebugData { name: "", ty: UInt<65> }, + rhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + dest_width: 66, + }, + 7: CastToUInt { + dest: StatePartIndex(68), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(67), // (0x3) SlotDebugData { name: "", ty: UInt<66> }, + dest_width: 2, + }, + 8: Const { + dest: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 9: CastToUInt { + dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 2, + }, + 10: Const { + dest: StatePartIndex(54), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x2, + }, + 11: CmpEq { + dest: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(54), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + }, + 12: CmpEq { + dest: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(54), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + }, + 13: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 14: Add { + dest: StatePartIndex(58), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 15: CastToUInt { + dest: StatePartIndex(59), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(58), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 16: Add { + dest: StatePartIndex(61), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 17: CastToUInt { + dest: StatePartIndex(62), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(61), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 18: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 19: Copy { + dest: StatePartIndex(42), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 20: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 21: Copy { + dest: StatePartIndex(15), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + src: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:114:5 + 22: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 23: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 24: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 25: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 26: Copy { + dest: StatePartIndex(11), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + src: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 27: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 28: CmpEq { + dest: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:104:5 + 29: Copy { + dest: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 30: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 31: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 32: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 33: And { + dest: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 34: Copy { + dest: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 35: NotU { + dest: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 36: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:124:9 + 37: BranchIfZero { + target: 39, + value: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:125:13 + 38: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 39: BranchIfZero { + target: 44, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 40: BranchIfZero { + target: 42, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 41: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(64), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:168:9 + 42: BranchIfNonZero { + target: 44, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 43: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:166:5 + 44: BranchIfNonZero { + target: 49, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:186:13 + 45: BranchIfZero { + target: 47, + value: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:187:17 + 46: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(68), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:186:13 + 47: BranchIfNonZero { + target: 49, + value: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:189:17 + 48: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(70), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 49: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 50: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 51: Copy { + dest: StatePartIndex(26), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:84:31 + 52: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 53: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 54: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 55: Copy { + dest: StatePartIndex(23), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 56: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + value: 0x0, + }, + // at: ready_valid.rs:91:19 + 57: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x2 2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(15), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + }, + 58: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 59: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 60: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x2 2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + }, + 61: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 62: BranchIfSmallZero { + target: 65, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 63: MemoryReadUInt { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 3>, + // data: [ + // // len = 0x3 + // [0x0]: 0x2a, + // [0x1]: 0x2b, + // [0x2]: 0x29, + // ], + // }) (), + addr: StatePartIndex(6), // (0x2 2) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 64: Branch { + target: 66, + }, + 65: Const { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 66: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 67: Copy { + dest: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 68: Shl { + dest: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 69: Or { + dest: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + }, + 70: CastToUInt { + dest: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 71: Copy { + dest: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 72: BranchIfZero { + target: 74, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 73: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 74: BranchIfNonZero { + target: 76, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:134:13 + 75: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(2), // (0x57) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 76: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 77: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 78: Copy { + dest: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 79: SliceInt { + dest: StatePartIndex(9), // (0x29) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 80: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 81: BranchIfSmallNeImmediate { + target: 83, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 82: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 83: BranchIfSmallNeImmediate { + target: 85, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 84: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 85: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 86: BranchIfZero { + target: 91, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 87: BranchIfZero { + target: 89, + value: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 88: Copy { + dest: StatePartIndex(26), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:158:9 + 89: BranchIfNonZero { + target: 91, + value: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 90: Copy { + dest: StatePartIndex(26), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(62), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 91: Copy { + dest: StatePartIndex(4), // (0x57) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x57) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 92: SliceInt { + dest: StatePartIndex(5), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x57) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 93: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x57) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 94: BranchIfSmallNeImmediate { + target: 96, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 95: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 96: BranchIfSmallNeImmediate { + target: 98, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 97: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 98: Copy { + dest: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 99: Copy { + dest: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 100: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 101: CmpNe { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 102: BranchIfZero { + target: 104, + value: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 103: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 104: BranchIfZero { + target: 109, + value: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 105: BranchIfZero { + target: 107, + value: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 106: Copy { + dest: StatePartIndex(23), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:148:9 + 107: BranchIfNonZero { + target: 109, + value: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 108: Copy { + dest: StatePartIndex(23), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(59), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:118:30 + 109: BranchIfSmallNeImmediate { + target: 111, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 110: Copy { + dest: StatePartIndex(42), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 111: Copy { + dest: StatePartIndex(18), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 112: BranchIfSmallZero { + target: 117, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 113: BranchIfSmallNonZero { + target: 116, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 114: Copy { + dest: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(23), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + }, + 115: Branch { + target: 117, + }, + 116: Copy { + dest: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:86:25 + 117: BranchIfSmallZero { + target: 122, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 118: BranchIfSmallNonZero { + target: 121, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 119: Copy { + dest: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(26), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + }, + 120: Branch { + target: 122, + }, + 121: Copy { + dest: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 122: BranchIfSmallZero { + target: 127, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 123: BranchIfSmallNonZero { + target: 126, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 124: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 125: Branch { + target: 127, + }, + 126: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 127: BranchIfSmallZero { + target: 128, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 128: BranchIfSmallZero { + target: 136, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 129: CopySmall { + dest: StatePartIndex(12), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x2 2) SlotDebugData { name: "", ty: UInt<2> }, + }, + 130: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 131: Copy { + dest: StatePartIndex(20), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 132: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 133: BranchIfSmallZero { + target: 136, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 134: BranchIfZero { + target: 136, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 135: MemoryWriteUInt { + value: StatePartIndex(20), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 3>, + // data: [ + // // len = 0x3 + // [0x0]: 0x2a, + // [0x1]: 0x2b, + // [0x2]: 0x29, + // ], + // }) (), + addr: StatePartIndex(12), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 136: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 137: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 138: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 139: Return, + ], + .. + }, + pc: 139, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 3>, + data: [ + // len = 0x3 + [0x0]: 0x2a, + [0x1]: 0x2b, + [0x2]: 0x29, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 2, + 1, + 0, + 0, + 0, + 2, + 1, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 87, + 0, + 87, + 43, + 83, + 0, + 83, + 41, + 3, + 2, + 1, + 0, + 41, + 2, + 0, + 0, + 43, + 1, + 43, + 1, + 2, + 2, + 0, + 2, + 2, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 43, + 0, + 0, + 1, + 1, + 41, + 1, + 82, + 83, + 83, + 83, + 0, + 2, + 1, + 0, + 0, + 3, + 3, + 1, + 3, + 3, + 3, + 3, + 0, + 5, + 3, + 3, + 0, + 0, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<2>, + flow: Sink, + }, + ty: UInt<2>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 3, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 3>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x2b, + last_state: 0x2b, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x3, + last_state: 0x3, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x2b, + last_state: 0x2b, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x2b, + last_state: 0x2b, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 3, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 3>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_3_true_true.vcd b/crates/fayalite/tests/sim/expected/queue_3_true_true.vcd new file mode 100644 index 0000000..1c178a6 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_3_true_true.vcd @@ -0,0 +1,1935 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 2 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$scope struct \[1] $end +$var reg 8 5F$iE mem $end +$upscope $end +$scope struct \[2] $end +$var reg 8 !BEt5 mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 2 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var wire 2 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var reg 2 Xk?#v inp_index_reg $end +$var reg 2 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 72, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count_lower", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 4>, + data: [ + // len = 0x4 + [0x0]: 0x00, + [0x1]: 0x00, + [0x2]: 0x00, + [0x3]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(69), // (0x7) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + dest_width: 3, + }, + 1: CastToUInt { + dest: StatePartIndex(70), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(69), // (0x7) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + // at: ready_valid.rs:178:13 + 2: Copy { + dest: StatePartIndex(68), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<2> }, + src: StatePartIndex(70), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 3: CastToUInt { + dest: StatePartIndex(71), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(68), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<2> }, + dest_width: 3, + }, + 4: Const { + dest: StatePartIndex(65), // (0x4) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x4, + }, + 5: CastToUInt { + dest: StatePartIndex(66), // (0x4) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(65), // (0x4) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 3, + }, + 6: Const { + dest: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 7: CastToUInt { + dest: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 2, + }, + 8: CastToUInt { + dest: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 3, + }, + 9: Const { + dest: StatePartIndex(56), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x3, + }, + 10: CmpEq { + dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(56), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + }, + 11: CmpEq { + dest: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(56), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + }, + 12: Const { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + value: 0x0, + }, + 13: Copy { + dest: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + }, + 14: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 15: Add { + dest: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 16: CastToUInt { + dest: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 17: Add { + dest: StatePartIndex(63), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 18: CastToUInt { + dest: StatePartIndex(64), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(63), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 19: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 20: Copy { + dest: StatePartIndex(42), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 21: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 22: Copy { + dest: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:114:5 + 23: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 24: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 25: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 26: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 27: Copy { + dest: StatePartIndex(11), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 28: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 29: CmpEq { + dest: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:104:5 + 30: Copy { + dest: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 31: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 32: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 33: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 34: And { + dest: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 35: Copy { + dest: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 36: NotU { + dest: StatePartIndex(44), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 37: Copy { + dest: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 38: BranchIfZero { + target: 43, + value: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 39: BranchIfZero { + target: 41, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 40: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<3> }, + src: StatePartIndex(66), // (0x4) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: ready_valid.rs:168:9 + 41: BranchIfNonZero { + target: 43, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 42: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<3> }, + src: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: ready_valid.rs:166:5 + 43: BranchIfNonZero { + target: 45, + value: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:182:13 + 44: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<3> }, + src: StatePartIndex(71), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: ready_valid.rs:88:26 + 45: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 46: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 47: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:84:31 + 48: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 49: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 50: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 51: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 52: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + value: 0x0, + }, + // at: ready_valid.rs:91:19 + 53: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + }, + 54: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 55: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 56: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + }, + 57: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 58: BranchIfSmallZero { + target: 61, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 59: MemoryReadUInt { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 4>, + // data: [ + // // len = 0x4 + // [0x0]: 0x28, + // [0x1]: 0x29, + // [0x2]: 0x2a, + // [0x3]: 0x2b, + // ], + // }) (), + addr: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 60: Branch { + target: 62, + }, + 61: Const { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 62: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 63: Copy { + dest: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 64: Shl { + dest: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 65: Or { + dest: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + }, + 66: CastToUInt { + dest: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 67: Copy { + dest: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 68: BranchIfZero { + target: 70, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 69: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 70: BranchIfNonZero { + target: 72, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:136:13 + 71: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 72: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 73: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 74: Copy { + dest: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 75: SliceInt { + dest: StatePartIndex(9), // (0x29) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 76: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 77: BranchIfSmallNeImmediate { + target: 79, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 78: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 79: BranchIfSmallNeImmediate { + target: 81, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 80: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 81: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 82: BranchIfZero { + target: 87, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 83: BranchIfZero { + target: 85, + value: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 84: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:158:9 + 85: BranchIfNonZero { + target: 87, + value: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 86: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(64), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 87: Copy { + dest: StatePartIndex(4), // (0x57) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x57) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 88: SliceInt { + dest: StatePartIndex(5), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x57) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 89: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x57) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 90: BranchIfSmallNeImmediate { + target: 92, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 91: Copy { + dest: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 92: BranchIfSmallNeImmediate { + target: 94, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 93: Copy { + dest: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 94: Copy { + dest: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 95: Copy { + dest: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 96: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 97: CmpNe { + dest: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 98: BranchIfZero { + target: 100, + value: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 99: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 100: BranchIfZero { + target: 105, + value: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 101: BranchIfZero { + target: 103, + value: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 102: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:148:9 + 103: BranchIfNonZero { + target: 105, + value: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 104: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:118:30 + 105: BranchIfSmallNeImmediate { + target: 107, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 106: Copy { + dest: StatePartIndex(42), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 107: Copy { + dest: StatePartIndex(18), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 108: BranchIfSmallZero { + target: 113, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 109: BranchIfSmallNonZero { + target: 112, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 110: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + }, + 111: Branch { + target: 113, + }, + 112: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:86:25 + 113: BranchIfSmallZero { + target: 118, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 114: BranchIfSmallNonZero { + target: 117, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 115: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + }, + 116: Branch { + target: 118, + }, + 117: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 118: BranchIfSmallZero { + target: 123, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 119: BranchIfSmallNonZero { + target: 122, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 120: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 121: Branch { + target: 123, + }, + 122: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 123: BranchIfSmallZero { + target: 124, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 124: BranchIfSmallZero { + target: 132, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 125: CopySmall { + dest: StatePartIndex(12), // (0x3 3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<2> }, + }, + 126: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 127: Copy { + dest: StatePartIndex(20), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 128: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 129: BranchIfSmallZero { + target: 132, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 130: BranchIfZero { + target: 132, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 131: MemoryWriteUInt { + value: StatePartIndex(20), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 4>, + // data: [ + // // len = 0x4 + // [0x0]: 0x28, + // [0x1]: 0x29, + // [0x2]: 0x2a, + // [0x3]: 0x2b, + // ], + // }) (), + addr: StatePartIndex(12), // (0x3 3) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 132: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 133: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 134: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 135: Return, + ], + .. + }, + pc: 135, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 4>, + data: [ + // len = 0x4 + [0x0]: 0x28, + [0x1]: 0x29, + [0x2]: 0x2a, + [0x3]: 0x2b, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 1, + 1, + 0, + 0, + 1, + 0, + 3, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 87, + 1, + 87, + 43, + 83, + 0, + 83, + 41, + 3, + 1, + 1, + 0, + 41, + 0, + 1, + 0, + 43, + 1, + 43, + 1, + 0, + 1, + 0, + 1, + 1, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 43, + 0, + 1, + 1, + 1, + 41, + 1, + 82, + 83, + 83, + 83, + 0, + 0, + 1, + 3, + 0, + 0, + 0, + 1, + 1, + 0, + 2, + 2, + 4, + 4, + 0, + 3, + 7, + 3, + 3, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<3>, + flow: Sink, + }, + ty: UInt<3>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 4, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 4>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + TraceWire { + name: "count_lower", + child: TraceUInt { + location: TraceScalarId(29), + name: "count_lower", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x2b, + last_state: 0x2b, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<3>, + }, + maybe_changed: true, + state: 0x3, + last_state: 0x3, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x2b, + last_state: 0x2b, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x2b, + last_state: 0x2b, + }, + SimTrace { + id: TraceScalarId(29), + kind: BigUInt { + index: StatePartIndex(68), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x3, + last_state: 0x3, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 4, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 4>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_4_false_false.vcd b/crates/fayalite/tests/sim/expected/queue_4_false_false.vcd new file mode 100644 index 0000000..5373a84 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_4_false_false.vcd @@ -0,0 +1,2025 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 3 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$scope struct \[1] $end +$var reg 8 5F$iE mem $end +$upscope $end +$scope struct \[2] $end +$var reg 8 !BEt5 mem $end +$upscope $end +$scope struct \[3] $end +$var reg 8 C7]kZ mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 2 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var wire 2 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var reg 2 Xk?#v inp_index_reg $end +$var reg 2 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 70, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count_lower", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 4>, + data: [ + // len = 0x4 + [0x0]: 0x00, + [0x1]: 0x00, + [0x2]: 0x00, + [0x3]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(67), // (0x7) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + dest_width: 3, + }, + 1: CastToUInt { + dest: StatePartIndex(68), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(67), // (0x7) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + // at: ready_valid.rs:178:13 + 2: Copy { + dest: StatePartIndex(66), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<2> }, + src: StatePartIndex(68), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 3: CastToUInt { + dest: StatePartIndex(69), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(66), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<2> }, + dest_width: 3, + }, + 4: Const { + dest: StatePartIndex(63), // (0x4) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x4, + }, + 5: CastToUInt { + dest: StatePartIndex(64), // (0x4) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(63), // (0x4) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 3, + }, + 6: Const { + dest: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 7: CastToUInt { + dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 2, + }, + 8: CastToUInt { + dest: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 3, + }, + 9: Const { + dest: StatePartIndex(54), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x3, + }, + 10: CmpEq { + dest: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(54), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + }, + 11: CmpEq { + dest: StatePartIndex(60), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(54), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + }, + 12: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 13: Add { + dest: StatePartIndex(58), // (0x1) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 14: CastToUInt { + dest: StatePartIndex(59), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(58), // (0x1) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 15: Add { + dest: StatePartIndex(61), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 16: CastToUInt { + dest: StatePartIndex(62), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(61), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 17: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 18: Copy { + dest: StatePartIndex(42), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 19: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 20: Copy { + dest: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:114:5 + 21: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 22: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 23: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 24: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 25: Copy { + dest: StatePartIndex(11), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 26: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 27: CmpEq { + dest: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:104:5 + 28: Copy { + dest: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 29: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 30: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 31: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 32: And { + dest: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 33: Copy { + dest: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 34: NotU { + dest: StatePartIndex(44), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 35: Copy { + dest: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 36: BranchIfZero { + target: 41, + value: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 37: BranchIfZero { + target: 39, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 38: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<3> }, + src: StatePartIndex(64), // (0x4) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: ready_valid.rs:168:9 + 39: BranchIfNonZero { + target: 41, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 40: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<3> }, + src: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: ready_valid.rs:166:5 + 41: BranchIfNonZero { + target: 43, + value: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:182:13 + 42: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<3> }, + src: StatePartIndex(69), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: ready_valid.rs:88:26 + 43: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 44: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 45: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:84:31 + 46: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 47: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 48: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 49: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 50: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + value: 0x0, + }, + // at: ready_valid.rs:91:19 + 51: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + }, + 52: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 53: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 54: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + }, + 55: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 56: BranchIfSmallZero { + target: 59, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 57: MemoryReadUInt { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 4>, + // data: [ + // // len = 0x4 + // [0x0]: 0x28, + // [0x1]: 0x29, + // [0x2]: 0x2a, + // [0x3]: 0x2b, + // ], + // }) (), + addr: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 58: Branch { + target: 60, + }, + 59: Const { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 60: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 61: Copy { + dest: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 62: Shl { + dest: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 63: Or { + dest: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + }, + 64: CastToUInt { + dest: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 65: Copy { + dest: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 66: BranchIfZero { + target: 68, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 67: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 68: BranchIfNonZero { + target: 70, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:134:13 + 69: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(2), // (0x57) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 70: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 71: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 72: Copy { + dest: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 73: SliceInt { + dest: StatePartIndex(9), // (0x29) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 74: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 75: BranchIfSmallNeImmediate { + target: 77, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 76: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 77: BranchIfSmallNeImmediate { + target: 79, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 78: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 79: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 80: BranchIfZero { + target: 85, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 81: BranchIfZero { + target: 83, + value: StatePartIndex(60), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 82: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:158:9 + 83: BranchIfNonZero { + target: 85, + value: StatePartIndex(60), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 84: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(62), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 85: Copy { + dest: StatePartIndex(4), // (0x57) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x57) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 86: SliceInt { + dest: StatePartIndex(5), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x57) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 87: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x57) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 88: BranchIfSmallNeImmediate { + target: 90, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 89: Copy { + dest: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 90: BranchIfSmallNeImmediate { + target: 92, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 91: Copy { + dest: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 92: Copy { + dest: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 93: Copy { + dest: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 94: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 95: CmpNe { + dest: StatePartIndex(53), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 96: BranchIfZero { + target: 98, + value: StatePartIndex(53), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 97: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 98: BranchIfZero { + target: 103, + value: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 99: BranchIfZero { + target: 101, + value: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 100: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:148:9 + 101: BranchIfNonZero { + target: 103, + value: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 102: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(59), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:118:30 + 103: BranchIfSmallNeImmediate { + target: 105, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 104: Copy { + dest: StatePartIndex(42), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 105: Copy { + dest: StatePartIndex(18), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 106: BranchIfSmallZero { + target: 111, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 107: BranchIfSmallNonZero { + target: 110, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 108: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + }, + 109: Branch { + target: 111, + }, + 110: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:86:25 + 111: BranchIfSmallZero { + target: 116, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 112: BranchIfSmallNonZero { + target: 115, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 113: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + }, + 114: Branch { + target: 116, + }, + 115: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 116: BranchIfSmallZero { + target: 121, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 117: BranchIfSmallNonZero { + target: 120, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 118: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 119: Branch { + target: 121, + }, + 120: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 121: BranchIfSmallZero { + target: 122, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 122: BranchIfSmallZero { + target: 130, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 123: CopySmall { + dest: StatePartIndex(12), // (0x3 3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<2> }, + }, + 124: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 125: Copy { + dest: StatePartIndex(20), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 126: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 127: BranchIfSmallZero { + target: 130, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 128: BranchIfZero { + target: 130, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 129: MemoryWriteUInt { + value: StatePartIndex(20), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 4>, + // data: [ + // // len = 0x4 + // [0x0]: 0x28, + // [0x1]: 0x29, + // [0x2]: 0x2a, + // [0x3]: 0x2b, + // ], + // }) (), + addr: StatePartIndex(12), // (0x3 3) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 130: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 131: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 132: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 133: Return, + ], + .. + }, + pc: 133, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 4>, + data: [ + // len = 0x4 + [0x0]: 0x28, + [0x1]: 0x29, + [0x2]: 0x2a, + [0x3]: 0x2b, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 1, + 1, + 0, + 0, + 1, + 0, + 3, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 87, + 1, + 87, + 43, + 83, + 0, + 83, + 41, + 3, + 1, + 1, + 0, + 41, + 0, + 1, + 0, + 43, + 1, + 43, + 1, + 0, + 1, + 0, + 1, + 1, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 43, + 0, + 1, + 1, + 1, + 41, + 1, + 82, + 83, + 83, + 83, + 1, + 3, + 0, + 0, + 0, + 1, + 1, + 0, + 2, + 2, + 4, + 4, + 0, + 3, + 7, + 3, + 3, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<3>, + flow: Sink, + }, + ty: UInt<3>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 4, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 4>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + TraceWire { + name: "count_lower", + child: TraceUInt { + location: TraceScalarId(29), + name: "count_lower", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x2b, + last_state: 0x2b, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<3>, + }, + maybe_changed: true, + state: 0x3, + last_state: 0x3, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x2b, + last_state: 0x2b, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x2b, + last_state: 0x2b, + }, + SimTrace { + id: TraceScalarId(29), + kind: BigUInt { + index: StatePartIndex(66), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x3, + last_state: 0x3, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 4, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 4>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_4_false_true.vcd b/crates/fayalite/tests/sim/expected/queue_4_false_true.vcd new file mode 100644 index 0000000..bed1241 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_4_false_true.vcd @@ -0,0 +1,2021 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 3 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$scope struct \[1] $end +$var reg 8 5F$iE mem $end +$upscope $end +$scope struct \[2] $end +$var reg 8 !BEt5 mem $end +$upscope $end +$scope struct \[3] $end +$var reg 8 C7]kZ mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 2 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var wire 2 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var reg 2 Xk?#v inp_index_reg $end +$var reg 2 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 72, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count_lower", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 4>, + data: [ + // len = 0x4 + [0x0]: 0x00, + [0x1]: 0x00, + [0x2]: 0x00, + [0x3]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + dest_width: 3, + }, + 1: CastToUInt { + dest: StatePartIndex(70), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + // at: ready_valid.rs:178:13 + 2: Copy { + dest: StatePartIndex(68), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<2> }, + src: StatePartIndex(70), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 3: CastToUInt { + dest: StatePartIndex(71), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(68), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<2> }, + dest_width: 3, + }, + 4: Const { + dest: StatePartIndex(65), // (0x4) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x4, + }, + 5: CastToUInt { + dest: StatePartIndex(66), // (0x4) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(65), // (0x4) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 3, + }, + 6: Const { + dest: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 7: CastToUInt { + dest: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 2, + }, + 8: CastToUInt { + dest: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 3, + }, + 9: Const { + dest: StatePartIndex(56), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x3, + }, + 10: CmpEq { + dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(56), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + }, + 11: CmpEq { + dest: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(56), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + }, + 12: Const { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + value: 0x0, + }, + 13: Copy { + dest: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + }, + 14: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 15: Add { + dest: StatePartIndex(60), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 16: CastToUInt { + dest: StatePartIndex(61), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(60), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 17: Add { + dest: StatePartIndex(63), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 18: CastToUInt { + dest: StatePartIndex(64), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(63), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 19: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 20: Copy { + dest: StatePartIndex(42), // (0x2c) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 21: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 22: Copy { + dest: StatePartIndex(15), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:114:5 + 23: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 24: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 25: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 26: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 27: Copy { + dest: StatePartIndex(11), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 28: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 29: CmpEq { + dest: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:104:5 + 30: Copy { + dest: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 31: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 32: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 33: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 34: And { + dest: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 35: Copy { + dest: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 36: NotU { + dest: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 37: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:124:9 + 38: BranchIfZero { + target: 40, + value: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:125:13 + 39: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 40: BranchIfZero { + target: 45, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 41: BranchIfZero { + target: 43, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 42: Copy { + dest: StatePartIndex(10), // (0x4) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<3> }, + src: StatePartIndex(66), // (0x4) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: ready_valid.rs:168:9 + 43: BranchIfNonZero { + target: 45, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 44: Copy { + dest: StatePartIndex(10), // (0x4) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<3> }, + src: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: ready_valid.rs:166:5 + 45: BranchIfNonZero { + target: 47, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:182:13 + 46: Copy { + dest: StatePartIndex(10), // (0x4) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<3> }, + src: StatePartIndex(71), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: ready_valid.rs:88:26 + 47: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 48: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 49: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:84:31 + 50: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 51: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 52: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 53: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 54: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + value: 0x0, + }, + // at: ready_valid.rs:91:19 + 55: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(15), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + }, + 56: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 57: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 58: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + }, + 59: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 60: BranchIfSmallZero { + target: 63, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 61: MemoryReadUInt { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 4>, + // data: [ + // // len = 0x4 + // [0x0]: 0x2c, + // [0x1]: 0x29, + // [0x2]: 0x2a, + // [0x3]: 0x2b, + // ], + // }) (), + addr: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 62: Branch { + target: 64, + }, + 63: Const { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 64: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 65: Copy { + dest: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 66: Shl { + dest: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 67: Or { + dest: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + }, + 68: CastToUInt { + dest: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 69: Copy { + dest: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 70: BranchIfZero { + target: 72, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 71: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 72: BranchIfNonZero { + target: 74, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:136:13 + 73: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 74: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 75: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 76: Copy { + dest: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 77: SliceInt { + dest: StatePartIndex(9), // (0x29) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 78: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 79: BranchIfSmallNeImmediate { + target: 81, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 80: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 81: BranchIfSmallNeImmediate { + target: 83, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 82: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 83: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 84: BranchIfZero { + target: 89, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 85: BranchIfZero { + target: 87, + value: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 86: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:158:9 + 87: BranchIfNonZero { + target: 89, + value: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 88: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(64), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 89: Copy { + dest: StatePartIndex(4), // (0x59) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x59) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 90: SliceInt { + dest: StatePartIndex(5), // (0x2c) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x59) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 91: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x59) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 92: BranchIfSmallNeImmediate { + target: 94, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 93: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 94: BranchIfSmallNeImmediate { + target: 96, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 95: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 96: Copy { + dest: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 97: Copy { + dest: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 98: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 99: CmpNe { + dest: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 100: BranchIfZero { + target: 102, + value: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 101: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 102: BranchIfZero { + target: 107, + value: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 103: BranchIfZero { + target: 105, + value: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 104: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:148:9 + 105: BranchIfNonZero { + target: 107, + value: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 106: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(61), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:118:30 + 107: BranchIfSmallNeImmediate { + target: 109, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 108: Copy { + dest: StatePartIndex(42), // (0x2c) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x2c) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 109: Copy { + dest: StatePartIndex(18), // (0x2c) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x2c) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 110: BranchIfSmallZero { + target: 115, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 111: BranchIfSmallNonZero { + target: 114, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 112: Copy { + dest: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + }, + 113: Branch { + target: 115, + }, + 114: Copy { + dest: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:86:25 + 115: BranchIfSmallZero { + target: 120, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 116: BranchIfSmallNonZero { + target: 119, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 117: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + }, + 118: Branch { + target: 120, + }, + 119: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 120: BranchIfSmallZero { + target: 125, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 121: BranchIfSmallNonZero { + target: 124, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 122: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 123: Branch { + target: 125, + }, + 124: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 125: BranchIfSmallZero { + target: 126, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 126: BranchIfSmallZero { + target: 134, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 127: CopySmall { + dest: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + }, + 128: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 129: Copy { + dest: StatePartIndex(20), // (0x2c) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x2c) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 130: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 131: BranchIfSmallZero { + target: 134, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 132: BranchIfZero { + target: 134, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 133: MemoryWriteUInt { + value: StatePartIndex(20), // (0x2c) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 4>, + // data: [ + // // len = 0x4 + // [0x0]: 0x2c, + // [0x1]: 0x29, + // [0x2]: 0x2a, + // [0x3]: 0x2b, + // ], + // }) (), + addr: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 134: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 135: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 136: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 137: Return, + ], + .. + }, + pc: 137, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 4>, + data: [ + // len = 0x4 + [0x0]: 0x2c, + [0x1]: 0x29, + [0x2]: 0x2a, + [0x3]: 0x2b, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 1, + 1, + 0, + 0, + 0, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 89, + 0, + 89, + 44, + 83, + 0, + 83, + 41, + 4, + 1, + 1, + 0, + 41, + 1, + 0, + 0, + 44, + 1, + 44, + 1, + 1, + 1, + 0, + 1, + 1, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 44, + 0, + 0, + 1, + 1, + 41, + 1, + 82, + 83, + 83, + 83, + 0, + 0, + 0, + 3, + 0, + 0, + 0, + 2, + 2, + 0, + 2, + 2, + 4, + 4, + 0, + 0, + 0, + 0, + 0, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<3>, + flow: Sink, + }, + ty: UInt<3>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 4, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 4>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + TraceWire { + name: "count_lower", + child: TraceUInt { + location: TraceScalarId(29), + name: "count_lower", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x2c, + last_state: 0x2c, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<3>, + }, + maybe_changed: true, + state: 0x4, + last_state: 0x4, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x2c, + last_state: 0x2c, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x2c, + last_state: 0x2c, + }, + SimTrace { + id: TraceScalarId(29), + kind: BigUInt { + index: StatePartIndex(68), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 4, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 4>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_4_true_false.vcd b/crates/fayalite/tests/sim/expected/queue_4_true_false.vcd new file mode 100644 index 0000000..842a353 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_4_true_false.vcd @@ -0,0 +1,1993 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 3 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$scope struct \[1] $end +$var reg 8 5F$iE mem $end +$upscope $end +$scope struct \[2] $end +$var reg 8 !BEt5 mem $end +$upscope $end +$scope struct \[3] $end +$var reg 8 C7]kZ mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 2 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var wire 2 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var reg 2 Xk?#v inp_index_reg $end +$var reg 2 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 70, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count_lower", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 4>, + data: [ + // len = 0x4 + [0x0]: 0x00, + [0x1]: 0x00, + [0x2]: 0x00, + [0x3]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + dest_width: 3, + }, + 1: CastToUInt { + dest: StatePartIndex(68), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + // at: ready_valid.rs:178:13 + 2: Copy { + dest: StatePartIndex(66), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<2> }, + src: StatePartIndex(68), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 3: CastToUInt { + dest: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(66), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<2> }, + dest_width: 3, + }, + 4: Const { + dest: StatePartIndex(63), // (0x4) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x4, + }, + 5: CastToUInt { + dest: StatePartIndex(64), // (0x4) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(63), // (0x4) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 3, + }, + 6: Const { + dest: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 7: CastToUInt { + dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 2, + }, + 8: CastToUInt { + dest: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 3, + }, + 9: Const { + dest: StatePartIndex(54), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x3, + }, + 10: CmpEq { + dest: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(54), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + }, + 11: CmpEq { + dest: StatePartIndex(60), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(54), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + }, + 12: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 13: Add { + dest: StatePartIndex(58), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 14: CastToUInt { + dest: StatePartIndex(59), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(58), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 15: Add { + dest: StatePartIndex(61), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 16: CastToUInt { + dest: StatePartIndex(62), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(61), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 17: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 18: Copy { + dest: StatePartIndex(42), // (0x2c) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 19: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 20: Copy { + dest: StatePartIndex(15), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:114:5 + 21: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 22: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 23: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 24: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 25: Copy { + dest: StatePartIndex(11), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 26: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 27: CmpEq { + dest: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:104:5 + 28: Copy { + dest: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 29: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 30: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 31: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 32: And { + dest: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 33: Copy { + dest: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 34: NotU { + dest: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 35: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:124:9 + 36: BranchIfZero { + target: 38, + value: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:125:13 + 37: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 38: BranchIfZero { + target: 43, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 39: BranchIfZero { + target: 41, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 40: Copy { + dest: StatePartIndex(10), // (0x4) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<3> }, + src: StatePartIndex(64), // (0x4) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: ready_valid.rs:168:9 + 41: BranchIfNonZero { + target: 43, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 42: Copy { + dest: StatePartIndex(10), // (0x4) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<3> }, + src: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: ready_valid.rs:166:5 + 43: BranchIfNonZero { + target: 45, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:182:13 + 44: Copy { + dest: StatePartIndex(10), // (0x4) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<3> }, + src: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: ready_valid.rs:88:26 + 45: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 46: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 47: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:84:31 + 48: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 49: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 50: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 51: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 52: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + value: 0x0, + }, + // at: ready_valid.rs:91:19 + 53: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(15), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + }, + 54: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 55: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 56: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + }, + 57: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 58: BranchIfSmallZero { + target: 61, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 59: MemoryReadUInt { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 4>, + // data: [ + // // len = 0x4 + // [0x0]: 0x2c, + // [0x1]: 0x29, + // [0x2]: 0x2a, + // [0x3]: 0x2b, + // ], + // }) (), + addr: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 60: Branch { + target: 62, + }, + 61: Const { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 62: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 63: Copy { + dest: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 64: Shl { + dest: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 65: Or { + dest: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + }, + 66: CastToUInt { + dest: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 67: Copy { + dest: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 68: BranchIfZero { + target: 70, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 69: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 70: BranchIfNonZero { + target: 72, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:134:13 + 71: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(2), // (0x59) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 72: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 73: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 74: Copy { + dest: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 75: SliceInt { + dest: StatePartIndex(9), // (0x29) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 76: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 77: BranchIfSmallNeImmediate { + target: 79, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 78: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 79: BranchIfSmallNeImmediate { + target: 81, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 80: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 81: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 82: BranchIfZero { + target: 87, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 83: BranchIfZero { + target: 85, + value: StatePartIndex(60), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 84: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:158:9 + 85: BranchIfNonZero { + target: 87, + value: StatePartIndex(60), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 86: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(62), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 87: Copy { + dest: StatePartIndex(4), // (0x59) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x59) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 88: SliceInt { + dest: StatePartIndex(5), // (0x2c) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x59) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 89: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x59) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 90: BranchIfSmallNeImmediate { + target: 92, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 91: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 92: BranchIfSmallNeImmediate { + target: 94, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 93: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 94: Copy { + dest: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 95: Copy { + dest: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 96: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 97: CmpNe { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 98: BranchIfZero { + target: 100, + value: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 99: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 100: BranchIfZero { + target: 105, + value: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 101: BranchIfZero { + target: 103, + value: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 102: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:148:9 + 103: BranchIfNonZero { + target: 105, + value: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 104: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(59), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:118:30 + 105: BranchIfSmallNeImmediate { + target: 107, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 106: Copy { + dest: StatePartIndex(42), // (0x2c) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x2c) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 107: Copy { + dest: StatePartIndex(18), // (0x2c) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x2c) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 108: BranchIfSmallZero { + target: 113, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 109: BranchIfSmallNonZero { + target: 112, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 110: Copy { + dest: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + }, + 111: Branch { + target: 113, + }, + 112: Copy { + dest: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:86:25 + 113: BranchIfSmallZero { + target: 118, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 114: BranchIfSmallNonZero { + target: 117, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 115: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + }, + 116: Branch { + target: 118, + }, + 117: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 118: BranchIfSmallZero { + target: 123, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 119: BranchIfSmallNonZero { + target: 122, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 120: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 121: Branch { + target: 123, + }, + 122: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 123: BranchIfSmallZero { + target: 124, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 124: BranchIfSmallZero { + target: 132, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 125: CopySmall { + dest: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + }, + 126: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 127: Copy { + dest: StatePartIndex(20), // (0x2c) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x2c) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 128: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 129: BranchIfSmallZero { + target: 132, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 130: BranchIfZero { + target: 132, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 131: MemoryWriteUInt { + value: StatePartIndex(20), // (0x2c) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 4>, + // data: [ + // // len = 0x4 + // [0x0]: 0x2c, + // [0x1]: 0x29, + // [0x2]: 0x2a, + // [0x3]: 0x2b, + // ], + // }) (), + addr: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 132: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 133: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 134: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 135: Return, + ], + .. + }, + pc: 135, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 4>, + data: [ + // len = 0x4 + [0x0]: 0x2c, + [0x1]: 0x29, + [0x2]: 0x2a, + [0x3]: 0x2b, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 1, + 1, + 0, + 0, + 0, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 89, + 0, + 89, + 44, + 83, + 0, + 83, + 41, + 4, + 1, + 1, + 0, + 41, + 1, + 0, + 0, + 44, + 1, + 44, + 1, + 1, + 1, + 0, + 1, + 1, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 44, + 0, + 0, + 1, + 1, + 41, + 1, + 82, + 83, + 83, + 83, + 0, + 3, + 0, + 0, + 0, + 2, + 2, + 0, + 2, + 2, + 4, + 4, + 0, + 0, + 0, + 0, + 0, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<3>, + flow: Sink, + }, + ty: UInt<3>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 4, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 4>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + TraceWire { + name: "count_lower", + child: TraceUInt { + location: TraceScalarId(29), + name: "count_lower", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x2c, + last_state: 0x2c, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<3>, + }, + maybe_changed: true, + state: 0x4, + last_state: 0x4, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x2c, + last_state: 0x2c, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + maybe_changed: true, + state: 0x2c, + last_state: 0x2c, + }, + SimTrace { + id: TraceScalarId(29), + kind: BigUInt { + index: StatePartIndex(66), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x0, + last_state: 0x0, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 4, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 4>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_4_true_true.vcd b/crates/fayalite/tests/sim/expected/queue_4_true_true.vcd new file mode 100644 index 0000000..f4a2232 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_4_true_true.vcd @@ -0,0 +1,1989 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 3 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$scope struct \[1] $end +$var reg 8 5F$iE mem $end +$upscope $end +$scope struct \[2] $end +$var reg 8 !BEt5 mem $end +$upscope $end +$scope struct \[3] $end +$var reg 8 C7]kZ mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 2 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var wire 2 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var reg 2 Xk?#v inp_index_reg $end +$var reg 2 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~(47), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4", ty: Bool }, width: 1, }, - // at: module-XXXXXXXXXX.rs:8:1 - 3: Copy { - dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4$next", ty: Bool }, - src: StatePartIndex(52), // (0x1) SlotDebugData { name: "", ty: Bool }, - }, // at: module-XXXXXXXXXX.rs:7:1 - 4: Copy { + 3: Copy { dest: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[4]", ty: Bool }, src: StatePartIndex(47), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:1:1 - 5: Copy { + 4: Copy { dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Clock }, src: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[4]", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:10:1 - 6: Copy { + 5: Copy { dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_5.clk", ty: Clock }, src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Clock }, }, // at: module-XXXXXXXXXX.rs:9:1 - 7: Copy { + 6: Copy { dest: StatePartIndex(55), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_5: sw_reg).sw_reg::clk", ty: Clock }, src: StatePartIndex(53), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_5.clk", ty: Clock }, }, + // at: module-XXXXXXXXXX.rs:6:1 + 7: Copy { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4$next", ty: Bool }, + src: StatePartIndex(47), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:8:1 8: Copy { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4$next", ty: Bool }, + src: StatePartIndex(52), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:9:1 + 9: Copy { dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.o", ty: Bool }, src: StatePartIndex(45), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::o", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:11:1 - 9: Copy { + 10: Copy { dest: StatePartIndex(5), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[3]", ty: Bool }, src: StatePartIndex(43), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.o", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:1:1 - 10: Copy { + 11: Copy { dest: StatePartIndex(51), // (0x0) SlotDebugData { name: "", ty: Clock }, src: StatePartIndex(5), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[3]", ty: Bool }, }, - 11: NotU { + 12: NotU { dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2", ty: Bool }, width: 1, }, - // at: module-XXXXXXXXXX.rs:8:1 - 12: Copy { - dest: StatePartIndex(37), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2$next", ty: Bool }, - src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, - }, // at: module-XXXXXXXXXX.rs:7:1 13: Copy { dest: StatePartIndex(4), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[2]", ty: Bool }, @@ -383,241 +384,257 @@ Simulation { dest: StatePartIndex(44), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::clk", ty: Clock }, src: StatePartIndex(42), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.clk", ty: Clock }, }, + // at: module-XXXXXXXXXX.rs:6:1 17: Copy { + dest: StatePartIndex(37), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2$next", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:8:1 + 18: Copy { + dest: StatePartIndex(37), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2$next", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:9:1 + 19: Copy { dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.o", ty: Bool }, src: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::o", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:11:1 - 18: Copy { + 20: Copy { dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[1]", ty: Bool }, src: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.o", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:1:1 - 19: Copy { + 21: Copy { dest: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Clock }, src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[1]", ty: Bool }, }, - 20: NotU { + 22: NotU { dest: StatePartIndex(30), // (0x1) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(24), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0", ty: Bool }, width: 1, }, - // at: module-XXXXXXXXXX.rs:8:1 - 21: Copy { - dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0$next", ty: Bool }, - src: StatePartIndex(30), // (0x1) SlotDebugData { name: "", ty: Bool }, - }, // at: module-XXXXXXXXXX.rs:7:1 - 22: Copy { + 23: Copy { dest: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[0]", ty: Bool }, src: StatePartIndex(24), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:1:1 - 23: Copy { + 24: Copy { dest: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Clock }, src: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[0]", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:10:1 - 24: Copy { + 25: Copy { dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.clk", ty: Clock }, src: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Clock }, }, // at: module-XXXXXXXXXX.rs:9:1 - 25: Copy { + 26: Copy { dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::clk", ty: Clock }, src: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.clk", ty: Clock }, }, + // at: module-XXXXXXXXXX.rs:6:1 + 27: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0$next", ty: Bool }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:8:1 + 28: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0$next", ty: Bool }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, // at: module-XXXXXXXXXX.rs:1:1 - 26: Const { + 29: Const { dest: StatePartIndex(28), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, value: 0x0, }, - 27: Copy { + 30: Copy { dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: SyncReset }, src: StatePartIndex(28), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, - 28: Copy { + 31: Copy { dest: StatePartIndex(26), // (0x1) SlotDebugData { name: ".clk", ty: Clock }, src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::clk", ty: Clock }, }, - 29: Copy { + 32: Copy { dest: StatePartIndex(27), // (0x0) SlotDebugData { name: ".rst", ty: SyncReset }, src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: SyncReset }, }, // at: module-XXXXXXXXXX.rs:6:1 - 30: IsNonZeroDestIsSmall { + 33: IsNonZeroDestIsSmall { dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(26), // (0x1) SlotDebugData { name: ".clk", ty: Clock }, }, - 31: AndSmall { + 34: AndSmall { dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, rhs: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:1:1 - 32: Copy { + 35: Copy { dest: StatePartIndex(38), // (0x0) SlotDebugData { name: ".clk", ty: Clock }, src: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Clock }, }, - 33: Copy { + 36: Copy { dest: StatePartIndex(39), // (0x0) SlotDebugData { name: ".rst", ty: SyncReset }, src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: SyncReset }, }, // at: module-XXXXXXXXXX.rs:6:1 - 34: IsNonZeroDestIsSmall { + 37: IsNonZeroDestIsSmall { dest: StatePartIndex(5), // (0x0 0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(38), // (0x0) SlotDebugData { name: ".clk", ty: Clock }, }, - 35: AndSmall { + 38: AndSmall { dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(5), // (0x0 0) SlotDebugData { name: "", ty: Bool }, rhs: StatePartIndex(3), // (0x1 1) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:1:1 - 36: Copy { + 39: Copy { dest: StatePartIndex(49), // (0x0) SlotDebugData { name: ".clk", ty: Clock }, src: StatePartIndex(51), // (0x0) SlotDebugData { name: "", ty: Clock }, }, - 37: Copy { + 40: Copy { dest: StatePartIndex(50), // (0x0) SlotDebugData { name: ".rst", ty: SyncReset }, src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: SyncReset }, }, // at: module-XXXXXXXXXX.rs:6:1 - 38: IsNonZeroDestIsSmall { + 41: IsNonZeroDestIsSmall { dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(49), // (0x0) SlotDebugData { name: ".clk", ty: Clock }, }, - 39: AndSmall { + 42: AndSmall { dest: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, rhs: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:1:1 - 40: Copy { + 43: Copy { dest: StatePartIndex(21), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[5]", ty: Bool }, }, - 41: Shl { + 44: Shl { dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, lhs: StatePartIndex(21), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, rhs: 5, }, - 42: Copy { + 45: Copy { dest: StatePartIndex(18), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, src: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[4]", ty: Bool }, }, - 43: Shl { + 46: Shl { dest: StatePartIndex(19), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, lhs: StatePartIndex(18), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, rhs: 4, }, - 44: Copy { + 47: Copy { dest: StatePartIndex(15), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, src: StatePartIndex(5), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[3]", ty: Bool }, }, - 45: Shl { + 48: Shl { dest: StatePartIndex(16), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, lhs: StatePartIndex(15), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, rhs: 3, }, - 46: Copy { + 49: Copy { dest: StatePartIndex(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, src: StatePartIndex(4), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[2]", ty: Bool }, }, - 47: Shl { + 50: Shl { dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, lhs: StatePartIndex(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, rhs: 2, }, - 48: Copy { + 51: Copy { dest: StatePartIndex(9), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[1]", ty: Bool }, }, - 49: Shl { + 52: Shl { dest: StatePartIndex(10), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, lhs: StatePartIndex(9), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, rhs: 1, }, - 50: Copy { + 53: Copy { dest: StatePartIndex(8), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, src: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[0]", ty: Bool }, }, - 51: Or { + 54: Or { dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, lhs: StatePartIndex(8), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, rhs: StatePartIndex(10), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, }, - 52: Or { + 55: Or { dest: StatePartIndex(14), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, lhs: StatePartIndex(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, rhs: StatePartIndex(13), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, }, - 53: Or { + 56: Or { dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, lhs: StatePartIndex(14), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, rhs: StatePartIndex(16), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, }, - 54: Or { + 57: Or { dest: StatePartIndex(20), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, lhs: StatePartIndex(17), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, rhs: StatePartIndex(19), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, }, - 55: Or { + 58: Or { dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, lhs: StatePartIndex(20), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, rhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, }, // at: module-XXXXXXXXXX.rs:5:1 - 56: Copy { + 59: Copy { dest: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::o", ty: UInt<6> }, src: StatePartIndex(23), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, }, // at: module-XXXXXXXXXX.rs:6:1 - 57: BranchIfSmallZero { - target: 59, + 60: BranchIfSmallZero { + target: 62, value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 58: Copy { + 61: Copy { dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0", ty: Bool }, src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0$next", ty: Bool }, }, - 59: BranchIfSmallZero { - target: 61, + 62: BranchIfSmallZero { + target: 64, value: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 60: Copy { + 63: Copy { dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2", ty: Bool }, src: StatePartIndex(37), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2$next", ty: Bool }, }, - 61: BranchIfSmallZero { - target: 63, + 64: BranchIfSmallZero { + target: 66, value: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 62: Copy { + 65: Copy { dest: StatePartIndex(47), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4", ty: Bool }, src: StatePartIndex(48), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4$next", ty: Bool }, }, - 63: XorSmallImmediate { + 66: XorSmallImmediate { dest: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, rhs: 0x1, }, - 64: XorSmallImmediate { + 67: XorSmallImmediate { dest: StatePartIndex(3), // (0x1 1) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(5), // (0x0 0) SlotDebugData { name: "", ty: Bool }, rhs: 0x1, }, - 65: XorSmallImmediate { + 68: XorSmallImmediate { dest: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, rhs: 0x1, }, // at: module-XXXXXXXXXX.rs:1:1 - 66: Return, + 69: Return, ], .. }, - pc: 66, + pc: 69, memory_write_log: [], memories: StatePart { value: [], @@ -670,18 +687,7 @@ Simulation { 1, 0, 0, - 0, - 0, - 0, - 0, - 1, - 0, - 0, - 0, - 1, - 0, - 0, - 0, + 0 (modified), 0, 0, 0, @@ -692,9 +698,20 @@ Simulation { 1, 0, 0, + 0 (modified), 0, 0, 0, + 1, + 0, + 0, + 0, + 1, + 0, + 0, + 0 (modified), + 0, + 0, ], }, sim_only_slots: StatePart { @@ -1267,6 +1284,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: false, state: 0x1, last_state: 0x1, }, @@ -1276,6 +1294,7 @@ Simulation { index: StatePartIndex(1), ty: UInt<6>, }, + maybe_changed: false, state: 0x00, last_state: 0x00, }, @@ -1284,6 +1303,7 @@ Simulation { kind: BigBool { index: StatePartIndex(2), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1292,6 +1312,7 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1300,6 +1321,7 @@ Simulation { kind: BigBool { index: StatePartIndex(4), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1308,6 +1330,7 @@ Simulation { kind: BigBool { index: StatePartIndex(5), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1316,6 +1339,7 @@ Simulation { kind: BigBool { index: StatePartIndex(6), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1324,6 +1348,7 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1332,6 +1357,7 @@ Simulation { kind: BigBool { index: StatePartIndex(24), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1340,6 +1366,7 @@ Simulation { kind: BigClock { index: StatePartIndex(33), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1348,6 +1375,7 @@ Simulation { kind: BigBool { index: StatePartIndex(34), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1356,6 +1384,7 @@ Simulation { kind: BigClock { index: StatePartIndex(31), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1364,6 +1393,7 @@ Simulation { kind: BigBool { index: StatePartIndex(32), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1372,6 +1402,7 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1380,6 +1411,7 @@ Simulation { kind: BigClock { index: StatePartIndex(44), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1388,6 +1420,7 @@ Simulation { kind: BigBool { index: StatePartIndex(45), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1396,6 +1429,7 @@ Simulation { kind: BigClock { index: StatePartIndex(42), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1404,6 +1438,7 @@ Simulation { kind: BigBool { index: StatePartIndex(43), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1412,6 +1447,7 @@ Simulation { kind: BigBool { index: StatePartIndex(47), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1420,6 +1456,7 @@ Simulation { kind: BigClock { index: StatePartIndex(55), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1428,6 +1465,7 @@ Simulation { kind: BigBool { index: StatePartIndex(56), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1436,6 +1474,7 @@ Simulation { kind: BigClock { index: StatePartIndex(53), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1444,6 +1483,7 @@ Simulation { kind: BigBool { index: StatePartIndex(54), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, diff --git a/crates/fayalite/tests/sim/expected/ripple_counter.vcd b/crates/fayalite/tests/sim/expected/ripple_counter.vcd index 550205f..b800282 100644 --- a/crates/fayalite/tests/sim/expected/ripple_counter.vcd +++ b/crates/fayalite/tests/sim/expected/ripple_counter.vcd @@ -1,1713 +1,1443 @@ $timescale 1 ps $end $scope module ripple_counter $end -$var wire 1 ! clk $end -$var wire 6 " o $end +$var wire 1 IR0qP clk $end +$var wire 6 f0Cen o $end $scope struct bits $end -$var wire 1 # \[0] $end -$var wire 1 $ \[1] $end -$var wire 1 % \[2] $end -$var wire 1 & \[3] $end -$var wire 1 ' \[4] $end -$var wire 1 ( \[5] $end +$var wire 1 -$(J- \[0] $end +$var wire 1 (3), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::q", ty: Bool }, src: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool }, }, - // at: module-XXXXXXXXXX.rs:12:1 + // at: module-XXXXXXXXXX.rs:11:1 1: Copy { + dest: StatePartIndex(12), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool }, + src: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:12:1 + 2: Copy { dest: StatePartIndex(12), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool }, src: StatePartIndex(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool }, }, + // at: module-XXXXXXXXXX.rs:9:1 + 3: Copy { + dest: StatePartIndex(10), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool }, + src: StatePartIndex(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool }, + }, // at: module-XXXXXXXXXX.rs:10:1 - 2: Copy { + 4: Copy { dest: StatePartIndex(10), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool }, src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool }, }, + // at: module-XXXXXXXXXX.rs:7:1 + 5: Copy { + dest: StatePartIndex(8), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool }, + }, // at: module-XXXXXXXXXX.rs:8:1 - 3: Copy { + 6: Copy { dest: StatePartIndex(8), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool }, src: StatePartIndex(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool }, }, - // at: module-XXXXXXXXXX.rs:6:1 - 4: Copy { - dest: StatePartIndex(5), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool }, - src: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::d", ty: Bool }, - }, // at: module-XXXXXXXXXX.rs:5:1 - 5: IsNonZeroDestIsSmall { + 7: IsNonZeroDestIsSmall { dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst", ty: SyncReset }, }, - 6: IsNonZeroDestIsSmall { + 8: IsNonZeroDestIsSmall { dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk", ty: Clock }, }, - 7: AndSmall { + 9: AndSmall { dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, rhs: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, + 10: Copy { + dest: StatePartIndex(5), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool }, + src: StatePartIndex(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:6:1 + 11: Copy { + dest: StatePartIndex(5), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool }, + src: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::d", ty: Bool }, + }, // at: module-XXXXXXXXXX.rs:1:1 - 8: Const { + 12: Const { dest: StatePartIndex(6), // (0x0) SlotDebugData { name: "", ty: Bool }, value: 0x0, }, // at: module-XXXXXXXXXX.rs:5:1 - 9: BranchIfSmallZero { - target: 14, + 13: BranchIfSmallZero { + target: 18, value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 10: BranchIfSmallNonZero { - target: 13, + 14: BranchIfSmallNonZero { + target: 17, value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 11: Copy { + 15: Copy { dest: StatePartIndex(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool }, src: StatePartIndex(5), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool }, }, - 12: Branch { - target: 14, + 16: Branch { + target: 18, }, - 13: Copy { + 17: Copy { dest: StatePartIndex(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool }, src: StatePartIndex(6), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:7:1 - 14: BranchIfSmallZero { - target: 19, + 18: BranchIfSmallZero { + target: 23, value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 15: BranchIfSmallNonZero { - target: 18, + 19: BranchIfSmallNonZero { + target: 22, value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 16: Copy { + 20: Copy { dest: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool }, src: StatePartIndex(8), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool }, }, - 17: Branch { - target: 19, + 21: Branch { + target: 23, }, - 18: Copy { + 22: Copy { dest: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool }, src: StatePartIndex(6), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:9:1 - 19: BranchIfSmallZero { - target: 24, + 23: BranchIfSmallZero { + target: 28, value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 20: BranchIfSmallNonZero { - target: 23, + 24: BranchIfSmallNonZero { + target: 27, value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 21: Copy { + 25: Copy { dest: StatePartIndex(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool }, src: StatePartIndex(10), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool }, }, - 22: Branch { - target: 24, + 26: Branch { + target: 28, }, - 23: Copy { + 27: Copy { dest: StatePartIndex(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool }, src: StatePartIndex(6), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:11:1 - 24: BranchIfSmallZero { - target: 29, + 28: BranchIfSmallZero { + target: 33, value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 25: BranchIfSmallNonZero { - target: 28, + 29: BranchIfSmallNonZero { + target: 32, value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 26: Copy { + 30: Copy { dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool }, src: StatePartIndex(12), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool }, }, - 27: Branch { - target: 29, + 31: Branch { + target: 33, }, - 28: Copy { + 32: Copy { dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool }, src: StatePartIndex(6), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:5:1 - 29: XorSmallImmediate { + 33: XorSmallImmediate { dest: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, rhs: 0x1, }, // at: module-XXXXXXXXXX.rs:1:1 - 30: Return, + 34: Return, ], .. }, - pc: 30, + pc: 34, memory_write_log: [], memories: StatePart { value: [], @@ -439,6 +458,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x1, last_state: 0x0, }, @@ -447,6 +467,7 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -455,6 +476,7 @@ Simulation { kind: BigBool { index: StatePartIndex(2), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -463,6 +485,7 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -471,6 +494,7 @@ Simulation { kind: BigBool { index: StatePartIndex(4), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -479,6 +503,7 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -487,6 +512,7 @@ Simulation { kind: BigBool { index: StatePartIndex(9), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -495,6 +521,7 @@ Simulation { kind: BigBool { index: StatePartIndex(11), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, diff --git a/crates/fayalite/tests/sim/expected/shift_register.vcd b/crates/fayalite/tests/sim/expected/shift_register.vcd index 26726eb..e717ec8 100644 --- a/crates/fayalite/tests/sim/expected/shift_register.vcd +++ b/crates/fayalite/tests/sim/expected/shift_register.vcd @@ -1,193 +1,193 @@ $timescale 1 ps $end $scope module shift_register $end $scope struct cd $end -$var wire 1 ! clk $end -$var wire 1 " rst $end +$var wire 1 (0), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -364,6 +365,7 @@ Simulation { kind: BigClock { index: StatePartIndex(1), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -372,6 +374,7 @@ Simulation { kind: BigClock { index: StatePartIndex(2), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -381,6 +384,7 @@ Simulation { index: StatePartIndex(3), ty: UInt<8>, }, + maybe_changed: false, state: 0x31, last_state: 0x31, }, @@ -390,6 +394,7 @@ Simulation { index: StatePartIndex(4), ty: UInt<8>, }, + maybe_changed: false, state: 0x32, last_state: 0x32, }, @@ -399,6 +404,7 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, + maybe_changed: false, state: 0x32, last_state: 0x32, }, diff --git a/crates/fayalite/tests/sim/expected/sim_fork_join.vcd b/crates/fayalite/tests/sim/expected/sim_fork_join.vcd index a420c2b..37f434a 100644 --- a/crates/fayalite/tests/sim/expected/sim_fork_join.vcd +++ b/crates/fayalite/tests/sim/expected/sim_fork_join.vcd @@ -1,1467 +1,1467 @@ $timescale 1 ps $end $scope module sim_fork_join $end $scope struct clocks $end -$var wire 1 ! \[0] $end -$var wire 1 " \[1] $end -$var wire 1 # \[2] $end +$var wire 1 Xz8w) \[0] $end +$var wire 1 GIFRf \[1] $end +$var wire 1 OJ`bb \[2] $end $upscope $end $scope struct outputs $end -$var wire 8 $ \[0] $end -$var wire 8 % \[1] $end -$var wire 8 & \[2] $end +$var wire 8 G!R[n \[0] $end +$var wire 8 (H=Za \[1] $end +$var wire 8 Q7>," \[2] $end $upscope $end $upscope $end $enddefinitions $end $dumpvars -0! -0" -0# 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+b110001 G!R[n #632000000 -0! +0Xz8w) #633000000 -1# -b110010 & +1OJ`bb +b110010 Q7>," #634000000 -0# +0OJ`bb #635000000 -1# +1OJ`bb #636000000 -0# +0OJ`bb #637000000 -1# +1OJ`bb #638000000 -0# +0OJ`bb #639000000 -1" -b110010 % +1GIFRf +b110010 (H=Za #640000000 -0" +0GIFRf #641000000 -1# +1OJ`bb #642000000 -0# +0OJ`bb #643000000 -1# +1OJ`bb #644000000 -0# +0OJ`bb #645000000 -1# +1OJ`bb #646000000 -0# +0OJ`bb #647000000 -1# +1OJ`bb #648000000 -0# +0OJ`bb diff --git a/crates/fayalite/tests/sim/expected/sim_fork_join_scope.txt b/crates/fayalite/tests/sim/expected/sim_fork_join_scope.txt index 917dd5d..ae88960 100644 --- a/crates/fayalite/tests/sim/expected/sim_fork_join_scope.txt +++ b/crates/fayalite/tests/sim/expected/sim_fork_join_scope.txt @@ -68,12 +68,12 @@ Simulation { }, big_slots: StatePart { value: [ + 0 (modified), 0, 0, - 0, - 49, - 50, - 50, + 49 (modified), + 50 (modified), + 50 (modified), ], }, sim_only_slots: StatePart { @@ -356,6 +356,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -364,6 +365,7 @@ Simulation { kind: BigClock { index: StatePartIndex(1), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -372,6 +374,7 @@ Simulation { kind: BigClock { index: StatePartIndex(2), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -381,6 +384,7 @@ Simulation { index: StatePartIndex(3), ty: UInt<8>, }, + maybe_changed: false, state: 0x31, last_state: 0x31, }, @@ -390,6 +394,7 @@ Simulation { index: StatePartIndex(4), ty: UInt<8>, }, + maybe_changed: false, state: 0x32, last_state: 0x32, }, @@ -399,6 +404,7 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, + maybe_changed: false, state: 0x32, last_state: 0x32, }, diff --git a/crates/fayalite/tests/sim/expected/sim_fork_join_scope.vcd b/crates/fayalite/tests/sim/expected/sim_fork_join_scope.vcd index 555e83e..cb7bac4 100644 --- a/crates/fayalite/tests/sim/expected/sim_fork_join_scope.vcd +++ b/crates/fayalite/tests/sim/expected/sim_fork_join_scope.vcd @@ -1,1467 +1,1467 @@ $timescale 1 ps $end $scope module sim_fork_join_scope $end $scope struct clocks $end -$var wire 1 ! \[0] $end -$var wire 1 " \[1] $end -$var wire 1 # \[2] $end +$var wire 1 `,lzL \[0] $end +$var wire 1 SA$wv \[1] $end +$var wire 1 (9), // (0x0) SlotDebugData { name: "", ty: Bool }, value: 0x0, }, - // at: module-XXXXXXXXXX.rs:17:1 - 7: Copy { - dest: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty$next", ty: Bool }, - src: StatePartIndex(9), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:16:1 - 8: CloneSimOnly { - dest: StatePartIndex(9), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1$next", ty: SimOnly>> }, - src: StatePartIndex(0), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::inp", ty: SimOnly>> }, - }, // at: module-XXXXXXXXXX.rs:12:1 - 9: CloneSimOnly { + 7: CloneSimOnly { dest: StatePartIndex(1), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::out1", ty: SimOnly>> }, src: StatePartIndex(8), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1", ty: SimOnly>> }, }, // at: module-XXXXXXXXXX.rs:13:1 - 10: BranchIfZero { - target: 12, + 8: BranchIfZero { + target: 10, value: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:15:1 - 11: CloneSimOnly { + 9: CloneSimOnly { dest: StatePartIndex(1), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::out1", ty: SimOnly>> }, src: StatePartIndex(0), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::inp", ty: SimOnly>> }, }, // at: module-XXXXXXXXXX.rs:11:1 - 12: CloneSimOnly { + 10: CloneSimOnly { dest: StatePartIndex(4), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.inp", ty: SimOnly>> }, src: StatePartIndex(8), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1", ty: SimOnly>> }, }, // at: module-XXXXXXXXXX.rs:13:1 - 13: BranchIfZero { - target: 15, + 11: BranchIfZero { + target: 13, value: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:14:1 - 14: CloneSimOnly { + 12: CloneSimOnly { dest: StatePartIndex(4), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.inp", ty: SimOnly>> }, src: StatePartIndex(0), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::inp", ty: SimOnly>> }, }, // at: module-XXXXXXXXXX.rs:10:1 - 15: Copy { + 13: Copy { dest: StatePartIndex(2), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.cd.clk", ty: Clock }, src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::cd.clk", ty: Clock }, }, - 16: Copy { + 14: Copy { dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.cd.rst", ty: SyncReset }, src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::cd.rst", ty: SyncReset }, }, + // at: module-XXXXXXXXXX.rs:9:1 + 15: Copy { + dest: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty$next", ty: Bool }, + src: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:17:1 + 16: Copy { + dest: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty$next", ty: Bool }, + src: StatePartIndex(9), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, // at: module-XXXXXXXXXX.rs:1:1 17: Const { dest: StatePartIndex(8), // (0x1) SlotDebugData { name: "", ty: Bool }, @@ -280,91 +280,100 @@ Simulation { lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, rhs: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - // at: module-XXXXXXXXXX.rs:7:1 21: CloneSimOnly { + dest: StatePartIndex(9), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1$next", ty: SimOnly>> }, + src: StatePartIndex(8), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1", ty: SimOnly>> }, + }, + // at: module-XXXXXXXXXX.rs:16:1 + 22: CloneSimOnly { + dest: StatePartIndex(9), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1$next", ty: SimOnly>> }, + src: StatePartIndex(0), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::inp", ty: SimOnly>> }, + }, + // at: module-XXXXXXXXXX.rs:7:1 + 23: CloneSimOnly { dest: StatePartIndex(5), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.out", ty: SimOnly>> }, src: StatePartIndex(7), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects.helper1: sim_only_connects_helper).sim_only_connects_helper::out", ty: SimOnly>> }, }, // at: module-XXXXXXXXXX.rs:18:1 - 22: CloneSimOnly { + 24: CloneSimOnly { dest: StatePartIndex(2), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::out2", ty: SimOnly>> }, src: StatePartIndex(5), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.out", ty: SimOnly>> }, }, // at: module-XXXXXXXXXX.rs:21:1 - 23: CloneSimOnly { + 25: CloneSimOnly { dest: StatePartIndex(11), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper2.inp", ty: SimOnly>> }, src: StatePartIndex(2), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::out2", ty: SimOnly>> }, }, // at: module-XXXXXXXXXX.rs:19:1 - 24: CloneSimOnly { + 26: CloneSimOnly { dest: StatePartIndex(13), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects.helper2: sim_only_connects_helper).sim_only_connects_helper::inp", ty: SimOnly>> }, src: StatePartIndex(11), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper2.inp", ty: SimOnly>> }, }, // at: module-XXXXXXXXXX.rs:7:1 - 25: CloneSimOnly { + 27: CloneSimOnly { dest: StatePartIndex(6), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects.helper1: sim_only_connects_helper).sim_only_connects_helper::inp", ty: SimOnly>> }, src: StatePartIndex(4), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.inp", ty: SimOnly>> }, }, - 26: Copy { + 28: Copy { dest: StatePartIndex(4), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_only_connects.helper1: sim_only_connects_helper).sim_only_connects_helper::cd.clk", ty: Clock }, src: StatePartIndex(2), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.cd.clk", ty: Clock }, }, - 27: Copy { + 29: Copy { dest: StatePartIndex(5), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects.helper1: sim_only_connects_helper).sim_only_connects_helper::cd.rst", ty: SyncReset }, src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.cd.rst", ty: SyncReset }, }, // at: module-XXXXXXXXXX.rs:8:1 - 28: BranchIfSmallZero { - target: 33, + 30: BranchIfSmallZero { + target: 35, value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 29: BranchIfSmallNonZero { - target: 32, + 31: BranchIfSmallNonZero { + target: 34, value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 30: CloneSimOnly { + 32: CloneSimOnly { dest: StatePartIndex(8), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1", ty: SimOnly>> }, src: StatePartIndex(9), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1$next", ty: SimOnly>> }, }, - 31: Branch { - target: 33, + 33: Branch { + target: 35, }, - 32: CloneSimOnly { + 34: CloneSimOnly { dest: StatePartIndex(8), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1", ty: SimOnly>> }, src: StatePartIndex(10), // ({}) SlotDebugData { name: "", ty: SimOnly>> }, }, // at: module-XXXXXXXXXX.rs:9:1 - 33: BranchIfSmallZero { - target: 38, + 35: BranchIfSmallZero { + target: 40, value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 34: BranchIfSmallNonZero { - target: 37, + 36: BranchIfSmallNonZero { + target: 39, value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 35: Copy { + 37: Copy { dest: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty", ty: Bool }, src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty$next", ty: Bool }, }, - 36: Branch { - target: 38, + 38: Branch { + target: 40, }, - 37: Copy { + 39: Copy { dest: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty", ty: Bool }, src: StatePartIndex(8), // (0x1) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:8:1 - 38: XorSmallImmediate { + 40: XorSmallImmediate { dest: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, rhs: 0x1, }, // at: module-XXXXXXXXXX.rs:1:1 - 39: Return, + 41: Return, ], .. }, - pc: 39, + pc: 41, memory_write_log: [], memories: StatePart { value: [], @@ -383,7 +392,7 @@ Simulation { 0, 1, 0, - 1, + 1 (modified), 0, 0, 0, @@ -391,7 +400,7 @@ Simulation { 0, 1, 0, - 1, + 1 (modified), 0, ], }, @@ -1243,6 +1252,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1251,6 +1261,7 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1260,6 +1271,7 @@ Simulation { index: StatePartIndex(0), ty: SimOnly>>, }, + maybe_changed: true, state: { "extra": "value", }, @@ -1273,6 +1285,7 @@ Simulation { index: StatePartIndex(1), ty: SimOnly>>, }, + maybe_changed: true, state: { "extra": "value", }, @@ -1286,6 +1299,7 @@ Simulation { index: StatePartIndex(2), ty: SimOnly>>, }, + maybe_changed: true, state: { "bar": "", "extra": "value", @@ -1303,6 +1317,7 @@ Simulation { index: StatePartIndex(3), ty: SimOnly>>, }, + maybe_changed: true, state: { "bar": "baz", "extra": "value", @@ -1319,6 +1334,7 @@ Simulation { kind: BigClock { index: StatePartIndex(4), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1327,6 +1343,7 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(5), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1336,6 +1353,7 @@ Simulation { index: StatePartIndex(6), ty: SimOnly>>, }, + maybe_changed: true, state: { "extra": "value", }, @@ -1349,6 +1367,7 @@ Simulation { index: StatePartIndex(7), ty: SimOnly>>, }, + maybe_changed: true, state: { "bar": "", "extra": "value", @@ -1365,6 +1384,7 @@ Simulation { kind: BigClock { index: StatePartIndex(2), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1373,6 +1393,7 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(3), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1382,6 +1403,7 @@ Simulation { index: StatePartIndex(4), ty: SimOnly>>, }, + maybe_changed: true, state: { "extra": "value", }, @@ -1395,6 +1417,7 @@ Simulation { index: StatePartIndex(5), ty: SimOnly>>, }, + maybe_changed: true, state: { "bar": "", "extra": "value", @@ -1412,6 +1435,7 @@ Simulation { index: StatePartIndex(8), ty: SimOnly>>, }, + maybe_changed: true, state: { "extra": "value", }, @@ -1424,6 +1448,7 @@ Simulation { kind: BigBool { index: StatePartIndex(6), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1432,6 +1457,7 @@ Simulation { kind: BigClock { index: StatePartIndex(12), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1440,6 +1466,7 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(13), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1449,6 +1476,7 @@ Simulation { index: StatePartIndex(13), ty: SimOnly>>, }, + maybe_changed: true, state: { "bar": "", "extra": "value", @@ -1466,6 +1494,7 @@ Simulation { index: StatePartIndex(14), ty: SimOnly>>, }, + maybe_changed: true, state: { "bar": "baz", "extra": "value", @@ -1482,6 +1511,7 @@ Simulation { kind: BigClock { index: StatePartIndex(10), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1490,6 +1520,7 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(11), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1499,6 +1530,7 @@ Simulation { index: StatePartIndex(11), ty: SimOnly>>, }, + maybe_changed: true, state: { "bar": "", "extra": "value", @@ -1516,6 +1548,7 @@ Simulation { index: StatePartIndex(12), ty: SimOnly>>, }, + maybe_changed: true, state: { "bar": "baz", "extra": "value", diff --git a/crates/fayalite/tests/sim/expected/sim_only_connects.vcd b/crates/fayalite/tests/sim/expected/sim_only_connects.vcd index 1e4c249..db62091 100644 --- a/crates/fayalite/tests/sim/expected/sim_only_connects.vcd +++ b/crates/fayalite/tests/sim/expected/sim_only_connects.vcd @@ -1,182 +1,122 @@ $timescale 1 ps $end $scope module sim_only_connects $end $scope struct cd $end -$var wire 1 ! clk $end -$var wire 1 " rst $end +$var wire 1 tq:(w clk $end +$var wire 1 FVlgb rst $end $upscope $end -$var string 1 # inp $end -$var string 1 $ out1 $end -$var string 1 % out2 $end -$var string 1 & out3 $end -$scope struct helper1 $end +$var string 1 g:xf? inp $end +$var string 1 [OKKg out1 $end +$var string 1 9pB-> out2 $end +$var string 1 8(7-4 out3 $end +$scope module helper1 $end $scope struct cd $end -$var wire 1 + clk $end -$var wire 1 , rst $end +$var wire 1 $Kwp\ clk $end +$var wire 1 nmVq' rst $end $upscope $end -$var string 1 - inp $end -$var string 1 . out $end +$var string 1 qS)@z inp $end +$var string 1 ~je// out $end $upscope $end -$scope module sim_only_connects_helper $end +$var string 1 CyjVm delay1 $end +$var reg 1 z~g{\ delay1_empty $end +$scope module helper2 $end $scope struct cd $end -$var wire 1 ' clk $end -$var wire 1 ( rst $end +$var wire 1 Ph.=# clk $end +$var wire 1 !GXK\ rst $end $upscope $end -$var string 1 ) inp $end -$var string 1 * out $end -$upscope $end -$var string 1 / delay1 $end -$var reg 1 0 delay1_empty $end -$scope struct helper2 $end -$scope struct cd $end -$var wire 1 5 clk $end -$var wire 1 6 rst $end -$upscope $end -$var string 1 7 inp $end -$var string 1 8 out $end -$upscope $end -$scope module sim_only_connects_helper_2 $end -$scope struct cd $end -$var wire 1 1 clk $end -$var wire 1 2 rst $end -$upscope $end -$var string 1 3 inp $end -$var string 1 4 out $end +$var string 1 /YVv: inp $end +$var string 1 Kk*{# out $end $upscope $end $upscope $end $enddefinitions $end $dumpvars -0! -1" -s{\"extra\":\x20\"value\"} # -s{} $ -s{} % -s{} & -0' -1( -s{} ) -s{} * -0+ -1, -s{} - -s{} . -s{} / -00 -01 -12 -s{} 3 -s{} 4 -05 -16 -s{} 7 -s{} 8 +0tq:(w +1FVlgb +s{\"extra\":\x20\"value\"} g:xf? +s{} [OKKg +s{} 9pB-> +s{} 8(7-4 +0$Kwp\ +1nmVq' +s{} qS)@z +s{} ~je// +s{} CyjVm +0z~g{\ +0Ph.=# +1!GXK\ +s{} /YVv: +s{} Kk*{# $end #1000000 -1! -s{\"extra\":\x20\"value\"} $ -1' -s{\"extra\":\x20\"value\"} ) -1+ -s{\"extra\":\x20\"value\"} - -10 -11 -15 -s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} % -s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} * -s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} . -s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 3 -s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 7 -s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} & -s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 4 -s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 8 +1tq:(w +s{\"extra\":\x20\"value\"} [OKKg +1$Kwp\ +s{\"extra\":\x20\"value\"} qS)@z +1z~g{\ +1Ph.=# +s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 9pB-> +s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} ~je// +s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} /YVv: +s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 8(7-4 +s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} Kk*{# #2000000 -0! -0" -0' -0( -0+ -0, -01 -02 -05 -06 +0tq:(w +0FVlgb +0$Kwp\ +0nmVq' +0Ph.=# +0!GXK\ #3000000 -1! -1' -1+ -s{\"extra\":\x20\"value\"} / -00 -11 -15 +1tq:(w +1$Kwp\ +s{\"extra\":\x20\"value\"} CyjVm +0z~g{\ +1Ph.=# #4000000 -0! -0' -0+ -01 -05 +0tq:(w +0$Kwp\ +0Ph.=# #5000000 -1! -1' -1+ -11 -15 +1tq:(w +1$Kwp\ +1Ph.=# #6000000 -0! -0' -0+ -01 -05 +0tq:(w +0$Kwp\ +0Ph.=# #7000000 -1! -1' -1+ -11 -15 +1tq:(w +1$Kwp\ +1Ph.=# #8000000 -0! -0' -0+ -01 -05 +0tq:(w +0$Kwp\ +0Ph.=# #9000000 -1! -1' -1+ -11 -15 +1tq:(w +1$Kwp\ +1Ph.=# #10000000 -0! -0' -0+ -01 -05 +0tq:(w +0$Kwp\ +0Ph.=# #11000000 -1! -1' -1+ -11 -15 +1tq:(w +1$Kwp\ +1Ph.=# #12000000 -0! -0' -0+ -01 -05 +0tq:(w +0$Kwp\ +0Ph.=# #13000000 -1! -1' -1+ -11 -15 +1tq:(w +1$Kwp\ +1Ph.=# #14000000 -0! -0' -0+ -01 -05 +0tq:(w +0$Kwp\ +0Ph.=# #15000000 -1! -1' -1+ -11 -15 +1tq:(w +1$Kwp\ +1Ph.=# #16000000 diff --git a/crates/fayalite/tests/sim/expected/sim_read_past.txt b/crates/fayalite/tests/sim/expected/sim_read_past.txt index 6df4571..f771434 100644 --- a/crates/fayalite/tests/sim/expected/sim_read_past.txt +++ b/crates/fayalite/tests/sim/expected/sim_read_past.txt @@ -530,18 +530,18 @@ Simulation { }, big_slots: StatePart { value: [ + 0 (modified), 0, 0, - 0, - 49, - 50, - 50, - 0, - 1, - 0, - 49, - 49, - 50, + 49 (modified), + 50 (modified), + 50 (modified), + 0 (modified), + 1 (modified), + 0 (modified), + 49 (modified), + 49 (modified), + 50 (modified), 1, 0, 0, @@ -9500,6 +9500,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -9508,6 +9509,7 @@ Simulation { kind: BigClock { index: StatePartIndex(1), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -9516,6 +9518,7 @@ Simulation { kind: BigClock { index: StatePartIndex(2), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -9525,6 +9528,7 @@ Simulation { index: StatePartIndex(3), ty: UInt<8>, }, + maybe_changed: false, state: 0x31, last_state: 0x31, }, @@ -9534,6 +9538,7 @@ Simulation { index: StatePartIndex(4), ty: UInt<8>, }, + maybe_changed: false, state: 0x32, last_state: 0x32, }, @@ -9543,6 +9548,7 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, + maybe_changed: false, state: 0x32, last_state: 0x32, }, @@ -9551,6 +9557,7 @@ Simulation { kind: BigClock { index: StatePartIndex(6), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -9559,6 +9566,7 @@ Simulation { kind: BigClock { index: StatePartIndex(7), }, + maybe_changed: false, state: 0x1, last_state: 0x1, }, @@ -9567,6 +9575,7 @@ Simulation { kind: BigClock { index: StatePartIndex(8), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -9576,6 +9585,7 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, + maybe_changed: false, state: 0x31, last_state: 0x31, }, @@ -9585,6 +9595,7 @@ Simulation { index: StatePartIndex(10), ty: UInt<8>, }, + maybe_changed: false, state: 0x31, last_state: 0x31, }, @@ -9594,6 +9605,7 @@ Simulation { index: StatePartIndex(11), ty: UInt<8>, }, + maybe_changed: false, state: 0x32, last_state: 0x32, }, diff --git a/crates/fayalite/tests/sim/expected/sim_read_past.vcd b/crates/fayalite/tests/sim/expected/sim_read_past.vcd index 5d0a932..e98fc97 100644 --- a/crates/fayalite/tests/sim/expected/sim_read_past.vcd +++ b/crates/fayalite/tests/sim/expected/sim_read_past.vcd @@ -1,1908 +1,1908 @@ $timescale 1 ps $end $scope module sim_read_past $end $scope struct clocks $end -$var wire 1 ! \[0] $end -$var wire 1 " \[1] $end -$var wire 1 # \[2] $end +$var wire 1 zV+7l \[0] $end +$var wire 1 7&!(0), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -318,6 +319,7 @@ Simulation { kind: BigAsyncReset { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -327,6 +329,7 @@ Simulation { index: StatePartIndex(2), ty: UInt<8>, }, + maybe_changed: false, state: 0x03, last_state: 0x03, }, diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_async.vcd b/crates/fayalite/tests/sim/expected/sim_resettable_counter_async.vcd index f05658f..d16c2df 100644 --- a/crates/fayalite/tests/sim/expected/sim_resettable_counter_async.vcd +++ b/crates/fayalite/tests/sim/expected/sim_resettable_counter_async.vcd @@ -1,68 +1,68 @@ $timescale 1 ps $end $scope module sim_resettable_counter $end $scope struct cd $end -$var wire 1 ! clk $end -$var wire 1 " rst $end +$var wire 1 zGup) clk $end +$var wire 1 TfzI\ rst $end $upscope $end -$var wire 8 # out $end +$var wire 8 #$b%i out $end $upscope $end $enddefinitions $end $dumpvars -0! -0" -b0 # +0zGup) +0TfzI\ +b0 #$b%i $end #1000000 -1! -b1 # +1zGup) +b1 #$b%i #2000000 -0! -1" -b0 # +0zGup) +1TfzI\ +b0 #$b%i #3000000 -1! +1zGup) #4000000 -0! -0" +0zGup) +0TfzI\ #5000000 -1! -b1 # +1zGup) +b1 #$b%i #6000000 -0! +0zGup) #7000000 -1! -b10 # +1zGup) +b10 #$b%i #8000000 -0! +0zGup) #9000000 -1! -b11 # +1zGup) +b11 #$b%i #10000000 -0! +0zGup) #11000000 -1! -b100 # +1zGup) +b100 #$b%i #12000000 -0! -1" -b0 # +0zGup) +1TfzI\ +b0 #$b%i #13000000 -1! +1zGup) #14000000 -0! -0" +0zGup) +0TfzI\ #15000000 -1! -b1 # +1zGup) +b1 #$b%i #16000000 -0! +0zGup) #17000000 -1! -b10 # +1zGup) +b10 #$b%i #18000000 -0! +0zGup) #19000000 -1! -b11 # +1zGup) +b11 #$b%i #20000000 -0! +0zGup) diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.txt b/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.txt index 2283ce5..f03c25a 100644 --- a/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.txt +++ b/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.txt @@ -56,8 +56,8 @@ Simulation { }, big_slots: StatePart { value: [ - 0, - 0, + 0 (modified), + 0 (modified), 3, ], }, @@ -310,6 +310,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -318,6 +319,7 @@ Simulation { kind: BigAsyncReset { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -327,6 +329,7 @@ Simulation { index: StatePartIndex(2), ty: UInt<8>, }, + maybe_changed: false, state: 0x03, last_state: 0x03, }, diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.vcd b/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.vcd index 99f7b86..b7f79d2 100644 --- a/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.vcd +++ b/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.vcd @@ -1,65 +1,65 @@ $timescale 1 ps $end $scope module sim_resettable_counter $end $scope struct cd $end -$var wire 1 ! clk $end -$var wire 1 " rst $end +$var wire 1 zGup) clk $end +$var wire 1 TfzI\ rst $end $upscope $end -$var wire 8 # out $end +$var wire 8 #$b%i out $end $upscope $end $enddefinitions $end $dumpvars -0! -1" -b0 # +0zGup) +1TfzI\ +b0 #$b%i $end #1000000 -1! +1zGup) #2000000 -0! +0zGup) #3000000 -1! +1zGup) #4000000 -0! -0" +0zGup) +0TfzI\ #5000000 -1! -b1 # +1zGup) +b1 #$b%i #6000000 -0! +0zGup) #7000000 -1! -b10 # +1zGup) +b10 #$b%i #8000000 -0! +0zGup) #9000000 -1! -b11 # +1zGup) +b11 #$b%i #10000000 -0! +0zGup) #11000000 -1! -b100 # +1zGup) +b100 #$b%i #12000000 -0! -1" -b0 # +0zGup) +1TfzI\ +b0 #$b%i #13000000 -1! +1zGup) #14000000 -0! -0" +0zGup) +0TfzI\ #15000000 -1! -b1 # +1zGup) +b1 #$b%i #16000000 -0! +0zGup) #17000000 -1! -b10 # +1zGup) +b10 #$b%i #18000000 -0! +0zGup) #19000000 -1! -b11 # +1zGup) +b11 #$b%i #20000000 -0! +0zGup) diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.txt b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.txt index c77046f..c93d6c1 100644 --- a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.txt +++ b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.txt @@ -56,7 +56,7 @@ Simulation { }, big_slots: StatePart { value: [ - 0, + 0 (modified), 0, 3, ], @@ -310,6 +310,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -318,6 +319,7 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -327,6 +329,7 @@ Simulation { index: StatePartIndex(2), ty: UInt<8>, }, + maybe_changed: false, state: 0x03, last_state: 0x03, }, diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.vcd b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.vcd index 39c2641..48c11ce 100644 --- a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.vcd +++ b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.vcd @@ -1,70 +1,70 @@ $timescale 1 ps $end $scope module sim_resettable_counter $end $scope struct cd $end -$var wire 1 ! clk $end -$var wire 1 " rst $end +$var wire 1 zGup) clk $end +$var wire 1 TfzI\ rst $end $upscope $end -$var wire 8 # out $end +$var wire 8 #$b%i out $end $upscope $end $enddefinitions $end $dumpvars -0! -0" -b0 # +0zGup) +0TfzI\ +b0 #$b%i $end #1000000 -1! -b1 # +1zGup) +b1 #$b%i #2000000 -0! -1" +0zGup) +1TfzI\ #3000000 -1! -b10 # -b0 # +1zGup) +b10 #$b%i +b0 #$b%i #4000000 -0! -0" +0zGup) +0TfzI\ #5000000 -1! -b1 # +1zGup) +b1 #$b%i #6000000 -0! +0zGup) #7000000 -1! -b10 # +1zGup) +b10 #$b%i #8000000 -0! +0zGup) #9000000 -1! -b11 # +1zGup) +b11 #$b%i #10000000 -0! +0zGup) #11000000 -1! -b100 # +1zGup) +b100 #$b%i #12000000 -0! -1" +0zGup) +1TfzI\ #13000000 -1! -b101 # -b0 # +1zGup) +b101 #$b%i +b0 #$b%i #14000000 -0! -0" +0zGup) +0TfzI\ #15000000 -1! -b1 # +1zGup) +b1 #$b%i #16000000 -0! +0zGup) #17000000 -1! -b10 # +1zGup) +b10 #$b%i #18000000 -0! +0zGup) #19000000 -1! -b11 # +1zGup) +b11 #$b%i #20000000 -0! +0zGup) diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.txt b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.txt index e1c565a..f13af84 100644 --- a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.txt +++ b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.txt @@ -56,7 +56,7 @@ Simulation { }, big_slots: StatePart { value: [ - 0, + 0 (modified), 0, 3, ], @@ -310,6 +310,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -318,6 +319,7 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -327,6 +329,7 @@ Simulation { index: StatePartIndex(2), ty: UInt<8>, }, + maybe_changed: false, state: 0x03, last_state: 0x03, }, diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.vcd b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.vcd index 3cb97e2..7abe857 100644 --- a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.vcd +++ b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.vcd @@ -1,70 +1,70 @@ $timescale 1 ps $end $scope module sim_resettable_counter $end $scope struct cd $end -$var wire 1 ! clk $end -$var wire 1 " rst $end +$var wire 1 zGup) clk $end +$var wire 1 TfzI\ rst $end $upscope $end -$var wire 8 # out $end +$var wire 8 #$b%i out $end $upscope $end $enddefinitions $end $dumpvars -0! -1" -b0 # +0zGup) +1TfzI\ +b0 #$b%i $end #1000000 -1! -b1 # -b0 # +1zGup) +b1 #$b%i +b0 #$b%i #2000000 -0! +0zGup) #3000000 -1! -b1 # -b0 # +1zGup) +b1 #$b%i +b0 #$b%i #4000000 -0! -0" +0zGup) +0TfzI\ #5000000 -1! -b1 # +1zGup) +b1 #$b%i #6000000 -0! +0zGup) #7000000 -1! -b10 # +1zGup) +b10 #$b%i #8000000 -0! +0zGup) #9000000 -1! -b11 # +1zGup) +b11 #$b%i #10000000 -0! +0zGup) #11000000 -1! -b100 # +1zGup) +b100 #$b%i #12000000 -0! -1" +0zGup) +1TfzI\ #13000000 -1! -b101 # -b0 # +1zGup) +b101 #$b%i +b0 #$b%i #14000000 -0! -0" +0zGup) +0TfzI\ #15000000 -1! -b1 # +1zGup) +b1 #$b%i #16000000 -0! +0zGup) #17000000 -1! -b10 # +1zGup) +b10 #$b%i #18000000 -0! +0zGup) #19000000 -1! -b11 # +1zGup) +b11 #$b%i #20000000 -0! +0zGup) diff --git a/crates/fayalite/tests/sim/expected/sim_trace_as_string.txt b/crates/fayalite/tests/sim/expected/sim_trace_as_string.txt new file mode 100644 index 0000000..0dd374c --- /dev/null +++ b/crates/fayalite/tests/sim/expected/sim_trace_as_string.txt @@ -0,0 +1,2254 @@ +Simulation { + state: State { + insns: Insns { + state_layout: StateLayout { + ty: TypeLayout { + small_slots: StatePartLayout { + len: 12, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 31, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.addr", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.data[0]", + ty: Enum { + Text(UInt<512>), + FmtError, + }, + }, + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.data[1]", + ty: Enum { + Text(UInt<512>), + FmtError, + }, + }, + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.addr", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.data[0]", + ty: Enum { + Text(UInt<512>), + FmtError, + }, + }, + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.data[1]", + ty: Enum { + Text(UInt<512>), + FmtError, + }, + }, + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.mask[0]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.mask[1]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.data[0]", + ty: Enum { + Text(UInt<512>), + FmtError, + }, + }, + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.data[1]", + ty: Enum { + Text(UInt<512>), + FmtError, + }, + }, + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.data[0]", + ty: Enum { + Text(UInt<512>), + FmtError, + }, + }, + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.data[1]", + ty: Enum { + Text(UInt<512>), + FmtError, + }, + }, + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.mask[0]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.mask[1]", + ty: Bool, + }, + SlotDebugData { + name: "[0]", + ty: Enum { + Text(UInt<512>), + FmtError, + }, + }, + SlotDebugData { + name: "[1]", + ty: Enum { + Text(UInt<512>), + FmtError, + }, + }, + SlotDebugData { + name: "[0]", + ty: Bool, + }, + SlotDebugData { + name: "[1]", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array), FmtError}, .. }, 2>, 4>, + data: [ + // len = 0x4 + [0x0]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, + [0x1]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, + [0x2]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, + [0x3]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, + ], + }, + ], + .. + }, + }, + insns: [ + // at: module-XXXXXXXXXX.rs:16:1 + 0: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.mask[0]", ty: Bool }, + src: StatePartIndex(11), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.mask[0]", ty: Bool }, + }, + 1: Copy { + dest: StatePartIndex(24), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.mask[1]", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.mask[1]", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:15:1 + 2: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.en", ty: Bool }, + src: StatePartIndex(7), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.en", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:14:1 + 3: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.data[0]", ty: Enum {Text(UInt<512>), FmtError} }, + src: StatePartIndex(9), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.data[0]", ty: Enum {Text(UInt<512>), FmtError} }, + }, + 4: Copy { + dest: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.data[1]", ty: Enum {Text(UInt<512>), FmtError} }, + src: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.data[1]", ty: Enum {Text(UInt<512>), FmtError} }, + }, + // at: module-XXXXXXXXXX.rs:1:1 + 5: CastToUInt { + dest: StatePartIndex(30), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(6), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.addr", ty: UInt<8> }, + dest_width: 2, + }, + // at: module-XXXXXXXXXX.rs:13:1 + 6: Copy { + dest: StatePartIndex(18), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.addr", ty: UInt<2> }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: module-XXXXXXXXXX.rs:12:1 + 7: Copy { + dest: StatePartIndex(20), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::clk", ty: Clock }, + }, + // at: module-XXXXXXXXXX.rs:9:1 + 8: Copy { + dest: StatePartIndex(14), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.en", ty: Bool }, + src: StatePartIndex(2), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.en", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:1:1 + 9: CastToUInt { + dest: StatePartIndex(29), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(1), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.addr", ty: UInt<8> }, + dest_width: 2, + }, + // at: module-XXXXXXXXXX.rs:8:1 + 10: Copy { + dest: StatePartIndex(13), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.addr", ty: UInt<2> }, + src: StatePartIndex(29), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: module-XXXXXXXXXX.rs:7:1 + 11: Copy { + dest: StatePartIndex(15), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::clk", ty: Clock }, + }, + // at: module-XXXXXXXXXX.rs:5:1 + 12: CastBigToArrayIndex { + dest: StatePartIndex(9), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(18), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.addr", ty: UInt<2> }, + }, + 13: IsNonZeroDestIsSmall { + dest: StatePartIndex(8), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.en", ty: Bool }, + }, + 14: IsNonZeroDestIsSmall { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(20), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.clk", ty: Clock }, + }, + 15: AndSmall { + dest: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(5), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 16: CastBigToArrayIndex { + dest: StatePartIndex(4), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(13), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.addr", ty: UInt<2> }, + }, + 17: IsNonZeroDestIsSmall { + dest: StatePartIndex(3), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(14), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.en", ty: Bool }, + }, + 18: BranchIfSmallZero { + target: 22, + value: StatePartIndex(3), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 19: MemoryReadUInt { + dest: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.data[0]", ty: Enum {Text(UInt<512>), FmtError} }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array), FmtError}, .. }, 2>, 4>, + // data: [ + // // len = 0x4 + // [0x0]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74c16db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba60b6dacada, + // [0x1]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001, + // [0x2]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74c96db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba64b6dacada, + // [0x3]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74cd6db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba66b6dacada, + // ], + // }) (), + addr: StatePartIndex(4), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + stride: 1026, + start: 0, + width: 513, + }, + 20: MemoryReadUInt { + dest: StatePartIndex(17), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.data[1]", ty: Enum {Text(UInt<512>), FmtError} }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array), FmtError}, .. }, 2>, 4>, + // data: [ + // // len = 0x4 + // [0x0]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74c16db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba60b6dacada, + // [0x1]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001, + // [0x2]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74c96db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba64b6dacada, + // [0x3]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74cd6db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba66b6dacada, + // ], + // }) (), + addr: StatePartIndex(4), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + stride: 1026, + start: 513, + width: 513, + }, + 21: Branch { + target: 24, + }, + 22: Const { + dest: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.data[0]", ty: Enum {Text(UInt<512>), FmtError} }, + value: 0x0, + }, + 23: Const { + dest: StatePartIndex(17), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.data[1]", ty: Enum {Text(UInt<512>), FmtError} }, + value: 0x0, + }, + // at: module-XXXXXXXXXX.rs:10:1 + 24: Copy { + dest: StatePartIndex(4), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.data[0]", ty: Enum {Text(UInt<512>), FmtError} }, + src: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.data[0]", ty: Enum {Text(UInt<512>), FmtError} }, + }, + 25: Copy { + dest: StatePartIndex(5), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.data[1]", ty: Enum {Text(UInt<512>), FmtError} }, + src: StatePartIndex(17), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.data[1]", ty: Enum {Text(UInt<512>), FmtError} }, + }, + // at: module-XXXXXXXXXX.rs:5:1 + 26: IsNonZeroDestIsSmall { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(15), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.clk", ty: Clock }, + }, + 27: AndSmall { + dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 28: BranchIfSmallZero { + target: 29, + value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 29: BranchIfSmallZero { + target: 41, + value: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 30: CopySmall { + dest: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(9), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + }, + 31: CopySmall { + dest: StatePartIndex(11), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(8), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 32: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "[0]", ty: Enum {Text(UInt<512>), FmtError} }, + src: StatePartIndex(21), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.data[0]", ty: Enum {Text(UInt<512>), FmtError} }, + }, + 33: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "[1]", ty: Enum {Text(UInt<512>), FmtError} }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.data[1]", ty: Enum {Text(UInt<512>), FmtError} }, + }, + 34: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "[0]", ty: Bool }, + src: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.mask[0]", ty: Bool }, + }, + 35: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "[1]", ty: Bool }, + src: StatePartIndex(24), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.mask[1]", ty: Bool }, + }, + 36: BranchIfSmallZero { + target: 41, + value: StatePartIndex(11), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 37: BranchIfZero { + target: 39, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "[0]", ty: Bool }, + }, + 38: MemoryWriteUInt { + value: StatePartIndex(25), // (0x1) SlotDebugData { name: "[0]", ty: Enum {Text(UInt<512>), FmtError} }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array), FmtError}, .. }, 2>, 4>, + // data: [ + // // len = 0x4 + // [0x0]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74c16db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba60b6dacada, + // [0x1]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001, + // [0x2]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74c96db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba64b6dacada, + // [0x3]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74cd6db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba66b6dacada, + // ], + // }) (), + addr: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + stride: 1026, + start: 0, + width: 513, + }, + 39: BranchIfZero { + target: 41, + value: StatePartIndex(28), // (0x1) SlotDebugData { name: "[1]", ty: Bool }, + }, + 40: MemoryWriteUInt { + value: StatePartIndex(26), // (0x1) SlotDebugData { name: "[1]", ty: Enum {Text(UInt<512>), FmtError} }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array), FmtError}, .. }, 2>, 4>, + // data: [ + // // len = 0x4 + // [0x0]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74c16db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba60b6dacada, + // [0x1]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001, + // [0x2]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74c96db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba64b6dacada, + // [0x3]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74cd6db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba66b6dacada, + // ], + // }) (), + addr: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + stride: 1026, + start: 513, + width: 513, + }, + 41: XorSmallImmediate { + dest: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 42: XorSmallImmediate { + dest: StatePartIndex(5), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: module-XXXXXXXXXX.rs:1:1 + 43: Return, + ], + .. + }, + pc: 43, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array), FmtError}, .. }, 2>, 4>, + data: [ + // len = 0x4 + [0x0]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74c16db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba60b6dacada, + [0x1]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001, + [0x2]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74c96db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba64b6dacada, + [0x3]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74cd6db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba66b6dacada, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 0, + 0, + 1, + 1, + 1, + 0, + 0, + 1, + 1, + 1, + 1, + 1, + ], + }, + big_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 1 (modified), + 1 (modified), + 1, + 1, + 0, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::sim_trace_as_string, + instantiated: Module { + name: sim_trace_as_string, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::sim_trace_as_string, + instantiated: Module { + name: sim_trace_as_string, + .. + }, + }.clk, + Instance { + name: ::sim_trace_as_string, + instantiated: Module { + name: sim_trace_as_string, + .. + }, + }.read, + Instance { + name: ::sim_trace_as_string, + instantiated: Module { + name: sim_trace_as_string, + .. + }, + }.write, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::sim_trace_as_string, + instantiated: Module { + name: sim_trace_as_string, + .. + }, + }.clk, + Instance { + name: ::sim_trace_as_string, + instantiated: Module { + name: sim_trace_as_string, + .. + }, + }.read, + Instance { + name: ::sim_trace_as_string, + instantiated: Module { + name: sim_trace_as_string, + .. + }, + }.read.addr, + Instance { + name: ::sim_trace_as_string, + instantiated: Module { + name: sim_trace_as_string, + .. + }, + }.read.clk, + Instance { + name: ::sim_trace_as_string, + instantiated: Module { + name: sim_trace_as_string, + .. + }, + }.read.data, + Instance { + name: ::sim_trace_as_string, + instantiated: Module { + name: sim_trace_as_string, + .. + }, + }.read.data., + Instance { + name: ::sim_trace_as_string, + instantiated: Module { + name: sim_trace_as_string, + .. + }, + }.read.data.[0], + Instance { + name: ::sim_trace_as_string, + instantiated: Module { + name: sim_trace_as_string, + .. + }, + }.read.data.[1], + Instance { + name: ::sim_trace_as_string, + instantiated: Module { + name: sim_trace_as_string, + .. + }, + }.read.en, + Instance { + name: ::sim_trace_as_string, + instantiated: Module { + name: sim_trace_as_string, + .. + }, + }.write, + Instance { + name: ::sim_trace_as_string, + instantiated: Module { + name: sim_trace_as_string, + .. + }, + }.write.addr, + Instance { + name: ::sim_trace_as_string, + instantiated: Module { + name: sim_trace_as_string, + .. + }, + }.write.clk, + Instance { + name: ::sim_trace_as_string, + instantiated: Module { + name: sim_trace_as_string, + .. + }, + }.write.data, + Instance { + name: ::sim_trace_as_string, + instantiated: Module { + name: sim_trace_as_string, + .. + }, + }.write.data[0], + Instance { + name: ::sim_trace_as_string, + instantiated: Module { + name: sim_trace_as_string, + .. + }, + }.write.data[0]., + Instance { + name: ::sim_trace_as_string, + instantiated: Module { + name: sim_trace_as_string, + .. + }, + }.write.data[1], + Instance { + name: ::sim_trace_as_string, + instantiated: Module { + name: sim_trace_as_string, + .. + }, + }.write.data[1]., + Instance { + name: ::sim_trace_as_string, + instantiated: Module { + name: sim_trace_as_string, + .. + }, + }.write.en, + Instance { + name: ::sim_trace_as_string, + instantiated: Module { + name: sim_trace_as_string, + .. + }, + }.write.mask, + Instance { + name: ::sim_trace_as_string, + instantiated: Module { + name: sim_trace_as_string, + .. + }, + }.write.mask[0], + Instance { + name: ::sim_trace_as_string, + instantiated: Module { + name: sim_trace_as_string, + .. + }, + }.write.mask[1], + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "sim_trace_as_string", + children: [ + TraceModuleIO { + name: "clk", + child: TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + ty: Clock, + flow: Source, + }, + TraceModuleIO { + name: "read", + child: TraceBundle { + name: "read", + fields: [ + TraceUInt { + location: TraceScalarId(1), + name: "addr", + ty: UInt<8>, + flow: Source, + }, + TraceBool { + location: TraceScalarId(2), + name: "en", + flow: Source, + }, + TraceClock { + location: TraceScalarId(3), + name: "clk", + flow: Source, + }, + TraceTraceAsString { + location: TraceScalarId(4), + name: "data", + ty: TraceAsString { + inner_ty: Array), FmtError}, 2>, + .. + }, + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<8>, + /* offset = 8 */ + en: Bool, + /* offset = 9 */ + clk: Clock, + #[hdl(flip)] /* offset = 10 */ + data: TraceAsString { + inner_ty: Array), FmtError}, 2>, + .. + }, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<8>, + /* offset = 8 */ + en: Bool, + /* offset = 9 */ + clk: Clock, + #[hdl(flip)] /* offset = 10 */ + data: TraceAsString { + inner_ty: Array), FmtError}, 2>, + .. + }, + }, + flow: Source, + }, + TraceModuleIO { + name: "write", + child: TraceBundle { + name: "write", + fields: [ + TraceUInt { + location: TraceScalarId(5), + name: "addr", + ty: UInt<8>, + flow: Source, + }, + TraceBool { + location: TraceScalarId(6), + name: "en", + flow: Source, + }, + TraceClock { + location: TraceScalarId(7), + name: "clk", + flow: Source, + }, + TraceArray { + name: "data", + elements: [ + TraceTraceAsString { + location: TraceScalarId(8), + name: "[0]", + ty: TraceAsString { + inner_ty: Enum { + Text(UInt<512>), + FmtError, + }, + .. + }, + flow: Source, + }, + TraceTraceAsString { + location: TraceScalarId(9), + name: "[1]", + ty: TraceAsString { + inner_ty: Enum { + Text(UInt<512>), + FmtError, + }, + .. + }, + flow: Source, + }, + ], + ty: Array), FmtError}, .. }, 2>, + flow: Source, + }, + TraceArray { + name: "mask", + elements: [ + TraceBool { + location: TraceScalarId(10), + name: "[0]", + flow: Source, + }, + TraceBool { + location: TraceScalarId(11), + name: "[1]", + flow: Source, + }, + ], + ty: Array, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<8>, + /* offset = 8 */ + en: Bool, + /* offset = 9 */ + clk: Clock, + /* offset = 10 */ + data: Array), FmtError}, .. }, 2>, + /* offset = 1036 */ + mask: Array, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<8>, + /* offset = 8 */ + en: Bool, + /* offset = 9 */ + clk: Clock, + /* offset = 10 */ + data: Array), FmtError}, .. }, 2>, + /* offset = 1036 */ + mask: Array, + }, + flow: Source, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 1026, + element_type: TraceArray { + name: "mem", + elements: [ + TraceTraceAsString { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 4, + stride: 1026, + start: 0, + len: 513, + }, + name: "[0]", + ty: TraceAsString { + inner_ty: Enum { + Text(UInt<512>), + FmtError, + }, + .. + }, + flow: Duplex, + }, + TraceTraceAsString { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 4, + stride: 1026, + start: 513, + len: 513, + }, + name: "[1]", + ty: TraceAsString { + inner_ty: Enum { + Text(UInt<512>), + FmtError, + }, + .. + }, + flow: Duplex, + }, + ], + ty: Array), FmtError}, .. }, 2>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(12), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(13), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(14), + name: "clk", + flow: Sink, + }, + TraceArray { + name: "data", + elements: [ + TraceTraceAsString { + location: TraceScalarId(15), + name: "[0]", + ty: TraceAsString { + inner_ty: Enum { + Text(UInt<512>), + FmtError, + }, + .. + }, + flow: Source, + }, + TraceTraceAsString { + location: TraceScalarId(16), + name: "[1]", + ty: TraceAsString { + inner_ty: Enum { + Text(UInt<512>), + FmtError, + }, + .. + }, + flow: Source, + }, + ], + ty: Array), FmtError}, .. }, 2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: Array), FmtError}, .. }, 2>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: Array), FmtError}, .. }, 2>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(17), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(18), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(19), + name: "clk", + flow: Sink, + }, + TraceArray { + name: "data", + elements: [ + TraceTraceAsString { + location: TraceScalarId(20), + name: "[0]", + ty: TraceAsString { + inner_ty: Enum { + Text(UInt<512>), + FmtError, + }, + .. + }, + flow: Sink, + }, + TraceTraceAsString { + location: TraceScalarId(21), + name: "[1]", + ty: TraceAsString { + inner_ty: Enum { + Text(UInt<512>), + FmtError, + }, + .. + }, + flow: Sink, + }, + ], + ty: Array), FmtError}, .. }, 2>, + flow: Sink, + }, + TraceArray { + name: "mask", + elements: [ + TraceBool { + location: TraceScalarId(22), + name: "[0]", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(23), + name: "[1]", + flow: Sink, + }, + ], + ty: Array, + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: Array), FmtError}, .. }, 2>, + /* offset = 1030 */ + mask: Array, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: Array), FmtError}, .. }, 2>, + /* offset = 1030 */ + mask: Array, + }, + }, + ], + array_type: Array), FmtError}, .. }, 2>, 4>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigUInt { + index: StatePartIndex(1), + ty: UInt<8>, + }, + maybe_changed: false, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(2), + kind: BigBool { + index: StatePartIndex(2), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigClock { + index: StatePartIndex(3), + }, + maybe_changed: false, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(4), + kind: TraceAsString { + layout: CompiledTypeLayout { + ty: TraceAsString { + inner_ty: Array), FmtError}, 2>, + .. + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 2, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.data[0]", + ty: Enum { + Text(UInt<512>), + FmtError, + }, + }, + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.data[1]", + ty: Enum { + Text(UInt<512>), + FmtError, + }, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Transparent { + inner: CompiledTypeLayout { + ty: Array), FmtError}, 2>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 2, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.data[0]", + ty: Enum { + Text(UInt<512>), + FmtError, + }, + }, + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.data[1]", + ty: Enum { + Text(UInt<512>), + FmtError, + }, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Array { + elements_non_empty: [ + CompiledTypeLayout { + ty: Enum { + Text(UInt<512>), + FmtError, + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.data[0]", + ty: Enum { + Text(UInt<512>), + FmtError, + }, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + CompiledTypeLayout { + ty: Enum { + Text(UInt<512>), + FmtError, + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.data[1]", + ty: Enum { + Text(UInt<512>), + FmtError, + }, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + ], + }, + }, + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 4, len: 2 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + }, + maybe_changed: true, + state: OpaqueSimValue { + bits: 0x200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001_u1026, + sim_only_values: [], + }, + last_state: OpaqueSimValue { + bits: 0x174C56D74C56DB595B400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000BA60B6BA62B6DACADA_u1026, + sim_only_values: [], + }, + }, + SimTrace { + id: TraceScalarId(5), + kind: BigUInt { + index: StatePartIndex(6), + ty: UInt<8>, + }, + maybe_changed: false, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigBool { + index: StatePartIndex(7), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigClock { + index: StatePartIndex(8), + }, + maybe_changed: false, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: TraceAsString { + layout: CompiledTypeLayout { + ty: TraceAsString { + inner_ty: Enum { + Text(UInt<512>), + FmtError, + }, + .. + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.data[0]", + ty: Enum { + Text(UInt<512>), + FmtError, + }, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Transparent { + inner: CompiledTypeLayout { + ty: Enum { + Text(UInt<512>), + FmtError, + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.data[0]", + ty: Enum { + Text(UInt<512>), + FmtError, + }, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 9, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + }, + maybe_changed: true, + state: OpaqueSimValue { + bits: 0x1_u513, + sim_only_values: [], + }, + last_state: OpaqueSimValue { + bits: 0x1_u513, + sim_only_values: [], + }, + }, + SimTrace { + id: TraceScalarId(9), + kind: TraceAsString { + layout: CompiledTypeLayout { + ty: TraceAsString { + inner_ty: Enum { + Text(UInt<512>), + FmtError, + }, + .. + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.data[1]", + ty: Enum { + Text(UInt<512>), + FmtError, + }, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Transparent { + inner: CompiledTypeLayout { + ty: Enum { + Text(UInt<512>), + FmtError, + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.data[1]", + ty: Enum { + Text(UInt<512>), + FmtError, + }, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 10, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + }, + maybe_changed: true, + state: OpaqueSimValue { + bits: 0x1_u513, + sim_only_values: [], + }, + last_state: OpaqueSimValue { + bits: 0x1_u513, + sim_only_values: [], + }, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(11), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigBool { + index: StatePartIndex(12), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(13), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigBool { + index: StatePartIndex(14), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigClock { + index: StatePartIndex(15), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(15), + kind: TraceAsString { + layout: CompiledTypeLayout { + ty: TraceAsString { + inner_ty: Enum { + Text(UInt<512>), + FmtError, + }, + .. + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.data[0]", + ty: Enum { + Text(UInt<512>), + FmtError, + }, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Transparent { + inner: CompiledTypeLayout { + ty: Enum { + Text(UInt<512>), + FmtError, + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.data[0]", + ty: Enum { + Text(UInt<512>), + FmtError, + }, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 16, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + }, + maybe_changed: true, + state: OpaqueSimValue { + bits: 0x1_u513, + sim_only_values: [], + }, + last_state: OpaqueSimValue { + bits: 0xBA60B6BA62B6DACADA_u513, + sim_only_values: [], + }, + }, + SimTrace { + id: TraceScalarId(16), + kind: TraceAsString { + layout: CompiledTypeLayout { + ty: TraceAsString { + inner_ty: Enum { + Text(UInt<512>), + FmtError, + }, + .. + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.data[1]", + ty: Enum { + Text(UInt<512>), + FmtError, + }, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Transparent { + inner: CompiledTypeLayout { + ty: Enum { + Text(UInt<512>), + FmtError, + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.data[1]", + ty: Enum { + Text(UInt<512>), + FmtError, + }, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 17, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + }, + maybe_changed: true, + state: OpaqueSimValue { + bits: 0x1_u513, + sim_only_values: [], + }, + last_state: OpaqueSimValue { + bits: 0xBA62B6BA62B6DACADA_u513, + sim_only_values: [], + }, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<2>, + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigBool { + index: StatePartIndex(19), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigClock { + index: StatePartIndex(20), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(20), + kind: TraceAsString { + layout: CompiledTypeLayout { + ty: TraceAsString { + inner_ty: Enum { + Text(UInt<512>), + FmtError, + }, + .. + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.data[0]", + ty: Enum { + Text(UInt<512>), + FmtError, + }, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Transparent { + inner: CompiledTypeLayout { + ty: Enum { + Text(UInt<512>), + FmtError, + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.data[0]", + ty: Enum { + Text(UInt<512>), + FmtError, + }, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 5, len: 0 }, + big_slots: StatePartIndexRange { start: 21, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + }, + maybe_changed: true, + state: OpaqueSimValue { + bits: 0x1_u513, + sim_only_values: [], + }, + last_state: OpaqueSimValue { + bits: 0x1_u513, + sim_only_values: [], + }, + }, + SimTrace { + id: TraceScalarId(21), + kind: TraceAsString { + layout: CompiledTypeLayout { + ty: TraceAsString { + inner_ty: Enum { + Text(UInt<512>), + FmtError, + }, + .. + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.data[1]", + ty: Enum { + Text(UInt<512>), + FmtError, + }, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Transparent { + inner: CompiledTypeLayout { + ty: Enum { + Text(UInt<512>), + FmtError, + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.data[1]", + ty: Enum { + Text(UInt<512>), + FmtError, + }, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 5, len: 0 }, + big_slots: StatePartIndexRange { start: 22, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + }, + maybe_changed: true, + state: OpaqueSimValue { + bits: 0x1_u513, + sim_only_values: [], + }, + last_state: OpaqueSimValue { + bits: 0x1_u513, + sim_only_values: [], + }, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(23), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(24), + }, + maybe_changed: true, + state: 0x1, + last_state: 0x1, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 1026, + element_type: TraceArray { + name: "mem", + elements: [ + TraceTraceAsString { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 4, + stride: 1026, + start: 0, + len: 513, + }, + name: "[0]", + ty: TraceAsString { + inner_ty: Enum { + Text(UInt<512>), + FmtError, + }, + .. + }, + flow: Duplex, + }, + TraceTraceAsString { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 4, + stride: 1026, + start: 513, + len: 513, + }, + name: "[1]", + ty: TraceAsString { + inner_ty: Enum { + Text(UInt<512>), + FmtError, + }, + .. + }, + flow: Duplex, + }, + ], + ty: Array), FmtError}, .. }, 2>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(12), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(13), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(14), + name: "clk", + flow: Sink, + }, + TraceArray { + name: "data", + elements: [ + TraceTraceAsString { + location: TraceScalarId(15), + name: "[0]", + ty: TraceAsString { + inner_ty: Enum { + Text(UInt<512>), + FmtError, + }, + .. + }, + flow: Source, + }, + TraceTraceAsString { + location: TraceScalarId(16), + name: "[1]", + ty: TraceAsString { + inner_ty: Enum { + Text(UInt<512>), + FmtError, + }, + .. + }, + flow: Source, + }, + ], + ty: Array), FmtError}, .. }, 2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: Array), FmtError}, .. }, 2>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: Array), FmtError}, .. }, 2>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(17), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(18), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(19), + name: "clk", + flow: Sink, + }, + TraceArray { + name: "data", + elements: [ + TraceTraceAsString { + location: TraceScalarId(20), + name: "[0]", + ty: TraceAsString { + inner_ty: Enum { + Text(UInt<512>), + FmtError, + }, + .. + }, + flow: Sink, + }, + TraceTraceAsString { + location: TraceScalarId(21), + name: "[1]", + ty: TraceAsString { + inner_ty: Enum { + Text(UInt<512>), + FmtError, + }, + .. + }, + flow: Sink, + }, + ], + ty: Array), FmtError}, .. }, 2>, + flow: Sink, + }, + TraceArray { + name: "mask", + elements: [ + TraceBool { + location: TraceScalarId(22), + name: "[0]", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(23), + name: "[1]", + flow: Sink, + }, + ], + ty: Array, + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: Array), FmtError}, .. }, 2>, + /* offset = 1030 */ + mask: Array, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: Array), FmtError}, .. }, 2>, + /* offset = 1030 */ + mask: Array, + }, + }, + ], + array_type: Array), FmtError}, .. }, 2>, 4>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(1), + StatePartIndex(6), + ], + event_queue: EventQueue(EventQueueData { + instant: 7 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/sim_trace_as_string.vcd b/crates/fayalite/tests/sim/expected/sim_trace_as_string.vcd new file mode 100644 index 0000000..3338905 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/sim_trace_as_string.vcd @@ -0,0 +1,221 @@ +$timescale 1 ps $end +$scope module sim_trace_as_string $end +$var wire 1 J(7*b clk $end +$scope struct read $end +$var wire 8 @t0}\ addr $end +$var wire 1 78"T5 en $end +$var wire 1 G7v@m clk $end +$var string 1 F&^FN data $end +$upscope $end +$scope struct write $end +$var wire 8 "fUdW addr $end +$var wire 1 r1OK) en $end +$var wire 1 ,ADvU clk $end +$scope struct data $end +$var string 1 pD.mP \[0] $end +$var string 1 !V!em \[1] $end +$upscope $end +$scope struct mask $end +$var wire 1 l8dgD \[0] $end +$var wire 1 1/sDs \[1] $end +$upscope $end +$upscope $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$scope struct mem $end +$var string 1 sz>#| \[0] $end +$var string 1 G._83 \[1] $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$scope struct mem $end +$var string 1 2r3#W \[0] $end +$var string 1 AbGF% \[1] $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$scope struct mem $end +$var string 1 .^<$p \[0] $end +$var string 1 ?s@Dc \[1] $end +$upscope $end +$upscope $end +$scope struct \[3] $end +$scope struct mem $end +$var string 1 {*||o \[0] $end +$var string 1 Bg,vB \[1] $end +$upscope $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 2 .0()- addr $end +$var wire 1 GEbRA en $end +$var wire 1 ;`9BK clk $end +$scope struct data $end +$var string 1 _Xe"P \[0] $end +$var string 1 jXrsx \[1] $end +$upscope $end +$upscope $end +$scope struct w1 $end +$var wire 2 '8u?z addr $end +$var wire 1 ~o=`& en $end +$var wire 1 *q>M1 clk $end +$scope struct data $end +$var string 1 N\zBe \[0] $end +$var string 1 c3h8{ \[1] $end +$upscope $end +$scope struct mask $end +$var wire 1 .SYGD \[0] $end +$var wire 1 />wYd \[1] $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$enddefinitions $end +$dumpvars +s sz>#| +s G._83 +s 2r3#W +s AbGF% +s .^<$p +s ?s@Dc +s {*||o +s Bg,vB +0J(7*b +b0 @t0}\ +078"T5 +0G7v@m +s[,\x20] F&^FN +b0 "fUdW +0r1OK) +0,ADvU +s pD.mP +s !V!em +0l8dgD +01/sDs +b0 .0()- +0GEbRA +0;`9BK +s _Xe"P +s jXrsx +b0 '8u?z +0~o=`& +0*q>M1 +s N\zBe +s c3h8{ +0.SYGD +0/>wYd +$end +#500000 +1J(7*b +1;`9BK +1*q>M1 +#1000000 +0J(7*b +1r1OK) +smem[0][0] pD.mP +smem[0][1] !V!em +1l8dgD +11/sDs +0;`9BK +1~o=`& +0*q>M1 +smem[0][0] N\zBe +smem[0][1] c3h8{ +1.SYGD +1/>wYd +#1500000 +smem[0][0] sz>#| +smem[0][1] G._83 +1J(7*b +1;`9BK +1*q>M1 +#2000000 +0J(7*b +b1 "fUdW +smem[1][0] pD.mP +smem[1][1] !V!em +0;`9BK +b1 '8u?z +0*q>M1 +smem[1][0] N\zBe +smem[1][1] c3h8{ +#2500000 +smem[1][0] 2r3#W +smem[1][1] AbGF% +1J(7*b +1;`9BK +1*q>M1 +#3000000 +0J(7*b +b10 "fUdW +smem[2][0] pD.mP +smem[2][1] !V!em +0;`9BK +b10 '8u?z +0*q>M1 +smem[2][0] N\zBe +smem[2][1] c3h8{ +#3500000 +smem[2][0] .^<$p +smem[2][1] ?s@Dc +1J(7*b +1;`9BK +1*q>M1 +#4000000 +0J(7*b +b11 "fUdW +smem[3][0] pD.mP +smem[3][1] !V!em +0;`9BK +b11 '8u?z +0*q>M1 +smem[3][0] N\zBe +smem[3][1] c3h8{ +#4500000 +smem[3][0] {*||o +smem[3][1] Bg,vB +1J(7*b +1;`9BK +1*q>M1 +#5000000 +0J(7*b +b1 @t0}\ +178"T5 +s[mem[1][0],\x20mem[1][1]] F&^FN +b0 "fUdW +0r1OK) +s pD.mP +s !V!em +b1 .0()- +1GEbRA +0;`9BK +smem[1][0] _Xe"P +smem[1][1] jXrsx +b0 '8u?z +0~o=`& +0*q>M1 +s N\zBe +s c3h8{ +#5500000 +1J(7*b +1;`9BK +1*q>M1 +#6000000 +0J(7*b +b1 "fUdW +1r1OK) +0;`9BK +b1 '8u?z +1~o=`& +0*q>M1 +#6500000 +s 2r3#W +s AbGF% +1J(7*b +s F&^FN +1;`9BK +s _Xe"P +s jXrsx +1*q>M1 +#7000000 diff --git a/crates/fayalite/tests/ui/simvalue_is_not_internable.stderr b/crates/fayalite/tests/ui/simvalue_is_not_internable.stderr index 7191e5e..8eff725 100644 --- a/crates/fayalite/tests/ui/simvalue_is_not_internable.stderr +++ b/crates/fayalite/tests/ui/simvalue_is_not_internable.stderr @@ -1,107 +1,107 @@ error[E0277]: `Cell` cannot be shared between threads safely - --> tests/ui/simvalue_is_not_internable.rs:11:26 - | -11 | fn f(v: SimValue<()>) -> Interned> { - | ^^^^^^^^^^^^^^^^^^^^^^ `Cell` cannot be shared between threads safely - | - = help: within `fayalite::prelude::SimValue<()>`, the trait `Sync` is not implemented for `Cell` - = note: if you want to do aliasing and mutation between multiple threads, use `std::sync::RwLock` + --> tests/ui/simvalue_is_not_internable.rs:11:26 + | + 11 | fn f(v: SimValue<()>) -> Interned> { + | ^^^^^^^^^^^^^^^^^^^^^^ `Cell` cannot be shared between threads safely + | + = help: within `fayalite::prelude::SimValue<()>`, the trait `Sync` is not implemented for `Cell` + = note: if you want to do aliasing and mutation between multiple threads, use `std::sync::RwLock` note: required because it appears within the type `util::alternating_cell::AlternatingCell>` - --> src/util/alternating_cell.rs - | - | pub(crate) struct AlternatingCell { - | ^^^^^^^^^^^^^^^ + --> src/util/alternating_cell.rs + | + 22 | pub(crate) struct AlternatingCell { + | ^^^^^^^^^^^^^^^ note: required because it appears within the type `fayalite::prelude::SimValue<()>` - --> src/sim/value.rs - | - | pub struct SimValue { - | ^^^^^^^^ + --> src/sim/value.rs + | + | pub struct SimValue { + | ^^^^^^^^ note: required by a bound in `fayalite::intern::Interned` - --> src/intern.rs - | - | pub struct Interned { - | ^^^^ required by this bound in `Interned` + --> src/intern.rs + | + | pub struct Interned { + | ^^^^ required by this bound in `Interned` error[E0277]: `UnsafeCell>` cannot be shared between threads safely - --> tests/ui/simvalue_is_not_internable.rs:11:26 - | -11 | fn f(v: SimValue<()>) -> Interned> { - | ^^^^^^^^^^^^^^^^^^^^^^ `UnsafeCell>` cannot be shared between threads safely - | - = help: within `fayalite::prelude::SimValue<()>`, the trait `Sync` is not implemented for `UnsafeCell>` + --> tests/ui/simvalue_is_not_internable.rs:11:26 + | + 11 | fn f(v: SimValue<()>) -> Interned> { + | ^^^^^^^^^^^^^^^^^^^^^^ `UnsafeCell>` cannot be shared between threads safely + | + = help: within `fayalite::prelude::SimValue<()>`, the trait `Sync` is not implemented for `UnsafeCell>` note: required because it appears within the type `util::alternating_cell::AlternatingCell>` - --> src/util/alternating_cell.rs - | - | pub(crate) struct AlternatingCell { - | ^^^^^^^^^^^^^^^ + --> src/util/alternating_cell.rs + | + 22 | pub(crate) struct AlternatingCell { + | ^^^^^^^^^^^^^^^ note: required because it appears within the type `fayalite::prelude::SimValue<()>` - --> src/sim/value.rs - | - | pub struct SimValue { - | ^^^^^^^^ + --> src/sim/value.rs + | + | pub struct SimValue { + | ^^^^^^^^ note: required by a bound in `fayalite::intern::Interned` - --> src/intern.rs - | - | pub struct Interned { - | ^^^^ required by this bound in `Interned` + --> src/intern.rs + | + | pub struct Interned { + | ^^^^ required by this bound in `Interned` error[E0277]: `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` cannot be sent between threads safely - --> tests/ui/simvalue_is_not_internable.rs:11:26 - | -11 | fn f(v: SimValue<()>) -> Interned> { - | ^^^^^^^^^^^^^^^^^^^^^^ `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` cannot be sent between threads safely - | - = help: within `fayalite::prelude::SimValue<()>`, the trait `Send` is not implemented for `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` + --> tests/ui/simvalue_is_not_internable.rs:11:26 + | + 11 | fn f(v: SimValue<()>) -> Interned> { + | ^^^^^^^^^^^^^^^^^^^^^^ `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` cannot be sent between threads safely + | + = help: within `fayalite::prelude::SimValue<()>`, the trait `Send` is not implemented for `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` note: required because it appears within the type `DynSimOnlyValue` - --> src/sim/value/sim_only_value_unsafe.rs - | - | pub struct DynSimOnlyValue(Rc); - | ^^^^^^^^^^^^^^^ + --> src/sim/value/sim_only_value_unsafe.rs + | + 281 | pub struct DynSimOnlyValue(Rc); + | ^^^^^^^^^^^^^^^ note: required because it appears within the type `PhantomData` - --> $RUST/core/src/marker.rs - | - | pub struct PhantomData; - | ^^^^^^^^^^^ + --> $RUST/core/src/marker.rs + | + 819 | pub struct PhantomData; + | ^^^^^^^^^^^ note: required because it appears within the type `alloc::raw_vec::RawVec` - --> $RUST/alloc/src/raw_vec/mod.rs - | - | pub(crate) struct RawVec { - | ^^^^^^ + --> $RUST/alloc/src/raw_vec/mod.rs + | + 73 | pub(crate) struct RawVec { + | ^^^^^^ note: required because it appears within the type `Vec` - --> $RUST/alloc/src/vec/mod.rs - | - | pub struct Vec { - | ^^^ + --> $RUST/alloc/src/vec/mod.rs + | + 438 | pub struct Vec { + | ^^^ note: required because it appears within the type `OpaqueSimValue` - --> src/ty.rs - | - | pub struct OpaqueSimValue { - | ^^^^^^^^^^^^^^ + --> src/ty.rs + | + 896 | pub struct OpaqueSimValue { + | ^^^^^^^^^^^^^^ note: required because it appears within the type `value::SimValueInner<()>` - --> src/sim/value.rs - | - | struct SimValueInner { - | ^^^^^^^^^^^^^ + --> src/sim/value.rs + | + 51 | struct SimValueInner { + | ^^^^^^^^^^^^^ note: required because it appears within the type `UnsafeCell>` - --> $RUST/core/src/cell.rs - | - | pub struct UnsafeCell { - | ^^^^^^^^^^ + --> $RUST/core/src/cell.rs + | + | pub struct UnsafeCell { + | ^^^^^^^^^^ note: required because it appears within the type `util::alternating_cell::AlternatingCell>` - --> src/util/alternating_cell.rs - | - | pub(crate) struct AlternatingCell { - | ^^^^^^^^^^^^^^^ + --> src/util/alternating_cell.rs + | + 22 | pub(crate) struct AlternatingCell { + | ^^^^^^^^^^^^^^^ note: required because it appears within the type `fayalite::prelude::SimValue<()>` - --> src/sim/value.rs - | - | pub struct SimValue { - | ^^^^^^^^ + --> src/sim/value.rs + | + 160 | pub struct SimValue { + | ^^^^^^^^ note: required by a bound in `fayalite::intern::Interned` - --> src/intern.rs - | - | pub struct Interned { - | ^^^^ required by this bound in `Interned` + --> src/intern.rs + | + 648 | pub struct Interned { + | ^^^^ required by this bound in `Interned` error[E0277]: the trait bound `fayalite::prelude::SimValue<()>: Intern` is not satisfied --> tests/ui/simvalue_is_not_internable.rs:12:26 @@ -118,238 +118,238 @@ help: consider dereferencing here | + error[E0277]: `Cell` cannot be shared between threads safely - --> tests/ui/simvalue_is_not_internable.rs:12:26 - | -12 | Intern::intern_sized(v) - | -------------------- ^ `Cell` cannot be shared between threads safely - | | - | required by a bound introduced by this call - | - = help: within `fayalite::prelude::SimValue<()>`, the trait `Sync` is not implemented for `Cell` - = note: if you want to do aliasing and mutation between multiple threads, use `std::sync::RwLock` + --> tests/ui/simvalue_is_not_internable.rs:12:26 + | + 12 | Intern::intern_sized(v) + | -------------------- ^ `Cell` cannot be shared between threads safely + | | + | required by a bound introduced by this call + | + = help: within `fayalite::prelude::SimValue<()>`, the trait `Sync` is not implemented for `Cell` + = note: if you want to do aliasing and mutation between multiple threads, use `std::sync::RwLock` note: required because it appears within the type `util::alternating_cell::AlternatingCell>` - --> src/util/alternating_cell.rs - | - | pub(crate) struct AlternatingCell { - | ^^^^^^^^^^^^^^^ + --> src/util/alternating_cell.rs + | + 22 | pub(crate) struct AlternatingCell { + | ^^^^^^^^^^^^^^^ note: required because it appears within the type `fayalite::prelude::SimValue<()>` - --> src/sim/value.rs - | - | pub struct SimValue { - | ^^^^^^^^ + --> src/sim/value.rs + | + | pub struct SimValue { + | ^^^^^^^^ note: required by a bound in `intern_sized` - --> src/intern.rs - | - | pub trait Intern: Any + Send + Sync { - | ^^^^ required by this bound in `Intern::intern_sized` + --> src/intern.rs + | + | pub trait Intern: Any + Send + Sync { + | ^^^^ required by this bound in `Intern::intern_sized` ... - | fn intern_sized(self) -> Interned - | ------------ required by a bound in this associated function + | fn intern_sized(self) -> Interned + | ------------ required by a bound in this associated function help: consider dereferencing here - | -12 | Intern::intern_sized(*v) - | + + | + 12 | Intern::intern_sized(*v) + | + error[E0277]: `UnsafeCell>` cannot be shared between threads safely - --> tests/ui/simvalue_is_not_internable.rs:12:26 - | -12 | Intern::intern_sized(v) - | -------------------- ^ `UnsafeCell>` cannot be shared between threads safely - | | - | required by a bound introduced by this call - | - = help: within `fayalite::prelude::SimValue<()>`, the trait `Sync` is not implemented for `UnsafeCell>` + --> tests/ui/simvalue_is_not_internable.rs:12:26 + | + 12 | Intern::intern_sized(v) + | -------------------- ^ `UnsafeCell>` cannot be shared between threads safely + | | + | required by a bound introduced by this call + | + = help: within `fayalite::prelude::SimValue<()>`, the trait `Sync` is not implemented for `UnsafeCell>` note: required because it appears within the type `util::alternating_cell::AlternatingCell>` - --> src/util/alternating_cell.rs - | - | pub(crate) struct AlternatingCell { - | ^^^^^^^^^^^^^^^ + --> src/util/alternating_cell.rs + | + 22 | pub(crate) struct AlternatingCell { + | ^^^^^^^^^^^^^^^ note: required because it appears within the type `fayalite::prelude::SimValue<()>` - --> src/sim/value.rs - | - | pub struct SimValue { - | ^^^^^^^^ + --> src/sim/value.rs + | + | pub struct SimValue { + | ^^^^^^^^ note: required by a bound in `intern_sized` - --> src/intern.rs - | - | pub trait Intern: Any + Send + Sync { - | ^^^^ required by this bound in `Intern::intern_sized` + --> src/intern.rs + | + | pub trait Intern: Any + Send + Sync { + | ^^^^ required by this bound in `Intern::intern_sized` ... - | fn intern_sized(self) -> Interned - | ------------ required by a bound in this associated function + | fn intern_sized(self) -> Interned + | ------------ required by a bound in this associated function help: consider dereferencing here - | -12 | Intern::intern_sized(*v) - | + + | + 12 | Intern::intern_sized(*v) + | + error[E0277]: `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` cannot be sent between threads safely - --> tests/ui/simvalue_is_not_internable.rs:12:26 - | -12 | Intern::intern_sized(v) - | -------------------- ^ `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` cannot be sent between threads safely - | | - | required by a bound introduced by this call - | - = help: within `fayalite::prelude::SimValue<()>`, the trait `Send` is not implemented for `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` + --> tests/ui/simvalue_is_not_internable.rs:12:26 + | + 12 | Intern::intern_sized(v) + | -------------------- ^ `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` cannot be sent between threads safely + | | + | required by a bound introduced by this call + | + = help: within `fayalite::prelude::SimValue<()>`, the trait `Send` is not implemented for `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` note: required because it appears within the type `DynSimOnlyValue` - --> src/sim/value/sim_only_value_unsafe.rs - | - | pub struct DynSimOnlyValue(Rc); - | ^^^^^^^^^^^^^^^ + --> src/sim/value/sim_only_value_unsafe.rs + | + 281 | pub struct DynSimOnlyValue(Rc); + | ^^^^^^^^^^^^^^^ note: required because it appears within the type `PhantomData` - --> $RUST/core/src/marker.rs - | - | pub struct PhantomData; - | ^^^^^^^^^^^ + --> $RUST/core/src/marker.rs + | + 819 | pub struct PhantomData; + | ^^^^^^^^^^^ note: required because it appears within the type `alloc::raw_vec::RawVec` - --> $RUST/alloc/src/raw_vec/mod.rs - | - | pub(crate) struct RawVec { - | ^^^^^^ + --> $RUST/alloc/src/raw_vec/mod.rs + | + 73 | pub(crate) struct RawVec { + | ^^^^^^ note: required because it appears within the type `Vec` - --> $RUST/alloc/src/vec/mod.rs - | - | pub struct Vec { - | ^^^ + --> $RUST/alloc/src/vec/mod.rs + | + 438 | pub struct Vec { + | ^^^ note: required because it appears within the type `OpaqueSimValue` - --> src/ty.rs - | - | pub struct OpaqueSimValue { - | ^^^^^^^^^^^^^^ + --> src/ty.rs + | + 896 | pub struct OpaqueSimValue { + | ^^^^^^^^^^^^^^ note: required because it appears within the type `value::SimValueInner<()>` - --> src/sim/value.rs - | - | struct SimValueInner { - | ^^^^^^^^^^^^^ + --> src/sim/value.rs + | + 51 | struct SimValueInner { + | ^^^^^^^^^^^^^ note: required because it appears within the type `UnsafeCell>` - --> $RUST/core/src/cell.rs - | - | pub struct UnsafeCell { - | ^^^^^^^^^^ + --> $RUST/core/src/cell.rs + | + | pub struct UnsafeCell { + | ^^^^^^^^^^ note: required because it appears within the type `util::alternating_cell::AlternatingCell>` - --> src/util/alternating_cell.rs - | - | pub(crate) struct AlternatingCell { - | ^^^^^^^^^^^^^^^ + --> src/util/alternating_cell.rs + | + 22 | pub(crate) struct AlternatingCell { + | ^^^^^^^^^^^^^^^ note: required because it appears within the type `fayalite::prelude::SimValue<()>` - --> src/sim/value.rs - | - | pub struct SimValue { - | ^^^^^^^^ + --> src/sim/value.rs + | + 160 | pub struct SimValue { + | ^^^^^^^^ note: required by a bound in `intern_sized` - --> src/intern.rs - | - | pub trait Intern: Any + Send + Sync { - | ^^^^ required by this bound in `Intern::intern_sized` + --> src/intern.rs + | + 596 | pub trait Intern: Any + Send + Sync { + | ^^^^ required by this bound in `Intern::intern_sized` ... - | fn intern_sized(self) -> Interned - | ------------ required by a bound in this associated function + 604 | fn intern_sized(self) -> Interned + | ------------ required by a bound in this associated function help: consider dereferencing here - | -12 | Intern::intern_sized(*v) - | + + | + 12 | Intern::intern_sized(*v) + | + error[E0277]: `Cell` cannot be shared between threads safely - --> tests/ui/simvalue_is_not_internable.rs:12:5 - | -12 | Intern::intern_sized(v) - | ^^^^^^^^^^^^^^^^^^^^^^^ `Cell` cannot be shared between threads safely - | - = help: within `fayalite::prelude::SimValue<()>`, the trait `Sync` is not implemented for `Cell` - = note: if you want to do aliasing and mutation between multiple threads, use `std::sync::RwLock` + --> tests/ui/simvalue_is_not_internable.rs:12:5 + | + 12 | Intern::intern_sized(v) + | ^^^^^^^^^^^^^^^^^^^^^^^ `Cell` cannot be shared between threads safely + | + = help: within `fayalite::prelude::SimValue<()>`, the trait `Sync` is not implemented for `Cell` + = note: if you want to do aliasing and mutation between multiple threads, use `std::sync::RwLock` note: required because it appears within the type `util::alternating_cell::AlternatingCell>` - --> src/util/alternating_cell.rs - | - | pub(crate) struct AlternatingCell { - | ^^^^^^^^^^^^^^^ + --> src/util/alternating_cell.rs + | + 22 | pub(crate) struct AlternatingCell { + | ^^^^^^^^^^^^^^^ note: required because it appears within the type `fayalite::prelude::SimValue<()>` - --> src/sim/value.rs - | - | pub struct SimValue { - | ^^^^^^^^ + --> src/sim/value.rs + | + | pub struct SimValue { + | ^^^^^^^^ note: required by a bound in `fayalite::intern::Interned` - --> src/intern.rs - | - | pub struct Interned { - | ^^^^ required by this bound in `Interned` + --> src/intern.rs + | + | pub struct Interned { + | ^^^^ required by this bound in `Interned` error[E0277]: `UnsafeCell>` cannot be shared between threads safely - --> tests/ui/simvalue_is_not_internable.rs:12:5 - | -12 | Intern::intern_sized(v) - | ^^^^^^^^^^^^^^^^^^^^^^^ `UnsafeCell>` cannot be shared between threads safely - | - = help: within `fayalite::prelude::SimValue<()>`, the trait `Sync` is not implemented for `UnsafeCell>` + --> tests/ui/simvalue_is_not_internable.rs:12:5 + | + 12 | Intern::intern_sized(v) + | ^^^^^^^^^^^^^^^^^^^^^^^ `UnsafeCell>` cannot be shared between threads safely + | + = help: within `fayalite::prelude::SimValue<()>`, the trait `Sync` is not implemented for `UnsafeCell>` note: required because it appears within the type `util::alternating_cell::AlternatingCell>` - --> src/util/alternating_cell.rs - | - | pub(crate) struct AlternatingCell { - | ^^^^^^^^^^^^^^^ + --> src/util/alternating_cell.rs + | + 22 | pub(crate) struct AlternatingCell { + | ^^^^^^^^^^^^^^^ note: required because it appears within the type `fayalite::prelude::SimValue<()>` - --> src/sim/value.rs - | - | pub struct SimValue { - | ^^^^^^^^ + --> src/sim/value.rs + | + | pub struct SimValue { + | ^^^^^^^^ note: required by a bound in `fayalite::intern::Interned` - --> src/intern.rs - | - | pub struct Interned { - | ^^^^ required by this bound in `Interned` + --> src/intern.rs + | + | pub struct Interned { + | ^^^^ required by this bound in `Interned` error[E0277]: `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` cannot be sent between threads safely - --> tests/ui/simvalue_is_not_internable.rs:12:5 - | -12 | Intern::intern_sized(v) - | ^^^^^^^^^^^^^^^^^^^^^^^ `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` cannot be sent between threads safely - | - = help: within `fayalite::prelude::SimValue<()>`, the trait `Send` is not implemented for `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` + --> tests/ui/simvalue_is_not_internable.rs:12:5 + | + 12 | Intern::intern_sized(v) + | ^^^^^^^^^^^^^^^^^^^^^^^ `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` cannot be sent between threads safely + | + = help: within `fayalite::prelude::SimValue<()>`, the trait `Send` is not implemented for `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` note: required because it appears within the type `DynSimOnlyValue` - --> src/sim/value/sim_only_value_unsafe.rs - | - | pub struct DynSimOnlyValue(Rc); - | ^^^^^^^^^^^^^^^ + --> src/sim/value/sim_only_value_unsafe.rs + | + 281 | pub struct DynSimOnlyValue(Rc); + | ^^^^^^^^^^^^^^^ note: required because it appears within the type `PhantomData` - --> $RUST/core/src/marker.rs - | - | pub struct PhantomData; - | ^^^^^^^^^^^ + --> $RUST/core/src/marker.rs + | + 819 | pub struct PhantomData; + | ^^^^^^^^^^^ note: required because it appears within the type `alloc::raw_vec::RawVec` - --> $RUST/alloc/src/raw_vec/mod.rs - | - | pub(crate) struct RawVec { - | ^^^^^^ + --> $RUST/alloc/src/raw_vec/mod.rs + | + 73 | pub(crate) struct RawVec { + | ^^^^^^ note: required because it appears within the type `Vec` - --> $RUST/alloc/src/vec/mod.rs - | - | pub struct Vec { - | ^^^ + --> $RUST/alloc/src/vec/mod.rs + | + 438 | pub struct Vec { + | ^^^ note: required because it appears within the type `OpaqueSimValue` - --> src/ty.rs - | - | pub struct OpaqueSimValue { - | ^^^^^^^^^^^^^^ + --> src/ty.rs + | + 896 | pub struct OpaqueSimValue { + | ^^^^^^^^^^^^^^ note: required because it appears within the type `value::SimValueInner<()>` - --> src/sim/value.rs - | - | struct SimValueInner { - | ^^^^^^^^^^^^^ + --> src/sim/value.rs + | + 51 | struct SimValueInner { + | ^^^^^^^^^^^^^ note: required because it appears within the type `UnsafeCell>` - --> $RUST/core/src/cell.rs - | - | pub struct UnsafeCell { - | ^^^^^^^^^^ + --> $RUST/core/src/cell.rs + | + | pub struct UnsafeCell { + | ^^^^^^^^^^ note: required because it appears within the type `util::alternating_cell::AlternatingCell>` - --> src/util/alternating_cell.rs - | - | pub(crate) struct AlternatingCell { - | ^^^^^^^^^^^^^^^ + --> src/util/alternating_cell.rs + | + 22 | pub(crate) struct AlternatingCell { + | ^^^^^^^^^^^^^^^ note: required because it appears within the type `fayalite::prelude::SimValue<()>` - --> src/sim/value.rs - | - | pub struct SimValue { - | ^^^^^^^^ + --> src/sim/value.rs + | + 160 | pub struct SimValue { + | ^^^^^^^^ note: required by a bound in `fayalite::intern::Interned` - --> src/intern.rs - | - | pub struct Interned { - | ^^^^ required by this bound in `Interned` + --> src/intern.rs + | + 648 | pub struct Interned { + | ^^^^ required by this bound in `Interned` diff --git a/crates/fayalite/visit_types.json b/crates/fayalite/visit_types.json index a74cef9..f3af962 100644 --- a/crates/fayalite/visit_types.json +++ b/crates/fayalite/visit_types.json @@ -51,7 +51,8 @@ "Reset": "Visible", "Clock": "Visible", "PhantomConst": "Visible", - "DynSimOnly": "Visible" + "DynSimOnly": "Visible", + "TraceAsString": "Visible" } }, "Bundle": { @@ -1021,6 +1022,27 @@ "fold_where": "T: Fold", "visit_where": "T: Visit" }, + "ops::ToTraceAsString": { + "data": { + "$kind": "Struct", + "$constructor": "ops::ToTraceAsString::new", + "inner()": "Visible", + "ty()": "Visible" + }, + "generics": "", + "fold_where": "T: Fold", + "visit_where": "T: Visit" + }, + "ops::TraceAsStringAsInner": { + "data": { + "$kind": "Struct", + "$constructor": "ops::TraceAsStringAsInner::new", + "arg_typed()": "Visible" + }, + "generics": "", + "fold_where": "T: Fold", + "visit_where": "T: Visit" + }, "BlockId": { "data": { "$kind": "Opaque" @@ -1283,12 +1305,25 @@ "$kind": "Struct" } }, + "TargetPathTraceAsStringInner": { + "data": { + "$kind": "Struct" + } + }, + "TargetPathToTraceAsString": { + "data": { + "$kind": "Struct", + "ty": "Visible" + } + }, "TargetPathElement": { "data": { "$kind": "Enum", "BundleField": "Visible", "ArrayElement": "Visible", - "DynArrayElement": "Visible" + "DynArrayElement": "Visible", + "TraceAsStringInner": "Visible", + "ToTraceAsString": "Visible" } }, "PhantomConst": { @@ -1306,6 +1341,14 @@ "data": { "$kind": "ManualImpl" } + }, + "TraceAsString": { + "data": { + "$kind": "ManualImpl" + }, + "generics": "", + "fold_where": "T: Fold", + "visit_where": "T: Visit" } } } \ No newline at end of file diff --git a/rocq-demo/.gitignore b/rocq-demo/.gitignore new file mode 100644 index 0000000..0182113 --- /dev/null +++ b/rocq-demo/.gitignore @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: LGPL-3.0-or-later +# See Notices.txt for copyright information +.CoqMakefile.d +*.aux +CoqMakefile +CoqMakefile.conf +*.glob +*.vo* diff --git a/rocq-demo/Makefile b/rocq-demo/Makefile new file mode 100644 index 0000000..d0d5c9e --- /dev/null +++ b/rocq-demo/Makefile @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: LGPL-3.0-or-later +# See Notices.txt for copyright information +# +# Example Makefile wrapper as given on the Rocq documentation +# https://rocq-prover.org/doc/V9.1.0/refman/practical-tools/utilities.html#building-a-rocq-project-with-rocq-makefile-details + +# KNOWNTARGETS will not be passed along to CoqMakefile +KNOWNTARGETS := CoqMakefile +# KNOWNFILES will not get implicit targets from the final rule, and so +# depending on them won't invoke the submake +# Warning: These files get declared as PHONY, so any targets depending +# on them always get rebuilt +KNOWNFILES := Makefile _CoqProject + +.DEFAULT_GOAL := invoke-coq-makefile + +CoqMakefile: Makefile _CoqProject + $(COQBIN)rocq makefile -f _CoqProject -o CoqMakefile + +invoke-coq-makefile: CoqMakefile + $(MAKE) --no-print-directory -f CoqMakefile $(filter-out $(KNOWNTARGETS),$(MAKECMDGOALS)) + +.PHONY: invoke-coq-makefile $(KNOWNFILES) + +#################################################################### +## Your targets here ## +#################################################################### + +# This should be the last rule, to handle any targets not declared above +%: invoke-coq-makefile + @true diff --git a/rocq-demo/_CoqProject b/rocq-demo/_CoqProject new file mode 100644 index 0000000..be10420 --- /dev/null +++ b/rocq-demo/_CoqProject @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: LGPL-3.0-or-later +# See Notices.txt for copyright information + +-Q . RocqDemo +. diff --git a/scripts/check-copyright.sh b/scripts/check-copyright.sh index 023cd21..99205bb 100755 --- a/scripts/check-copyright.sh +++ b/scripts/check-copyright.sh @@ -50,7 +50,7 @@ function main() /crates/fayalite/tests/ui/*.stderr|/crates/fayalite/tests/sim/expected/*.vcd|/crates/fayalite/tests/sim/expected/*.txt) # file that can't contain copyright header ;; - /.forgejo/workflows/*.yml|*/.gitignore|*.toml) + /.forgejo/workflows/*.yml|*/.gitignore|*.toml|*/Makefile|*/_CoqProject) check_file "$file" "${POUND_HEADER[@]}" ;; *.md)