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HaeckseAlex
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fayalite
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libre-chip/fayalite
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Jacob Lifshay
26224abe1c
sim: properly update all VCD wires when they share simulation state
2026-05-05 21:12:00 -07:00
Jacob Lifshay
402f457c68
sim: Speed up updating traces by tracking which traces are written to
2026-04-30 19:12:20 -07:00
Jacob Lifshay
2aa41137d4
add simulator tests for queue()
2026-03-24 23:30:15 -07:00