cpu/crates/cpu/tests/expected/reg_alloc.vcd

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$var wire 1 c0 invert_src0 $end
$var wire 1 d0 invert_carry_in $end
$var wire 1 e0 invert_carry_out $end
$var wire 1 f0 add_pc $end
$upscope $end
$scope struct Logical $end
$scope struct alu_common $end
$scope struct common $end
$var string 0 g0 prefix_pad $end
$scope struct dest $end
$var wire 4 h0 value $end
$upscope $end
$scope struct src $end
$var wire 6 i0 \[0] $end
$var wire 6 j0 \[1] $end
$var wire 6 k0 \[2] $end
$upscope $end
$var wire 25 l0 imm_low $end
$var wire 1 m0 imm_sign $end
$scope struct _phantom $end
$upscope $end
$upscope $end
$var string 1 n0 output_integer_mode $end
$upscope $end
$var wire 4 o0 lut $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
$dumpvars
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sReadL2Reg\x20(0) n&
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sHdlSome\x20(1) L'
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