forked from libre-chip/cpu
WIP fixing bugs
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59da0aec06
SSH key fingerprint:
SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
3 changed files with 38211 additions and 16198 deletions
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@ -771,7 +771,7 @@ impl FetchPipeQueueEntry {
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.rotate_left(32)
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.wrapping_mul(0x92B38C197608A6B) // random prime
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.rotate_right(60);
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(random % 8) as u8
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if random % 32 == 0 { 30 } else { 3 }
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}
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}
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@ -799,6 +799,12 @@ fn mock_fetch_pipe(config: PhantomConst<CpuConfig>, insns: MockInsns) {
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async |mut sim| {
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sim.write(from_fetch.fetch.ready, false).await;
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sim.write(from_fetch.cancel.ready, false).await;
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sim.write(
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from_fetch.next_fetch_block_ids,
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#[hdl(sim)]
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(from_fetch.next_fetch_block_ids.ty()).HdlNone(),
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)
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.await;
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sim.write(
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to_post_decode.inner.data,
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to_post_decode.ty().inner.data.HdlNone(),
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@ -840,12 +846,21 @@ fn mock_fetch_pipe(config: PhantomConst<CpuConfig>, insns: MockInsns) {
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let mut next_id = 0u32;
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loop {
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let mut sim_queue = queue_debug.ty().new_sim(FetchPipeQueueEntry.default_sim());
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let mut next_fetch_block_ids =
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from_fetch.next_fetch_block_ids.ty().HdlSome.new_sim(0u8);
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for entry in &queue {
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ArrayVec::try_push_sim(&mut sim_queue, entry)
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.ok()
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.expect("queue is known to be small enough");
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let _ = ArrayVec::try_push_sim(&mut next_fetch_block_ids, &entry.fetch_block_id);
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}
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sim.write(queue_debug, sim_queue).await;
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sim.write(
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from_fetch.next_fetch_block_ids,
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#[hdl(sim)]
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(from_fetch.next_fetch_block_ids.ty()).HdlSome(next_fetch_block_ids),
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)
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.await;
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if let Some(front) = queue.front().filter(|v| v.cycles_left.as_int() == 0) {
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#[hdl(sim)]
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let FetchPipeQueueEntry {
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@ -874,6 +889,7 @@ fn mock_fetch_pipe(config: PhantomConst<CpuConfig>, insns: MockInsns) {
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fetch_block_id,
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id: next_id.cast_to_static::<UInt<_>>(),
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pc,
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predicted_next_pc: 0u64,
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size_in_bytes: insn.byte_len().cast_to_static::<UInt<_>>(),
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kind: insn.wip_decoded_insn_kind(),
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};
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@ -890,6 +906,7 @@ fn mock_fetch_pipe(config: PhantomConst<CpuConfig>, insns: MockInsns) {
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fetch_block_id,
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id: next_id.cast_to_static::<UInt<_>>(),
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pc: start_pc,
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predicted_next_pc: 0u64,
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size_in_bytes: 0u8.cast_to_static::<UInt<_>>(),
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kind: WipDecodedInsnKind.Interrupt(DEMO_ILLEGAL_INSN_TRAP),
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},
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@ -917,10 +934,27 @@ fn mock_fetch_pipe(config: PhantomConst<CpuConfig>, insns: MockInsns) {
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.await;
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sim.write(from_fetch.cancel.ready, true).await;
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sim.wait_for_clock_edge(cd.clk).await;
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println!(
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"Dump mock fetch decode pipe queue: {:#?}",
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Vec::from_iter(queue.iter().map(|v| {
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DebugAsDisplay(format!(
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"fid={:#x} pc={:#x}",
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v.fetch_block_id.as_int(),
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v.start_pc.as_int(),
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))
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}))
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);
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if sim.read_past_bool(to_post_decode.inner.ready, cd.clk).await {
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#[hdl(sim)]
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if let HdlSome(_) = sim.read_past(to_post_decode.inner.data, cd.clk).await {
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queue.pop_front();
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let Some(v) = queue.pop_front() else {
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unreachable!();
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};
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println!(
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"mock fetch decode pipe queue pop: fid={:#x} pc={:#x}",
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v.fetch_block_id.as_int(),
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v.start_pc.as_int(),
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);
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}
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}
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for entry in &mut queue {
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@ -935,7 +969,14 @@ fn mock_fetch_pipe(config: PhantomConst<CpuConfig>, insns: MockInsns) {
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{
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// cancel in-progress fetches from newest to oldest
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for _ in 0..*in_progress_fetches_to_cancel {
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let _ = queue.pop_back();
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let Some(v) = queue.pop_back() else {
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unreachable!();
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};
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println!(
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"mock fetch decode pipe queue cancel unpush: fid={:#x} pc={:#x}",
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v.fetch_block_id.as_int(),
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v.start_pc.as_int(),
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);
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}
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}
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if !sim.read_past_bool(from_fetch.fetch.ready, cd.clk).await {
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@ -949,6 +990,11 @@ fn mock_fetch_pipe(config: PhantomConst<CpuConfig>, insns: MockInsns) {
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start_pc,
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fetch_block_id,
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} = &inner;
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println!(
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"mock fetch decode pipe queue push: fid={:#x} pc={:#x}",
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fetch_block_id.as_int(),
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start_pc.as_int(),
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);
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queue.push_back(
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#[hdl(sim)]
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FetchPipeQueueEntry {
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@ -979,7 +1025,8 @@ impl ExecuteRetirePipeQueueEntry {
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WipDecodedInsn {
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fetch_block_id: 0u8,
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id: 0_hdl_u12,
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pc: 0xEEEE_EEEE_EEEE_EEEEu64,
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pc: 0u64,
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predicted_next_pc: 0u64,
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size_in_bytes: 0_hdl_u4,
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kind: WipDecodedInsnKind.NonBranch(),
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},
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@ -996,7 +1043,13 @@ impl ExecuteRetirePipeQueueEntry {
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.rotate_left(32)
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.wrapping_mul(0x73161B54984B1C21) // random prime
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.rotate_right(60);
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(random % 16) as u8
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const DELAYS: &[u8; 0x20] = &[
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0, 0, 0, 0, 0, 0, 0, 0, //
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1, 1, 1, 1, 1, 1, 1, 1, //
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2, 2, 2, 2, 2, 2, 2, 2, //
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3, 3, 3, 3, 4, 5, 6, 50, // 50 for simulating a cache miss or something
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];
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DELAYS[(random & 0x1F) as usize]
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}
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}
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@ -1052,6 +1105,7 @@ impl MockExecuteState {
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fetch_block_id: &insn.fetch_block_id,
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id: &insn.id,
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pc,
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predicted_next_pc: &insn.predicted_next_pc,
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size_in_bytes: mock_insn.byte_len().cast_to_static::<UInt<4>>(),
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kind: mock_insn.wip_decoded_insn_kind(),
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};
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@ -1060,16 +1114,14 @@ impl MockExecuteState {
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"insn doesn't match expected:\ninsn: {insn:?}\nexpected insn: {expected_insn:?}"
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));
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}
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if let Some(next_insn) = self.queue.front() {
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if next_pc != next_insn.insn.pc.as_int() {
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self.canceling = true;
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if !passive {
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println!(
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"MockExecuteState: starting canceling {} instruction(s): next_pc={next_pc:#x}, mis-predicted next_pc={next_insn_pc}",
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self.queue.len(),
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next_insn_pc = next_insn.insn.pc
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);
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}
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if next_pc != insn.predicted_next_pc.as_int() {
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self.canceling = true;
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if !passive {
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println!(
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"MockExecuteState: starting canceling {} instruction(s): next_pc={next_pc:#x}, mis-predicted next_pc={}",
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self.queue.len(),
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insn.predicted_next_pc
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);
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}
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}
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Ok(
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@ -1130,6 +1182,10 @@ impl MockExecuteState {
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if !self.used_ids.insert(insn.id.clone()) {
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panic!("next_pc gave a duplicate insn id: {insn:?}");
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}
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println!(
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"MockExecutionState::start fid={} id={} pc={}",
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insn.fetch_block_id, insn.id, insn.pc
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);
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self.queue.push_back(
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#[hdl(sim)]
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ExecuteRetirePipeQueueEntry {
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@ -1187,6 +1243,7 @@ fn mock_execute_retire_pipe(
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cd,
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async |mut sim| {
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sim.write(from_post_decode.ready, 0usize).await;
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sim.write(from_post_decode.cancel.ready, false).await;
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sim.write(
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retire_output.inner.data,
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retire_output.ty().inner.data.HdlNone(),
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@ -1310,6 +1367,8 @@ fn mock_execute_retire_pipe(
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},
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)
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.await;
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sim.write(from_post_decode.cancel.ready, state.canceling)
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.await;
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sim.wait_for_clock_edge(cd.clk).await;
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println!(
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"Dump mock execute retire pipe queue: {:#?}",
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@ -1322,8 +1381,17 @@ fn mock_execute_retire_pipe(
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))
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}))
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);
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if state.canceling {
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state.finish_cancel();
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#[hdl(sim)]
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if let HdlSome(v) = sim.read_past(from_post_decode.cancel.data, cd.clk).await {
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#[hdl(sim)]
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let () = v;
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if sim
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.read_past_bool(from_post_decode.cancel.ready, cd.clk)
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.await
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{
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assert!(state.canceling);
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state.finish_cancel();
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}
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}
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if sim.read_past_bool(retire_output.inner.ready, cd.clk).await {
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for _ in 0..**ArrayVec::len_sim(&retiring) {
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@ -1339,7 +1407,7 @@ fn mock_execute_retire_pipe(
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&mut new_insns,
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*sim.read_past(from_post_decode.ready, cd.clk).await,
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);
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for insn in dbg!(ArrayVec::elements_sim_ref(&new_insns)) {
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for insn in ArrayVec::elements_sim_ref(&new_insns) {
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state.start(insn, delay_sequence_index);
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}
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}
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@ -1430,9 +1498,9 @@ fn test_next_pc() {
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};
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sim.write_clock(sim.io().cd.clk, false);
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sim.write_reset(sim.io().cd.rst, true);
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for _cycle in 0..500 {
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for cycle in 0..800 {
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sim.advance_time(SimDuration::from_nanos(500));
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println!("clock tick");
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println!("clock tick: {cycle}");
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sim.write_clock(sim.io().cd.clk, true);
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sim.advance_time(SimDuration::from_nanos(500));
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sim.write_clock(sim.io().cd.clk, false);
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